JPS62165341A - semiconductor equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a semiconductor device having multilayer wiring formed on a semiconductor circuit by a metal vapor deposition method.

<Prior art> A semiconductor hybrid integrated circuit consists of circuits with various functions on a single semiconductor substrate, and the wiring that connects these circuits is formed by a multilayer wiring circuit, wire bonding, or both (31). The circuit of such a semiconductor device is formed by sequentially forming predetermined multilayer wiring on a semiconductor substrate in accordance with the circuit design.The formation of such multilayer wiring involves forming an insulating layer by CVD on the circuit-formed substrate 1-. A conductor layer for forming a lower wiring is formed on this insulating layer by a PVD method or the like, and a lower wiring is formed by photoetching according to the lower wiring pattern.Next, a CVD method is applied thereon.

An insulating layer is formed in the same manner as above using the PVD method or the like. A conductor layer constituting the two-layer wiring is formed on the first layer, and then the conductor layer is removed by photo-I etching according to the first-layer wiring pattern, leaving only the conductor layer in the first-layer wiring pattern. If the conductor layer is made of aluminum, unnecessary portions are removed by etching with H3PO4 or the like. Further, when connecting upper and lower layer wiring with conductors, the connecting portion of the insulating layer applied on the lower layer wiring or under the upper layer wiring is removed in advance, and a conductive layer of the single layer wiring is formed thereon.

<Problems to be Solved by the Invention> FIG. 2 is a plan view of an intersection between upper and lower layer interconnections of an ideal multilayer interconnection formed on the second side of a semiconductor device as described below. As shown in FIG. 2, ideally, the multilayer wiring of a semiconductor device is formed by photo-etching, with the lower layer wiring 1 and the upper layer wiring 2 intersecting each other orthogonally through the second insulating layer on the substrate 3. It is formed. However, in reality, as shown in FIG. 3(a), when forming the upper layer wiring 2, the etching solution flows around along the resist at the step between the intersection of the f layer wiring 1 and the -L layer wiring 2. , the conductor portion of the wiring is further eroded deeply, and constrictions 2a occur at four locations. If this constriction 2a is severe, there is a risk of disconnection during formation of the upper layer wiring.

FIG. 3(b) is a sectional view taken along the line AA shown in FIG. 3(a). In FIG. 3(b), l is a lower layer wiring, 2 is a single layer wiring, 3 is a semiconductor substrate, 4 is an insulator layer on the semiconductor substrate 3, and 5 is an insulator layer provided between the upper and lower layer wirings 1 and 2. , 5
A is a stepped portion formed in the insulator layer 5 for the lower wiring 1.

As shown in FIGS. 3(a) and 3(b), in the conventional method, a constricted portion 2a is generated in the upper layer wiring 2 above the stepped portion 5a.

The present invention has been made in view of the deficiencies of the prior art, and it is an object of the present invention to provide a semiconductor device having multilayer wiring that is not affected by constrictions at stepped portions.

Means for Solving the Problems> The structure of the semiconductor device according to the present invention that achieves the above object is such that, in a semiconductor device having multilayer wiring formed on a substrate, the intersection angle θ between the lower layer wiring and the upper layer wiring is Oo <θ<8
It is characterized by being in the 0° range.

Function> In the multilayer wiring of the semiconductor device according to the present invention, since the intersection angle θ of the upper and lower wiring is maintained in the range of 0″<θ<80°, the step part of the insulator layer at the intersection with the lower wiring The effect of the constriction that occurs is smaller than when the lines are perpendicular to each other.This prevents disconnection of the upper layer wiring at the stepped portion.

Embodiment One embodiment of a semiconductor device according to the present invention will be described with reference to the drawings. FIG. 1 is a plan view of an intersection of multilayer interconnections of a semiconductor device according to the present invention. As shown in FIG. 1, in the multilayer wiring on the substrate 3 of the semiconductor device according to the present invention, the lower layer wiring 1 and the upper layer wiring 2 intersect at θ (0° and θ<90°), as shown in FIG. They are not orthogonal like the ones in . As a result, if the conductor layer of the wiring is d, then X=-7--.

Sln.

Therefore, the smaller the intersection angle θ is, the longer the step portion X becomes.

but, Generally, θ is 30° θ< so’ It is preferable that it is in the range of .

In the present invention, one of the multilayer interconnections, the lower interconnection 2.1, is θ
Because they cross at
The possibility of disconnection of the upper layer wiring 2 due to the constricted portion 2a of the upper layer wiring 2, which occurs when removing other layers by etching, has been significantly reduced. In addition, in the present invention, since the upper and lower layer wirings 2.1 of the multilayer wiring intersect at θ, the area S at the intersection of the upper and lower layer wirings is expressed as: The smaller θ is, the larger the area S is. Become. Therefore, when connecting the upper and lower layer wiring 2.1 with conductors, the area S of the hole or through hole connecting the upper layer wiring 2 and the lower layer wiring 1 can be increased, and the resistance of the connection portion between the upper and lower layer wiring 2.1 can be increased. can be made smaller.

<Effects of the Invention> According to the semiconductor device according to the present invention, the upper and lower layer wiring of the multilayer wiring formed on the semiconductor substrate is 0 (0°<0<90°).
Because they intersect with each other, the intersecting length of the first-layer wiring and the lower-layer wiring becomes longer, and the influence of the constriction at the stepped portion that occurs during the photo-etching process is reduced. Layered wiring is no longer cut at stepped portions. In addition, the area of the intersection between the upper layer wiring and the upper layer wiring can be increased, and therefore the connection area can be increased in the area where connection is required with the -1- lower layer wiring, and 1- The area where the upper layer wiring connects It also has the advantage of reducing resistance.

[Brief explanation of drawings]

FIG. 1 is a plan view of an intersection between upper and lower layer wiring of a multilayer wiring of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a W side view of an ideal intersection of upper and lower layer wiring of a multilayer wiring of a semiconductor device. FIG. 3(a) is a 1i diagram of an intersection of multilayer wiring in a conventional semiconductor device, and FIG. 3(b) is a cross-sectional view taken along the line A-A of FIG. 3(a). In the drawing, I is the lower layer wiring, 2 is the 1st layer wiring, 2d is the constriction, and 3 is the substrate.

Claims (2)

[Claims] (1) In a semiconductor device in which multilayer wiring is formed on a substrate by metal vapor deposition, the intersection angle θ between lower layer wiring and upper layer wiring
is in the range of 0°<θ<90°. (2) The semiconductor device according to claim 1, wherein the θ is in a range of 30°<θ<60°.