JPS62165253A - LSI with built-in non-volatile memory - Google Patents

Abstract

PURPOSE:To protect security of only the desired data by providing a security means which makes the access to a block from the external impossible when an address signal accesses this block corresponding to a security bit of a non- volatile memory. CONSTITUTION:Security bits b0-b7 corresponding to several blocks in 1:1 are provided for an EPROM 2 divided into these blocks. A decoder 4 is provided which decodes the address signal from the external and outputs a signal, which permits or inhibits the access to the address of the EPROM corresponding to a security bit, if the address signal accesses the address designated by this security bit. The address access to the EPROM is controlled to perform the write to the EPROM and the access inhibition for each block. Thus, security of only desired data out of data written in a non-volatile memory like an EPROM incorporated in an LSI is protected.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a memory access control technology and a technology that is particularly effective when applied to the security protection of data written in non-volatile memory. ROM (Read Only) in which programs for processing are stored.
Memory) is E P ROM (Erasable
The present invention relates to a technology that is effective for use in a one-chip microcomputer configured using e-programmable ROM.

[Prior Art] In an LSI with a built-in memory such as a single-chip microcomputer, there are cases where it is desired to protect data written in a memory such as an EPROM built into the chip. For example, in a single-chip microcontroller such as Intel's model number 8751, a security bit is provided and the EP
The data written to the EPROM is protected by preventing data once written to the ROM from being read.

[Problem to be solved by the invention] If data security is protected using the method described above, EF
There is a problem in that all the data stored in the ROM cannot be accessed from the outside, and it is not possible to read out part of the data stored in the EPROM.

An object of the present invention is to make it possible to securely protect only desired data among data written in an EPROM.

The above and other objects and novel features of the present invention will become clear from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

In other words, the EPR built into a single-chip microcontroller
The OM is considered to be divided into several blocks for each address, and the above EPR is used to allow or disable access to a desired block among the divided blocks.
A security bit is provided that corresponds one-to-one to each OM block. Further, means for decoding an address signal from the outside and outputting a signal that allows or disables access from the outside to the block corresponding to the security bit when the address signal is the address of the block specified by the security bit. It is intended to provide

[Function] According to the above-described means, writing to and access to the EPROM can be prohibited for each block divided by address, thereby achieving the above-mentioned purpose of protecting the confidentiality of desired data written in the EPROM. can be achieved.

[Embodiment] FIG. 1 shows a block diagram of an embodiment of a single-chip microcomputer to which the present invention is applied.

In the figure, although not particularly limited, each circuit block surrounded by a two-dot chain line 20 is formed on one semiconductor chip such as a single crystal silicon saw board.

The illustrated single-chip microcomputer includes a microprocessor 1, an EPROM 2 whose memory cells are semiconductor nonvolatile storage elements such as a FAMO 5, and an EPROM 2 having an information capacity of 16 bytes, which contains data to be protected. Specify the block in which the block is located. -b
A protection circuit 3 having an 8-bit or 1-byte semiconductor non-volatile memory element consisting of 7 decodes address information from the outside and, if the address is the address specified by the security byte, sends a data security signal. A decoder 4 that outputs σED, input/output ports 5, 6, and gates G1. G2. G3. Each circuit block is connected to each other via an address bus AB and a data bus DB.

Although the specific configuration of the EPROM 2 is not shown in this embodiment, the EPROM 2, like a normal EPROM, includes a memory array consisting of a plurality of memory cells, a selection circuit consisting of an address decoder and a column switch circuit, an enable signal, a program It is composed of a control circuit that outputs various control signals upon receiving signals and the like. EPROM
2 is configured to have storage such as 16 bytes, although not particularly limited, and the 16 bytes include 8 blocks BL for each byte 2 as shown in FIG. ~BL, is considered to be divided into. EPROM 2 is made inaccessible when its enable terminal E is set to low level. The security byte 3 in the protection circuit 3 is the second
As shown in the figure, eight bits b correspond one-to-one to each block of the EPROM 2 divided into eight parts. -b7
DetIl! has been completed.

Although the details are not shown, the protection circuit 3 includes eight FAMs.
a decoder for decoding a specific combination of address data on the address bus AB; a decoder for decoding a specific combination of address data on the address bus AB; and providing each memory cell with data that is activated by the decoder and corresponds to the write data supplied via the data bus DB. It is composed of a write circuit and a read circuit that is connected to each of the eight memory cells and operates substantially constantly. The 8-bit security control data output from the readout circuit in circuit 3 is sent to decoder 4.
supplied to Although not particularly limited, each memory cell in the protection circuit 3 is put into the write state in response to the high level of the data bus DB when the write circuit is put into the operating state. The program for each memory cell is FAMO3
It is irreversible, similar to that of a normal EPROM using . That is, although a memory cell that was placed in an erased or unwritten state in a previous write operation may be placed in a written state in a later write operation, the change in state to the contrary is not substantial. do not have. When data is written in the protection circuit 3, access to the data written in the block BLi in the EPROM 2 corresponding to the written bit bi is made impossible.

In the initial state where no data has been written to EPROM2 (at this time, no data has been written to the security bit either), the EPR
EPR specified by an external device such as an OM writer
Data supplied from the data bus DB is written to the address of OM2. At this time, if you want to protect the confidentiality of that data, then set the security byte bin corresponding to the block where the write took place! 1711+ is written to -. For example, as shown in FIG. 2, when it is desired to protect the confidentiality of data contained in memory blocks BL2 and BL6, the security bit b2.
“1” is written to bb. This protects the data contained in memory blocks BL2 and BL. Here, this bin 1~ information is always sent to the decoder 4.

There are two modes for accessing the address of EPROM2, one is the CPU access mode in which the EPROM mode signal EPM is set to low level, and the other is the CPU access mode in which the EPROM mode signal EPM is set to low level.
E P ROM with mode signal EPM set to high level
Direct mode. In CPU access mode,
Reading and writing of data in the EPROM 2 is performed by an internal CPU, and in the EPROM direct access mode, reading and writing of data in the EPROM 2 is performed directly by an external device such as an EPROM writer, regardless of the CPUI.

CP whose EPROM mode signal EPM is set to low level
In U mode, when accessing the built-in EP R75M, the CP
The enable signal CE sent from the UI is set to high level. That is, the enable terminal E is set to a high level regardless of the level of the data security control signal CED output from the decoder 4. Therefore, in the CPU mode, all addresses in the EPROM can be accessed by the internal CPU.

In the EPRσM direct access mode, when an address signal is input from the outside to the address bus AB via the human output board 5, the address signal is input to the decoder 4 and decoded. The decoder 4 sends a data security signal c when the decoded address signal is the address specified by the security byte.
Output ED. And that security signal CED
is input to one input terminal of gate G, and gate G□
outputs a low level signal, thereby causing the EPR of the address specified by security byte 3 to be
Access to the 6 rooms is prohibited and data is kept confidential.

On the other hand, if there is no need to protect the security of the data written to the address of the EPROM, the security bit corresponding to the block containing the data is not written to, and in this case, the EPRσM direct mode is used to The way it appears is at a high level. Therefore, it is necessary to read the written data from the EPR? Access to the ThM block becomes possible from the outside.

In the above embodiment, the EP is divided into several blocks.
A security bit is provided in the ROM that corresponds one-to-one to that block, and when an address signal from the outside is decoded and the address is specified by the security bits I~, the EPROM corresponding to the security bit is By providing a decoder that outputs a signal that allows or disables access to the EPROM and controlling address access to the EPROM,
By virtue of the ability to prohibit writing and access for each independent block, it is possible to securely protect only desired data among the data written to the EPROM.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

In the above explanation, the invention made by the present inventor was mainly applied to a single-chip microcomputer, which is the background field of application, but the invention is not limited thereto.
M (Electrically ErasableP
It can be applied to general LSIs with built-in non-volatile memory (programmable ROM).

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, it is possible to protect the confidentiality of desired data among data written in a nonvolatile memory such as an EPROM built into an LSI.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a single-chip microcomputer to which the present invention is applied, and FIG. 2 is an explanatory diagram showing the correspondence between security by 1 and EPROM blocks.

Claims (1)

[Claims] 1. A non-volatile memory having a plurality of security bits and a plurality of blocks corresponding to the security bits, and the address signal is set based on the address signal and the security bit for the non-volatile memory. A non-volatile memory characterized in that, when the security bit of the non-volatile memory indicates an address for accessing a block corresponding to the non-volatile memory, the non-volatile memory is provided with security protection means that makes it impossible to access the block from the outside. Built-in LSI. 2. Claim 1, wherein the security bit is comprised of a writable non-volatile memory.
LSI with built-in non-volatile memory as described in section.