JPS62162147A - Data processor - Google Patents
Data processorInfo
- Publication number
- JPS62162147A JPS62162147A JP61002922A JP292286A JPS62162147A JP S62162147 A JPS62162147 A JP S62162147A JP 61002922 A JP61002922 A JP 61002922A JP 292286 A JP292286 A JP 292286A JP S62162147 A JPS62162147 A JP S62162147A
- Authority
- JP
- Japan
- Prior art keywords
- scan
- identification code
- shift
- path
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318558—Addressing or selecting of subparts of the device under test
- G01R31/318561—Identification of the subpart
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は複数のスキャンパスとこれらの複数のスキャン
パスのシフトインアウト動作を制御する制御手段を備え
たデータ処理装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device including a plurality of scan paths and a control means for controlling shift-in/out operations of the plurality of scan paths.
従来lのデータ処痕装置では、フリップ70ツ。 The conventional data storage device requires 70 flips.
グが縦続接続さルた複数のスキャンパスとこれら複数の
スキャンパスのシフトインアウト動作を制御する制御手
段とを有し、前記制御手段が各スキャンパスに含まれる
レジスタ及びフリップフロップ等へのデータの書込みま
たは、それ等からのデータの読み出しはシフトインデー
タのスキャンパスへのシフトイン、スキャンパスからの
シフトアウトによりシフトアウトデータを取り出すこと
により行なって保守あるいは診断の便に供していた。The control means includes a plurality of scan paths connected in cascade and a control means for controlling shift-in/out operations of the plurality of scan paths, and the control means transfers data to registers, flip-flops, etc. included in each scan path. Writing or reading data from them is performed by shifting shift-in data into the scan path, shifting out from the scan path, and taking out shift-out data for maintenance or diagnosis.
ウド動作の正常性確認の為、選択したスキャンパスに4
1i?定のパターンをスキャンインし、その後、スキャ
ンアウトし、スキャンインデータとスキャンアウトデー
タとの比較全行っていた。すなわちスキャンインアウト
の動作確認の為には、スキャンイン動作とスキャンアウ
ト動作とを行なわなけ肛ばならなかった。4 on the selected scan path to check the normality of the cloud operation.
1i? A certain pattern was scanned in, then scanned out, and the scan-in data and scan-out data were compared. That is, in order to confirm the scan-in-out operation, it is necessary to perform a scan-in operation and a scan-out operation.
このため、データ処理装置が大型化するにつnで、スキ
ャンパスの数及びスキャンパスに含まnるフリップフロ
ップの数が増大する傾向下において、スキャンインアウ
トの動作確認には多くの時間を要するといり問題点があ
った。For this reason, as data processing equipment becomes larger, the number of scan paths and the number of flip-flops included in the scan paths tend to increase, and it takes a lot of time to check scan-in-out operation. Then there was a problem.
本発明の装置に、複数のスキャンパスと該複数のスキャ
ンパスのシフトインアウト動作を制御する制御手段とを
備えたデータ処理装置において、前記複数のスキャンパ
スは、4!!r々、スキャンイン1111i VCCス
スキャンバス固有識別コードを保持する諌別コード保持
手段を有し、前記制御手段は、各スキャンパスのシフト
インアウトデーj1転送時。In the data processing device of the present invention, the data processing device includes a plurality of scan paths and a control means for controlling shift-in/out operations of the plurality of scan paths, wherein the plurality of scan paths is 4! ! r, scan-in 1111i VCC scan path has an identification code holding means for holding a unique identification code of the scan path, and the control means controls the scan-in 1111i when transferring the shift-in-out date j1 of each scan path.
各スキャンインデータに続いて前記識別コードを転送(
−前記識別コード保持手段から送り返された識別コード
と前記識別コード保持手段に保持されるべき識別コード
とを比較して構成さnる。Transmit the identification code following each scan-in data (
- The identification code sent back from the identification code holding means is compared with the identification code to be held in the identification code holding means.
〔実施例〕 次に1本発明について図面を参照して説明する。〔Example〕 Next, one embodiment of the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例を示すブロック図である。第
1図に示すデータ処理装置に、スキャンパス20〜50
とシフトインアウト動作全制御する制御手段10全備え
ている。FIG. 1 is a block diagram showing one embodiment of the present invention. The data processing device shown in FIG. 1 has 20 to 50 scan paths.
and control means 10 for controlling all shift-in-out operations.
制御手段10は、制御部11と、スキャンパス20〜5
0からのシフトアウトデータのいずれかを制御部11の
指示に工す選択する切換部12と、比較部13とから成
る。The control means 10 includes a control section 11 and scan paths 20 to 5.
It consists of a switching section 12 that selects any of the shift-out data from 0 based on an instruction from the control section 11, and a comparison section 13.
スキャンパス20〜50は、データ処理装置に本来組込
まれるレジスタ、フリップフロップ等からなる目的レジ
スタ22〜52と識別コードを保持する識別コード保持
手段21〜51とからそれぞれ構成さnる。Each of the scan paths 20-50 is composed of purpose registers 22-52 which are originally built into the data processing apparatus, such as registers and flip-flops, and identification code holding means 21-51 which hold identification codes.
以下に各部の動作について説明する。The operation of each part will be explained below.
制御手段10の制御部11により選択In、た久\へS
ζ<ス、例、tばスキャンパス30にシフトイン。The control unit 11 of the control means 10 selects In, Taku\S
ζ<s, e.g., t shifts into scan path 30.
データをシフトインする場合、まず、切換部12に、制
御部11の指示により、スキャンパス3゜からのシフト
アウトデータを出力するようにセットされる
次いで、制御部11内に保持されているシフトアウデー
タハ、識別コード保持手段31へ、識別コード保持手段
31から目的レジスタ32へと順次シフトインさn、目
的レジスタ32からシフトアウト17またデータは、切
換部12を通り制御部11に返さnる。When shifting in data, first, the switching unit 12 is set to output shift-out data from the scan path 3° according to an instruction from the control unit 11. The data is sequentially shifted in to the identification code holding means 31, from the identification code holding means 31 to the target register 32, and then shifted out from the target register 32 (17), and the data is returned to the control unit 11 through the switching unit 12. Ru.
その後、制御部11でスキャンパス選択VcLり生成さ
扛る識別コード(すなわち、各スキャンパスに占有の識
別コード)が識別コード保持手段31にシフトインさn
る。これと同時に、生成された識別コードに、比較部1
3へ送られる。また、目的レジスタ32を介して識別コ
ード保持手段31に保持でnていた識別コードは、切換
部12を通υ13へ送らn、前述した生成場れだ識別コ
ードと比較さnる。比較の結果側識別コードが一致して
いれば、制御手段10及びスキャンパス30が正常に動
作していることになる。鷹だ、この正常性のチェックと
目的レジスタへのデータの書込み、読み出しは、一連の
シフトインアウト動作(この時間は従来の装置のシフト
イン動作またはシフトアウト動作の時間に等しい)に工
り可能となり従来に比し時間が172 に短縮される
。識別コードのパターンは、全ビット0、全ビット1の
パターンを除いた万が望ましい。Thereafter, the identification code generated by the scan path selection VcL in the control unit 11 (that is, the identification code exclusive to each scan path) is shifted into the identification code holding means 31.
Ru. At the same time, the comparison unit 1
Sent to 3. Further, the identification code held in the identification code holding means 31 via the purpose register 32 is sent to υ13 through the switching unit 12, and is compared with the generated identification code described above. If the comparison result side identification codes match, it means that the control means 10 and the scan path 30 are operating normally. Well, this health check and writing and reading data to and from the destination register can be constructed into a series of shift-in-out operations (the time of which is equal to the time of a shift-in or shift-out operation in a conventional device). This reduces the time to 172 seconds compared to the conventional method. It is preferable that the identification code pattern excludes a pattern in which all bits are 0 and all bits are 1.
以上説明1.た工うに本発明はスキャンパスに、データ
処理装置内に本来組込まnるレジスタやフリップフロッ
プ等からなる目的レジスタに加えて、スキャンパスに占
有の識別コードを保持する識別コード保持手段をシフト
イン側に設け、シフトインアウト制御手段の制御に工り
一連のシフトインアウト動作で該識別コード保持手段へ
シフトインさnた識別コードと前記識別コード保持手段
からシフトアウトされた識別コード全比較することに工
り、スキャンパスの正常性と、前記制御子段の正常性が
確認できることに工りスキャンパスの正常性及び前記制
御手段の正常性チェックと同時に目的レジスタへのシフ
トアウト動作が行なうこと−7)i−T:@XPヤンパ
ス動作チェック時間を短縮できるという効果がある。Above explanation 1. Specifically, the present invention provides an identification code holding means for holding an exclusive identification code in the scan path, in addition to a purpose register consisting of a register, a flip-flop, etc., which is originally built into the data processing device, on the shift-in side. and comparing all the identification codes shifted in to the identification code holding means and the identification codes shifted out from the identification code holding means in a series of shift-in/out operations under the control of the shift-in/out control means. In addition, the normality of the scan path and the normality of the control child stage can be confirmed by performing a shift-out operation to the target register at the same time as checking the normality of the scan path and the normality of the control means. 7) i-T: @XP This has the effect of shortening the time to check the yan pass operation.
第1図は本発明の一笑流側を示すブロック図である。
10・・・・・・制御手段、11・・・・・・制御部、
12・・・・・・切換部、13・・・・・・比較部、2
0.30.40.50・・・・・・スキャンパス、21
.31.41.51・・・・・・識別コード保持手段、
22.32.42.52・・・・・・目的レジスタ。
代理人 弁理士 内 原 晋 ′1f5t
図FIG. 1 is a block diagram showing the basic side of the present invention. 10... Control means, 11... Control section,
12...Switching section, 13...Comparison section, 2
0.30.40.50...Scan path, 21
.. 31.41.51...Identification code holding means,
22.32.42.52... Purpose register. Agent Patent Attorney Susumu Uchihara '1f5t
figure
Claims (1)
ンアウト動作を制御する制御手段とを備えたデータ処理
装置において、前記複数のスキャンパスは、各々、スキ
ャンイン側に該スキャンパス固有の識別コードを保持す
る識別コード保持手段を有し、前記制御手段は、各スキ
ャンパスのシフトインアウトデータ転送時各スキャンイ
ンデータに続いて前記識別コードを転送し、前記識別コ
ード保持手段から送り返された識別コードと前記識別コ
ード保持手段に保持されるべき識別コードとを比較する
ことを特徴とするデータ処理装置。In a data processing device comprising a plurality of scan paths and a control means for controlling shift-in/out operations of the plurality of scan paths, each of the plurality of scan paths has an identification code unique to the scan path on the scan-in side. The control means includes an identification code holding means for holding an identification code, and the control means transfers the identification code following each scan-in data when transferring shift-in-out data of each scan path, and the control means transfers the identification code following each scan-in data, and the identification code sent back from the identification code holding means. and an identification code to be held in the identification code holding means.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61002922A JPS62162147A (en) | 1986-01-10 | 1986-01-10 | Data processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61002922A JPS62162147A (en) | 1986-01-10 | 1986-01-10 | Data processor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62162147A true JPS62162147A (en) | 1987-07-18 |
Family
ID=11542837
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61002922A Pending JPS62162147A (en) | 1986-01-10 | 1986-01-10 | Data processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62162147A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5466556A (en) * | 1993-05-14 | 1995-11-14 | Brother Kogyo Kabushiki Kaisha | Photosensitive microencapsulated toner |
US5470683A (en) * | 1993-07-28 | 1995-11-28 | Brother Kogyo Kabushiki Kaisha | Photosensitive microcapsule toner |
-
1986
- 1986-01-10 JP JP61002922A patent/JPS62162147A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5466556A (en) * | 1993-05-14 | 1995-11-14 | Brother Kogyo Kabushiki Kaisha | Photosensitive microencapsulated toner |
US5470683A (en) * | 1993-07-28 | 1995-11-28 | Brother Kogyo Kabushiki Kaisha | Photosensitive microcapsule toner |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5173904A (en) | Logic circuits systems, and methods having individually testable logic modules | |
EP1946131B1 (en) | Ic testing methods and apparatus | |
CA1126413A (en) | Method and arrangement of testing sequential circuits represented by monolithically integrated semiconductor circuits | |
US5781560A (en) | System testing device and method using JTAG circuit for testing high-package density printed circuit boards | |
US5819025A (en) | Method of testing interconnections between integrated circuits in a circuit | |
JPS61155877A (en) | Integrated circuit | |
JP3159829B2 (en) | Control network and control method for self-inspection | |
US5077740A (en) | Logic circuit having normal input/output data paths disabled when test data is transferred during macrocell testing | |
EP0792486B1 (en) | Test apparatus/method for level sensitive scan designs | |
EP0562886B1 (en) | Method and apparatus for generating test sequence | |
EP0849678B1 (en) | A system and method for testing electronic devices | |
US5189675A (en) | Self-diagnostic circuit for logic circuit block | |
JPS6226734B2 (en) | ||
EP0209982B1 (en) | Digital integrated circuits | |
JPS62162147A (en) | Data processor | |
JPH0666884A (en) | Scan system connection method for LSIs with different scan systems | |
JPS61155874A (en) | Method and device for detecting fault of large-scale integrated circuit | |
JPH06318964A (en) | Data processing system and its method of self-checking control | |
EP0210741A2 (en) | Digital integrated circuits | |
EP0347906B1 (en) | Self-diagnostic circuit for logic circuit block | |
JPH06213972A (en) | Boundary scan cell circuit, boundary scan test circuit and their using method | |
JP3072718B2 (en) | Method for testing an integrated circuit having multiple I/O signals - Patents.com | |
JPS6255955A (en) | Integrated circuit | |
JP3024310B2 (en) | Logic circuit inspection equipment | |
JP2820975B2 (en) | Scan test method for large-scale integrated circuits |