JPS62159284A - Multivalued image processor - Google Patents

Abstract

PURPOSE:To calculate a histogram of an image at a high speed by connecting an output signal of an adding circuit for adding a set value which has been set in advance, to an output data of a histogram use memory. CONSTITUTION:For instance, when (i), (j), (i)... are transferred successively as image data values, the i-th and the j-th addresses of a histogram use memory are brought to an access, and MOUT is obtained successively in an output data line of the memory 10. An output of the memory 10 is latched by a latching circuit 10, and thereafter, a set value is added by an adding circuit 13. In an output ADOUT of the circuit 13, a value which is brought to the previous memory contents to an increment is obtained, and subsequently, by a write pulse WE, the added value ADOUT is written as new contents of the memory. At the time point when a transfer of all image data is ended, the total number of picture elements having the image data value concerned is accumulated and held in each address of the memory 10, and can be read in freely from a CPU which is not shown in the figure, through a data gate 4.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a multilevel image processing apparatus that calculates a histogram for an image processing apparatus that handles multi-tone digitized image data.

BACKGROUND ART In processing image data using conventional technology, processing such as binarization or gradation conversion (partial enlargement) is a commonly used technique. Specifying the binarization threshold in binarization processing or specifying the position and width of the window in the gradation direction in gradation conversion is one of the important elements that determine the processing effect, and conventionally various decisions have been made. A method has been proposed and implemented. A typical method is to obtain a binarization threshold using a histogram as a statistic of image data. As shown in FIG. 6, an appropriate binarization threshold Th is calculated from the frequency distribution of pixel values of all image data and binarization is performed to optimize the processing. Also in the gradation conversion process, as shown in FIG. 6, window values (Wl, W2) for the conversion process are determined from the histogram. You can also divide the image into several small regions and
Adaptive threshold method that creates a histogram for each area and determines the threshold (Taniuchi 1) "Application of image processing technology to recognition and assembly of mechanical parts", "System and Control J
, vo123, A 7 PP379388.

(July 1979) have also been proposed.

FIG. 7 shows an example of the configuration of such a conventional image processing apparatus. The histogram is obtained by sequentially counting the distribution of image data values stored in the image memory 2 by the main control circuit (CPU) 1. Reference numeral 3 denotes a circuit dedicated to image processing, and in some cases, such dedicated hardware is provided to speed up the processing of repetitive operations such as spatial filtering and gradation conversion. 4 is an image memory for displaying, and 5 is a display for displaying images.

Problems to be solved by the invention In these conventional image processing methods using histograms,
A problem was pointed out in the method of calculating the histogram. That is, (1) since each pixel data in the image memory is statistically processed using a CPU or the like, it takes a considerable amount of time to obtain a histogram.

(';4) Problems include the need for the image memory to be configured to be accessible from the CPU.

In particular, as the size of image data increases, these problems make it virtually impossible to put processing using histograms to practical use.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide an image processing device that has a simple configuration and is equipped with a circuit that calculates a histogram of an image at high speed.

Means for Solving the Problems In the present invention, in order to solve the above problems, an image data transfer path and at least n address lines (n = maximum number of bits of image data) are provided in the image processing device. an address signal for the histogram memory is generated from the image data in the image data transfer path, and an input data line of the histogram memory is provided with a histogram memory corresponding to the output data of the histogram memory. An image processing device equipped with a histogram calculation circuit is realized by connecting an addition circuit that adds up all specified set values set in advance.

According to the present invention, with the above-described configuration, the appearance frequency of image data transferred within the image processing apparatus is counted and held at high speed by dedicated hardware, thereby improving the functionality of the image processing apparatus.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows an embodiment of an image processing apparatus using a histogram calculation circuit according to the present invention. 6 is an image input device for inputting image data, and 7 is a histogram calculation circuit which is an important component of the present invention. The histogram calculation circuit 7 operates when image data is input and transferred from the input device 6 to the image memory 2, or when data is transferred between the image processing dedicated circuit 3 and the image memory 2 for image data processing. A histogram is calculated while inputting image data via the data transfer path 8 on a monitor. In the embodiment shown in FIG. 1, only the image processing dedicated circuit 3 and the histogram calculation circuit 7 are connected to the system bus 9 of the main control circuit (CPU) 1, and the image memory is connected to the system bus 9 of the main control circuit (CPU) 1.
It is assumed that it will not be accessed from the PU.

Next, a specific example of the histogram calculation circuit 7 will be described. FIG. 2 shows a first embodiment of a histogram calculation circuit which is a component of the present invention.

The operation during histogram calculation will be explained. Prior to calculating the histogram, first, the contents of the histogram memory 1o are cleared to zero. Any memory that has a clear terminal may be used, but normally the memory contents are sequentially cleared under the control of the CPU. At this time, under the control of the multiplexer 11, the system address bus 9-1 is connected to the address line of the memory 1o, and the system data bus 9-2 is connected to the data line of the memory 1o. The memory address space is 8 bits for image data.
Then, 28=256, and the time to clear is
Just a little bit is fine.

The histogram is calculated when an image is input or when image data is transferred via the transfer path 8 for image processing. At this time, by controlling the multiplexer 11, the image data on the data transfer path 8 is connected to the address line of the memory 1Q.

FIG. 3 shows an example of a time chart at this time.

(a) is a signal -+DIN indicating that the data on the transfer path is valid, (b) is the reference clock CLK for data transfer, and (C) is image data DAT on the transfer path. (a) and (C) are synchronized with the reference clock CLK (b). The count up for calculating the histogram is
This is executed only when the valid signal -X-DIN is active (at "L" level).

After clearing the memory 10, if image data values i, j, i, etc. are sequentially transferred as shown in FIG. 3, addresses 1 and 1 of the memory 1o are accessed and The 1o output data line has the 3rd
MOUT(d) in the figure is obtained sequentially. , in the histogram calculation circuit of FIG.
Add set value A. Usually A=1. Addition circuit 1
The output ADOUT (f) of step 3 has a value obtained by incrementing the previous memory contents, and then the write pulse output ADOUT(
f) is written as the new memory contents. When II i 11 is transferred again as the third data,
The contents of address 1-i 11 of memory 1o are 1 to 2
Changes to. The data word width of the memory 10 is determined by the maximum number of pixels of the image to be handled; for example, 266×2
For a 56-dot image, the maximum number of pixels is 2, so a word structure of 16 to 17 bits/word is required.

The address space of the memory is determined by the gradation of the image data to be handled; for example, if the image data is 8-bit gradation, a space of 28=256 words is sufficient. At the time when all the image data has been transferred, each address in the memory 10 cumulatively stores the total number of pixels having the corresponding image data value.

This accumulated value is sent to the system via the data gate 14.
It is connected to the data bus 9-2 and can be read freely by the CPU 1.

FIG. 4 shows a second embodiment of a histogram calculation circuit which is a component according to the present invention. The same components as in FIG. 2 are given the same numbers. In the configuration shown in the figure, the adder circuit 13
One of the added values becomes the output (h) of the comparator circuit 15. A value obtained by latching the output data of the memory 10 is connected to the P input of the comparison circuit 16. A preset fixed value B is set to the other Q input of the comparison circuit 15. The comparison circuit 15 compares the output value of the memory 1o with the set value B, and as long as the relationship P×Q is established, an "H" level output signal is obtained at the output (h).

If the output of the comparator circuit 15 is connected to the LSB (all other bits are set to "L") of one input signal group of the adder circuit 13, addition of +1 is executed, and the second Similar to the example shown in the figure, the address contents of the memory 10 corresponding to the image data values are sequentially incremented. Eventually, when the contents of a certain address in the memory become equal to the value B set to the Q input of the comparator circuit 15, P<Q no longer holds, so the output (h) of the comparator circuit 16 goes to the "'L" level. become.

Therefore, the addition circuit does not perform addition (addition of 0), and the contents of the corresponding address in the memory 10 are not incremented either. For address-pixel data values whose memory contents are smaller than B, conventional operation is performed.

The setting value B of the comparison circuit 15 sets the upper limit of the frequency of appearance in the histogram, and all frequencies of image data that count the frequency of appearance of 8 or more are represented by the count value B. The embodiment shown in FIG. 4 automatically clips the upper limit for an image that has an extremely unbalanced image data frequency distribution (the frequency of occurrence of constant image data values is extremely high). The present invention provides a histogram calculation circuit that can calculate a histogram while multiplying the data.

By employing such a histogram calculation circuit, even when handling images with a large number of pixels, it becomes possible to freely set the word structure of the histogram memory within a practically acceptable range.

In the above description, the histogram calculation circuit calculates a histogram by monitoring image data when inputting an image or transferring data for image processing.
Of course, it is also possible to obtain a histogram each time, and it can also be applied to adaptive thresholds, value methods, etc.

Furthermore, as in the configuration in the embodiment, the image memory does not necessarily need to be accessible by the CPU as in the past, and the degree of freedom in memory configuration can be greatly improved, which is expected to have great industrial effects. It is possible.

Effects of the Invention As described above, according to the image processing device of the present invention, a histogram of image data within a required area can be obtained at high speed with a simple circuit configuration, and the functions of the image processing device can be improved. can be significantly improved.

[Brief explanation of drawings]

Figure 8g1 is a block diagram of a multivalued image processing apparatus according to an embodiment of the present invention, Figure 2 is a block diagram of a histogram calculation circuit in the same apparatus, Figure 3 is a waveform diagram for explaining its operation, and Figure 4 is a diagram of the nJ notation. FIGS. 5 and 6 are diagrams showing how threshold values are determined using a histogram, and FIG. 7 is a diagram showing a conventional histogram calculation circuit. 1... Main control circuit (CPU), 2...
Image memory, 6... Image input device, 7...
...Histogram calculation circuit, 8...Data transfer path, 1Q...Memory for histogram, 13...
...Addition circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 4 Figure 5 Figure 6 wt wz ＾ゑtater

Claims (1)

[Claims] a data transfer path for inputting or processing digital image data having a maximum of n bits of gradation;
a histogram memory having more than one address line;
The histogram calculation circuit includes an address signal of the histogram memory based on the image data signal from the data transfer path, and an input data line of the histogram memory receives an address signal of the histogram memory. 1. A multi-valued image processing device, characterized in that an output signal of an adding circuit is connected to add a designated setting value set in advance to a multivalued image processing device.