JPS62159232A - Instruction prefetching device - Google Patents

Abstract

PURPOSE:To perform quickly the correct instruction prefetching action by correcting the following wrong instruction prefetching action before the branch conditions are decided for a prefetched instruction in case an instruction prefetching action is carried out according to the branch information designating a wrong branching address. CONSTITUTION:It is checked whether the information designating the address of an instruction to be prefetched is registered to a branch history table 410 or not after the address of a branch instruction is set to an instruction address register 411. If this information is registered, an instruction prefetching action is carried out according to the corresponding branch information read out of the table 410. While an operand reading circuit OC stage estimation confirming circuit 426 collates the estimated branch address of an instruction with a designated branching address and outputs the estimation failure signal to a signal line 140 when confirming that the former branch address is wrong. An instruction prefetching control circuit 423 corrects the following wrong instruction prefetching action in response to said failure signal before execution of a prefetched instruction.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention' The present invention relates to an instruction prefetching device that prefetches the next instruction while predicting a judgment result prior to execution processing of a branch condition judgment step included in a step of an instruction sequence of a +11 processing device.

[Prior Art] ゛In the past, as an instruction prefetch device that performs branch prediction using a branch history table, for example, Japanese Patent Laid-Open No. 59-9155
It exists in the form seen in Publication No. 0. This conventional device registers a pair of information specifying the address of a branch instruction and branch information including the branch destination address of the branch instruction in a branch history table, and when fetching an instruction from the cache memory as an instruction prefetch operation, It checks whether the address of the instruction to be prefetched is registered in the branch history table as the address of a branch instruction, and if it is registered, the next instruction is prefetched using the corresponding branch destination address. If the information registered in the branch history table is incorrect, the branch condition for that instruction is determined, the corresponding information in the branch history table is updated, and then the prefetching of the subsequent instruction is performed again. ing.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, the branch destination address is changed due to updating of the value held in the register used to calculate the branch destination address of the branch instruction, and the old branch destination address included in the information held in the branch history table is changed. If an instruction prefetch operation is performed in accordance with the above, the subsequent correct instruction will be taken out only after the branch condition determination step for the instruction having incorrect branch information is completed. However, in the case of an unconditional branch instruction, it is possible to retake the instruction without waiting for the branch condition determination step, as long as the correct branch destination address is found. However, in the prior art, the validity of branch prediction cannot be evaluated unless the branch condition determination step is completed.
Execution of branch instructions whose branch addresses are frequently changed has the disadvantage of slowing down the processing speed.

The present invention eliminates such conventional drawbacks, and its purpose is to promptly perform a correct subsequent instruction prefetch operation when an instruction is prefetched based on incorrect branch information of a branch destination address. be.

Means for Solving Problem c] In order to achieve the above object, the present invention provides an instruction prefetching device in an information processing device that provides branch information that includes information specifying the address of a branch instruction and a branch destination address of the branch instruction. branch history table means for storing a plurality of pairs of instructions; and whether or not information specifying the address of the instruction to be prefetched in the instruction prefetching operation is registered in the branch history table means when performing an instruction prefetching operation. and a second checking means for checking whether information specifying a branch destination address included in branch information corresponding to the prefetched instruction is correct prior to determining the branch condition of the prefetched instruction. control means for reading out corresponding branch information from the IJ child table stage and continuing the instruction prefetching operation in accordance with the branch information in response to the confirmation of registration by the first checking means; a branch Mf that specifies an incorrect branch destination address in response to the results of the first and second checking means;
and an instruction preemption control means for performing control so as to correct a subsequent erroneous instruction prefetching operation without waiting for the execution of the prefetched instruction when the instruction prefetching operation is performed according to the information.

[Effect]

When an instruction prefetch operation is performed according to branch information that specifies an incorrect branch destination address, the first . In response to the result of the second checking means, the instruction prefetching control means corrects the subsequent erroneous instruction prefetching operation without waiting for completion of the branch condition determination step of the prefetched instruction.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention includes an instruction address generation circuit (rA) 401, an instruction address translation circuit (IT
) 402, instruction decoding circuit (ID) 403, operand address generation circuit (OA) 404, operand address conversion circuit (OT) 405, operand successive output circuit (○C) having an operand storage circuit 406, instruction execution circuit (EX) 407, instruction storage circuit (IC) 4
08, instruction buffer 409, branch history table (
BHT) 410, instruction address register 411,
Instruction address addition circuit 412, branch information buffer 413
, instruction alignment circuit 414, branch information switching circuit 415, branch information registers 416, 417, 418, 419, 420
, selection circuits 421, 422, instruction prefetch control circuit 42
3. OA stage pre/M confirmation circuit 424. OT stage prediction confirmation circuit 425, OC stage prediction confirmation circuit 42
6, EX stage pre-7fI116fi L'1 circuit 42
7. Instruction address recovery register 428, address generation circuit 430, 431, 432° comparison circuit 433, registers 434, 435, flip-flop 436, 437
, 438, 439, 440.441.

Note that the instruction prefetch control circuit 423 constitutes an instruction prefetch control means, the OC stage prediction confirmation circuit 426 constitutes a second inspection means*2, and the branch history table 410 constitutes a branch history table means and a first inspection means*. 1.

Instruction storage circuit 408 and operand read circuit 406
Both of the operand storage circuits in the main memory may be the main memory itself, and further, the instruction storage circuit 408 may be an instruction cache memory which is a copy of a part of the instruction section of the main memory, and the operand storage circuit may be a main memory operand storage circuit. It may also be configured as an operand cache memory that is a copy of a part of the section.

The present invention does not necessarily need to have a device configuration corresponding to the above-mentioned instruction processing unit; for example, an instruction address generation circuit 401, an operand address generation circuit 404, etc. Instruction address conversion circuit 402 and operand address conversion circuit 4
05. Instruction decoding circuit 408 and operand successive output circuit 40
The j17 circuit in 6 can also be applied in a shared computer system.

In Figure 1, branch history table (BHT) 4
10 stores information specifying the address of a branch instruction, a branch success/failure flag (V) as a prediction of execution of the branch instruction, and a branch destination address in pairs as shown in FIG.

An instruction address register (I) for the instruction storage circuit 408
AR) 411 holds an instruction read request address and executes an instruction read operation.

Further, an instruction address register (IAR) 411 is connected to a branch history table (BHT) 410 and an instruction address adder circuit 412 via a signal line 101.

The contents of register 411 are branch history table (BHT
) 410 and outputs a signal to the signal line 106 indicating whether the address of the instruction to be read is registered therein. If registered, the corresponding branch destination address is read out to the signal line 105. If it is not registered, the instruction address addition circuit 412 generates an address for prefetching the instruction of the subsequent instruction word.

The instruction address addition circuit 412 simply adds “rAR” when assuming that the instruction word read in one request is 8 bytes.
+8" to the output 107. The instruction buffer 409 is a circuit that generates 8 Bytes read from the instruction storage circuit 408.
The prefetched instruction words of te are accumulated to form a queue for supplying instructions to the instruction processing unit. The instruction alignment circuit 414 outputs signal line 1 when the instruction buffer 409 is empty.
02 from the instruction storage circuit 408. 8
Corresponding to the instruction word of Byte, the instruction buffer 409
When the instruction buffer is not empty, each instruction is extracted corresponding to the 8-byte instruction word stored in the instruction buffer via the signal line 103 and sent to the instruction decoding circuit 40 via the signal vA 104.
This is a circuit that supplies instructions to 3.

When the instruction decoding circuit 403 receives an instruction word via the signal line 104, it reports the length of the instruction word to the branch information register 417 via the signal line 112, and also indicates that the instruction is a branch instruction (unconditional branch instruction 9 condition). It reports to the OA stage prediction confirmation circuit 424 via the signal line 113 whether the instruction is an instruction that can perform a branch operation such as a branch instruction, and also reports whether the instruction is an unconditional branch instruction or not, and whether the instruction is a count branch instruction or not. (Branch oncoun is called an instruction: a BCT instruction) or not is sent to the register 435 via the signal line 114.

The branch information buffer 413 is prepared for the instruction word stored in the instruction buffer 409, and if there is a branch instruction predicted to be a successful branch in the instruction word, the branch information buffer 413 is prepared for the instruction word stored in the instruction buffer 409. This circuit stores information, and the address of a branch instruction is set via a signal line 101, and the branch destination address and v bit as branch information are set from a branch history table (BHT) 410 via a signal line 105. If there is no branch instruction that is predicted to be a successful branch, the ■ bit is set to 0 and the instruction address is set to signal line lo.
t respectively.

The branch information switching circuit 415 receives the branch II! signal via signals 5101 and 105 when the instruction buffer 409 is empty. ttI13 and, if not, the branch information given via the branch information buffer 413, respectively.

Registers 416, 417 and 418 each correspond to each processing stage of a branch instruction and hold branch information shown in FIG. The branch information registers 419 and 420 are registers that replace and hold the branch destination address part with the actual branch destination address generated by execution of the branch instruction.

The address generation circuits 430, 431, and 432 add the address of the branch instruction held in the branch information registers 417, 418, and 420, respectively, and the instruction word length of the branch instruction itself to generate the instruction address of the instruction on the branch N0GO side. generate.

The operand address generation circuit 404 generates an operand address specified by an instruction, and also generates an operand address specified by an instruction.
If it is an instruction, it has a function of outputting a value for performing a counting operation held in a general-purpose register specified by the BCT instruction to the comparison circuit 433 via the signal line 120.

○The A stage prediction confirmation circuit 424 is the instruction decoding circuit 40
This circuit detects whether or not the corresponding branch information has been read from the branch history table even though the instruction decoded in step 3 is not a branch instruction. receives the V bit held in the branch information register 416, and outputs an OA stage prediction failure signal to the instruction prefetch control circuit 423 and flip-flop 436 via the signal line 121 when the ■ bit is 1 even though it is not a branch instruction. .

The comparison circuit 433 compares the count value given via the signal line 120 with the value "1", and if the count value is 1, the count value is 1.
The signal is output to the OT stage prediction confirmation circuit 425 via the signal line 123.

The OT stage prediction confirmation circuit 425 is the output of a flip-flop 436 that holds the OA stage prediction failure signal output from the OA stage prediction confirmation circuit 424 .

The output of the register 435 that holds whether the instruction is an unconditional branch instruction or a BCT instruction, the count output from the comparison circuit 433 (IIL1 signal, and the branch information register 418)
(via held by When the bit is 0,
OT to the instruction prefetch control circuit 423 via the signal line 129
A stage prediction failure signal is outputted to the flip-flop 437 via the signal line 130, an OT stage BHT update instruction signal is outputted to the flip-flop 437, and an OT stage Go preemption instruction signal is outputted to the flip-flop 438 and the selection circuit 421 via the signal line 131. When the instruction is issued and the count value l signal is output, that is, when the branch information is not executed and the corresponding branch information ■ bit is 1, the signal line 129 and the signal yA1 are
30 to OT stage prediction failure signal and OT stage B, respectively! - Outputs an IT update instruction signal.

The selection circuit 121 is the OT stage prediction confirmation circuit 42
When the OT stage Go prefetch instruction signal outputted by No. 5 is 1, the branch destination address output from the instruction address conversion circuit 402 is selected, and when it is 0, the branch N0GO side address output from the address generation circuit 431 is selected.

The OC stage prediction f+1 recognition circuit 426 includes a flip-flop 437 that holds the OT stage BIT update instruction signal.
output of the flip-flop 438 holding the OT stage GO prefetch instruction signal, the instruction address conversion circuit 4
Branch destination address output by 02.

From the predicted branch destination address held in the branch information register 418 and the V bit, the ■ bit is 1 and the branch is predicted to GO, and the actual branch destination address and the predicted branch destination address are different, and furthermore, before the OT stage. When no prediction failure is detected in the signal line 140, the O
OC the C stage prediction failure signal to the instruction prefetch control circuit 423 and to the flip-flop 439 via the signal line 156.
A stage BHT update instruction signal and a C stage GO prefetch instruction signal are output to the flip-flop 440 via the signal line 141, respectively.

EX stage prediction confirmation circuit 427 performs OC stage BH
Output 1 of the flip-flop 440 that holds the 10C stage GO prefetching instruction signal of the flip-flop 439 that holds the T update instruction signal 1 The bit held by the branch information register 419 and the branch success/failure signal output from the instruction execution circuit 407 indicate that the actual When the branch success/failure and the V bit are different, and the prefetching is not performed again due to the detection of prediction failure before the OC stage, the signal line 147 is
It outputs an EX stage prediction failure signal to the instruction prefetch control circuit 423 via the signal line 148, and outputs an EX stage BIT update instruction signal to the instruction prefetch control circuit 423 and the flip-flop 441 via the signal line 148.

In response to the state of the branch success/failure signal line 149, the selection circuit 422 selects the signal line 152 when the state of the signal line indicates branch GO.
When selecting the branch destination address held in the branch information register 420 given via the signal line 153 and indicating branch N0GO, the address generation circuit 432 given via the signal line 153
and supplies the output to register 434 and instruction address recovery register 428 via signal m155.

The register 434 is for updating the branch history table (BHT) 410 when branch prediction fails, and the instruction address recovery register 428 updates the contents of the branch history table 410 in the instruction address register (IAR) 411. This is to supply a new address for instruction prefetching after the invalid write address has been set.

The instruction prefetch control circuit 423 connects signal lines 121.129.
OA and OT given through 140° and 147 respectively
, OC, EX each stage prediction failure signal, and signal line 1
Based on the EX stage BHT update instruction signal given via 48, the instruction address register (IAR) 41
1 and the input of the instruction address recovery register 426.

Referring to FIG. 16, the instruction processing in the embodiment of the present invention shown in FIG. 1 is divided into the following eight processing units.

(IIIAIC An instruction address (logical address) to be staged is generated.

(21 [T stage: Address translation of the generated instruction address is performed.

+311C stage: Instructions are successively issued from the storage device using the converted real address of the instruction.

+411D stage: Successive instructions are decoded.

+510A stage: The operand address (logical address) of the decoded instruction is generated.

(Stage 6107: Address translation of the generated operand address is performed.

+710C stage: The operand is read from storage at the translated operand's real address.

+81EX stage - the instruction is executed.

If an address translation buffer is provided for the address translation in the IT stage and the OT stage, and the necessary translation table exists in the address translation buffer, the address translation process can be executed at high speed.

In addition, in the above-mentioned IC stage and OC stage instruction and operand read operations, a cache memory that holds a copy of part of the data in the main memory is provided, if the necessary instructions and operands exist in the cache memory. Processing of the IC stage and OC stage can be performed at high speed.

When each stage of IT, OT, IC, and QC described above is capable of high-speed processing, eight-stage pipeline control is possible to efficiently execute the processing flow of a plurality of instructions.

Next, branch history table (BHT) 410,
Preliminary rule confirmation circuit 4 for each stage of OA, OT, QC, EX
The operation of this embodiment will be described in detail with reference to block diagrams and time charts of 24, 425, 426, 427 and the instruction prefetch control circuit 423.

Referring to Figure 2, branch history table (BHT) 4
10, a directory tα section 501, a data storage section 5;
02, test circuits 503, 504, 505, 506,
Priority circuit 507, level selection circuit PI308,
and an OR circuit 509. The storage units 501 and 502 store the instruction storage circuit 4 for one request.
The unit of instruction words read from 08 is a block unit, and the storage unit has m sets and n levels.

Referring to FIG. 3, a part of the instruction address of a branch instruction and a V bit indicating whether or not its contents are valid are stored in a storage unit 501, and a real address of a branch destination address is stored in a storage unit 502. ing. The V bit indicates the validity of the word in the corresponding branch history table (BHT) 410 and also functions as a branch success/failure flag as a prediction of execution of the branch instruction.

Indexing into the branch history table (BIT) 410 is performed by the set associative method as described below.

Test circuits 503, 504, 505, and 506 shown in FIG. A signal indicating whether the corresponding suffix is registered in
Output to 1133. Referring to FIG. 4, each of the test circuits 503, 504, 505 and 506 has -
It is composed of a numerical circuit 701 and a magnitude comparison circuit 702.

In the minus number circuit 701, the instruction address register (IA
R) Part of the request address held in 411 JA
The contents of each level of the storage section 501 read with R (: 4-17) as a set address are compared with the contents JAR (: 4-17) of the register 411, and it is detected whether or not an equal address exists. do. - 8B of the instruction word to be read at the request address held in the instruction address register (IAR) 411 by the output of the number circuit 701;
The branch history table (BH
T) It is determined whether a branch instruction registered in 410 exists. However, the above-mentioned coincidence detection alone is not sufficient to establish a correspondence between the request address and the branch instruction from which it should be read. Referring to FIG.
Instruction BCO, A, BCI.

There are four instructions of BO2. Instructions BCO, BCl,
When both BO2 are branch instructions predicted to be branch successes, part of the address of each branch instruction is registered in the storage unit (BHT-AA) 501. At this time, branch to instruction A from another branch instruction and address <A> of instruction A.
is held in the instruction address register (JAR) 411 as a request address for reading the block of instruction words, the branch history table (BHT) 4
The branch instruction information to be read from 10 must be the information of the branch instruction BCI from the instruction execution path.

Therefore, the request address held in the register (FAR) 411 and the period tα part (B I T -AA
i) When the relationship between the address of the branch instruction held in 501 and the above-mentioned one-lose condition is satisfied, the BHT-HITi signal of the corresponding level is generated. Note that this signal is given to the OR circuit 509 via lines 130 to 133, and the OR signal of the BHT HITi signal is output via the line 106 to generate a branch prediction signal (BHT
-HIT signal).

BIT −HITi = (IAR(:4 17) =
BIIT-AAi(:4-17) ) n (FAR(:29,30) ≦BIT-AAi(:
29.30) ) n B) IT-AAi (V) Referring again to FIG. 4, the magnitude comparison circuit 702 is
This is a circuit that realizes this condition.

Furthermore, when the condition of the signal BHT-HITi is satisfied at two or more levels, the address BHT-AA i in the 8-byte block of the address of the branch instruction held at the corresponding level (BHT-AA i) in the storage unit 501
The level with the smallest value of (:29.30) needs to be selected. Referring again to FIG. 5, the signal BHT-H[Ti
Both conditions hold true. At this time, the level for the instruction BC1 needs to be selected from the instruction execution path.

The priority circuit 507 receives the signal BHT-H.
This is for the establishment of two or more ITi, and this output sets the set address I of the storage unit BHT-DA502.
The branch destination address of the entry indicated by AR (: 18-28) is read out via the level selection circuit 508.

Referring to FIG. 6, the priority circuit 507 includes AND circuits 601-604 and OR circuits 605-60.
It consists of 8. AND circuits 601 to 604 are Q
+1 pieces are arranged in parallel. The n level selection signals of the level selection circuit 508 in FIG. 2 are the signals v, , v, , v, , v in FIG.

is given as follows.

V, no time VoL++, V(ILI
,-,VaL.

When Vo-V, VrLo, V+L+,
・”, νlL++v, −v, −v, cv
VzL, o, VzL+, -, VtLlIVo'
Vr ・V2' V, (7) when VxLo, V
3L,,-,V3L.

As described above, the level selection circuit 508 in FIG.
The branch information read from the instruction storage circuit 408 in FIG.
It is possible to associate the instruction with the instruction read from the .

FIG. 9 shows the correspondence between instructions in the instruction storage circuit 408 and branch information in the branch history table (BIT) 410. Instruction execution order is instruction AO
, branch instructions BCO, Bl, BC1, B2 . B3. BC2
, C1, C2, and so on. In addition, <
A> indicates the address of the human instruction, and BCj indicates the branch instruction.

Referring to FIG. 10, the instruction prefetching operation by the branch history table (BIT) 410 shown in FIG. 9 is performed as follows. In response to the setting of the instruction address register 411 of the request address, the instruction storage circuit 408
The instruction word is read from the table (BHT
) 410 are indexed. BHT- via signal line 106
When the HIT signal is output, the storage unit BHT-DA5f)2
The branch destination address <B1> is set in the address register 411, and the next instruction is prefetched. When the BHT-HIT signal is not output through the signal line 106, an 8-byte boundary address (person) to the instruction is given to the instruction address addition circuit 412, and the address to which "8" is added is output, and the next instruction is prefetched. are performed sequentially.

According to the above instruction prefetch, the instruction words read from the instruction storage circuit 408 are read out sequentially according to the prediction based on the contents of the table (BHT) 410, and are stored in the instruction buffer 409 in the predicted execution order of the instructions. It is possible.

At this time, even if the signal BHT-HIT is output, the instruction prefetch operation in the branch prediction direction may be performed after a part of the instruction prefetch operation in the opposite direction to the branch prediction direction is performed.

When the instruction prefetched as described above is a branch instruction and guided to the instruction decoding circuit 403 by the instruction alignment circuit 414 in FIG. ) is set.

Thereafter, as the processing of the branch instruction progresses, the branch information is sequentially changed to 2. Third. 4th. Fifth branch information register (Q
R1) 417. (QR2) 418. (QR3)
419, transferred to (QR4) 420. And OA.

Prediction confirmation circuit 424 for each stage of OT, ○C, EX
425, 426, and 427, the actual execution result of the branch instruction and the corresponding branch information are checked at each stage.

Referring to FIG. 11, the OA stage prediction confirmation circuit 424 includes flip-flops 1101.1102. Knot circuit 1103. and an AND circuit 1104. A signal indicating a branch instruction output from the instruction decoding circuit 403 is sent to flip-flops 1101 and 1102 via a signal line 113, and a V bit held by a branch information register (QRO) 416 is sent via a signal line 115, respectively. Ru. NOT circuit 1103 and AND circuit 110
4, the output of Furi, Bufronopl]01 becomes “0”.
” and the output of the flip-flop 1102 is “l”, that is, as a result of decoding the instruction, there is branch information corresponding to an instruction that is not a branch instruction, and the instruction is prefetched according to the branch information, the signal is OA to line 121
Output stage prediction failure signal.

Referring to FIG. 12, the OT stage prediction confirmation circuit 425 includes flip-flops 1201.1202.12.
03°1204, truth/false circuits 1206, 1207, and AND circuit 120B.

1209.1210. and OR circuit 1211.121
2.1213. In flip-flops 1201 and 1202, a bit indicating an unconditional branch instruction and a bit indicating a BCT instruction held in the register 435 are set via the signal line 122, respectively, and the flip-flop 1203 has a bit indicating the unconditional branch instruction held by the register 435 via the signal line 123. The count value l signal output from the circuit 433 is sent, and the V bit held in the branch information register (QRI) is set in the flip-flop 1204 via the signal line 126.
The OR circuit 1213 is supplied with the output of the OA stage prediction failure signal output from the OA stage prediction 41 LW circuit 424 and held in the flip-flop 436 via the signal line 144 . True/false circuit 1206.120? , AND circuits 1208, 1209, and 1210 change the outputs of flip-flops 1201, 1204 to “l” and “, respectively.
0", that is, when the corresponding branch information does not exist even though it is an unconditional branch instruction, and the instruction to the branch Go side is not prefetched, the output of the AND circuit 1208 becomes "
1', flip-flop 1202.1203°1
When the outputs of 204 are 'l', '0', and '0', respectively, it is a BCT instruction and the count value held in the general-purpose register specified by the BCT instruction is not '1', and a branch is executed. If there is no corresponding branch instruction (and the prefetch operation to the branch Go side is not performed), the output of the AND circuit 1209 becomes 1'', and the outputs of the flip-flops 1202, 1203, and 1204 all become 1''. 1” - that is, it is a BCT instruction and its BCT
The count value held in the general-purpose register specified by the instruction is “1”
”, and when there is branch information corresponding to a BCT instruction that does not perform a branch and an instruction prefetch operation is performed on the branch GO side, the output of the AND circuit 1210 is 1”
become. Furthermore, OR circuit 1211.1212.1213
When an unconditional branch instruction or a BCT instruction that performs a branch is not prefetched to the branch Go side, the OT stage Go prefetch instruction signal is sent to the signal line 13.
1, the OT stage prediction failure signal is sent to the signal line 129,
T stage BHT update instruction signals are output to signal lines 130, respectively. Furthermore, when a BCT instruction that does not perform a branch is prefetched to the branch GO side, an OT stage prediction failure signal and an OT stage BHT update instruction signal are output. Note that the OT stage BIT update instruction signal is generated when a prediction failure is detected at the OA stage, and the 0'A stage prediction confirmation circuit 424 sends the OA stage prediction failure signal to the flip-flop 436, and its output is sent to the signal line. 144 is also output.

Referring to FIG. 13, the OC stage prediction confirmation circuit 4
26 are registers 1301.1302. Flip-flop 1303. Comparison circuit 1306 for detecting mismatch. Truth/False Circuit 130? , AND circuit 1308 and OR circuit 13
09.1310. register 1301
The branch destination address actually obtained from the instruction word of the branch instruction given from the instruction address conversion circuit 402 via the signal line 133 is set in the register 130.
2 is set with the predicted branch destination address given from the branch information register (QR2) 418 via the signal line 137. Similarly, the V bit held in the branch information register (QR2) 418 is sent to the flip-flop 1303, and the truth/false circuit 1307 and the OR circuit 131 are sent to the flip-flop 1303.
0 is the O output from the OT stage prediction confirmation circuit 425.
Flip-flops 437 and 438 receiving the T stage BHT update instruction signal and the OT stage GO preemption instruction signal
outputs are provided via signal lines 157 and 158, respectively. The comparison circuit 1306, the truth/false circuit 1307, and the AND circuit 1308 cause the comparison circuit 1306, the output of the flip-flop 1303, and the signal line 157 to be set to "l", 'l', and "0", respectively, that is, the branch corresponding to the branch history table. For the instruction for which information exists and the subsequent instruction is prefetched according to the branch information, OA,
○In the prediction of the T stage, if no prediction failure is detected in the first recognition circuit and the predicted branch destination address is different from the actual branch destination address, the output of the AND circuit on the 130th day will be “1”. ”, and an OC stage prediction failure signal is output to the signal line 140. At the same time OR circuit 13
09 and 1310, the OC stage BIT update instruction signal and the OC stage GO preemption instruction signal are respectively
? It is output on 1156 and 141. Further, the OC stage BIT update instruction signal and the OC stage GO update instruction signal are the OT stage BIT update instruction signal and the OT stage G output from the OT stage prediction confirmation circuit 425, respectively.
Flip-flop 437 receiving the O preemption instruction signal;
It is also output when the output of 438 becomes "1".

Referring to FIG. 14, the EX stage prediction confirmation circuit 427 operates through flip-flops 1401. Truth/false circuit 140
2, 1403.1404. NAND circuit for negation of logical product 1405.1406. AND circuit 1407.140
8. and an OR circuit 1409. The truth/false circuit 1402 is connected to the instruction execution circuit 4 via a signal line 149.
The branch success/failure signal output from 07 is given to the flip-flop 1401, and the branch information register (QR3) 41
The ■ bit held by 9 is set, and the NAND circuit 140
5.1406 and the signal line 159 connected to the OR circuit 1409 is supplied with the output of the flip-flop 439 that has received the OC stage BHT update instruction signal, and the truth/false circuit 1
The output of the flip-flop 440 that has received the OC stage Go preemption instruction signal is applied to the signal line 404 via the signal line 160. The above truth/false circuit 1402.1403.14
04. NAND circuit 1405.1406. AND circuit 14
07.1408, branch success/failure signal of signal &'1149, output of flip-flop 1401, signal line 159
．． The signal lines 160 are 1", "O", "1", and "1", respectively.
'', that is, branch N0 to prefetch the subsequent instruction according to the prediction.
The instruction sent to the GO side is actually a branch GO, and a branch success/failure signal is output, and even if prediction failure for that instruction is not detected or detected by the OC stage, the GO side Only when a prefetch instruction is not output to the AND circuit 1407, the output of the AND circuit 1407 becomes "1", and the signal line 149. The output of flip-flop 1401 and signal lines 159 and 160 are “0” and “I”, respectively.
, "1", "O", that is, the instruction predicted to be a branch GO and prefetching the subsequent instruction to the branch Go side is actually a branch N0GO, and the branch success/failure signal is not output and the instruction is not executed until the oC stage. Sometimes a prediction failure for that instruction is not detected, or even if it is detected, the G
AND circuit 1 only when there is a preemption instruction to the o side.
The output of 408 becomes "1". Furthermore, the OR circuit 14o9 determines whether a prediction failure has been detected by the OC stage or the instruction predicted as branch GO is actually branch N.
0GO and a preemption instruction to the branch N0GO side has not been output by the OC stage, and the branch N0G
An instruction predicted as O is actually a branch GO and an OC
When a prefetch instruction to the branch GO side has not been output by the stage, an EX stage BHT update instruction signal is output to the signal line 148.

Referring to FIG. 15, the instruction prefetch control circuit 423
is a flip-flop 1501. Truth/false circuit 1502゜1
503.1504, 1505, 1506, 1507.7
7th circuit 1508.1509゜1510, 1511.1
512.1513.1514.1515.1516.1
517.1518. This instruction prefetch control circuit 423 receives the prediction failure signal output from the prediction confirmation circuit of each stage of OA, OT, QC, and EX, and the E
EX stage BHT update instruction signal output from the X stage prediction confirmation circuit 427 and branch history table 41
Based on the BHT-H, IT signal outputted by 0, a selection instruction signal is output for the selector at the stage before the instruction address register 411 and the selector at the stage before the instruction address recovery register 428.

When all the input signals of the instruction prefetch control circuit 423 are "0", the input selector of the instruction address register 411 is controlled to select the +8 instruction address output from the instruction address addition circuit 412 on the signal line 107, and the next In the machine cycle, the selected instruction address +8 is written to the instruction address register 411. Signal line 1
EX stage prediction confirmation circuit 427 via 48.147
When the EX stage BHT update instruction signal and the EX stage prediction failure signal are given, the instruction address recovery register 428 receives the output of the selection circuit 422 controlled by the branch success/failure signal output from the instruction execution circuit 407, that is, the actual branch. As a result of the determination, if the branch is Go, the branch destination address actually obtained by the instructions of the instruction word held in the branch information register (QR4) is also transferred to the instruction execution circuit 40.
If the result of branch determination in step 7 is NOGO, the address on the branch NOGO side output by the address generation circuit 433 is
In either case, the command is sent via the signal line 155, and at the same time the instruction address register 411 contains a branch information register.
The address of the branch instruction itself held by (QR4) is set via the signal line 151. Furthermore, one machine cycle later, if all the input signals are "0", the instruction prefetch control circuit 423 stores the EX stage BHT update instruction signal in the instruction address register 411 by the output of the flip-flop 1501 that holds the EX stage BHT update instruction signal for one machine cycle. controls so that the address of the next instruction to be executed based on the actual branch judgment result set in the instruction address recovery register 428 one machine cycle ago is sent via the signal line 162.

When the EX stage prediction failure signal on the signal line 147 is “0”, the ○C stage prediction confirmation circuit 42 is sent via the signal line 140.
When the OC stage prediction failure signal is given from 6, the instruction prefetch control circuit 423 registers the instruction address register 411.
, the OC held in the branch information register (QR3) 419
Control is performed to set the branch GO side address obtained from the instruction word of the instruction in the stage via the signal line 143. At this time, if the EX stage BHT update instruction signal is also given at the same time, the branch destination address of the instruction in the OC stage held in the branch information register (QR3) 419 is set in the instruction address recovery register 428, and the branch destination address of the instruction in the OC stage held in the branch information register (QR3) 419 is set in the instruction address recovery register 428, contains the branch information register (Q
R4) The instruction address of the instruction in the EX stage held by 420 is set, and after one machine cycle,
If all inputs to the instruction prefetch control circuit 423 are 0'', the actual branch Go side address of the instruction that was set in the instruction address recovery register 428 one machine cycle ago and was in the OC stage one machine cycle ago. is set in the instruction address register 411.

When the prediction failure signals of both the EX and QC stages on signal lines 147 and 140 are both “0”, OT is sent via signal line 129.
When an OT stage prediction failure signal is given from the stage prediction confirmation circuit 425, the instruction prefetch control circuit 423 determines whether the output of the selection circuit 421, that is, the instruction in the OT stage, is an unconditional branch instruction or is actually a BCT instruction that performs a branch. When the corresponding branch information does not exist in the branch history table and the branch N0GO side is prefetched,
The branch GO side address output by the instruction address conversion circuit 402 is 2. In addition, when the BCT instruction does not actually perform a branch and the corresponding branch information is successively output from the branch history table and the subsequent instruction is prefetched to the branch GO side, the address on the branch N0GO side output by the address generation circuit 431 is However, in both cases, the OT stage prediction confirmation circuit 42
The result selected by the selection circuit 421 is controlled to be set in the instruction address register 411 via the signal line 139 under the control of the OT stage Go prefetch instruction signal outputted via the signal line 131. At this time, E
If the X stage BHT update instruction signal is also given, the output of the selection circuit 421 is transferred to the instruction address recovery register 428.
Instead, the instruction address of the instruction in the EX stage held in the branch information register (QR4) 420 is set in the instruction address register 411 via the signal line 151, and one machine cycle later, the instruction prefetch control is executed. If all the inputs of the circuit 423 are "O", the instruction address recovery register 428 is set one machine cycle ago, and the unconditional branch instruction or BCT instruction that was in the OT stage one machine cycle ago. Control is performed so that an address for refetching the instruction is set in the instruction address register 411 via the signal line 162.

When the prediction failure signals of the EX, ○C, and OT stages on the signal lines 147, 140, and 129 are "0," when the OA stage prediction failure signal is given from the OA stage prediction confirmation circuit 424 via the signal line 121, , instruction prefetch control circuit 4
23 controls so that the instruction address on the branch N0GO side of the instruction in the OA stage outputted by the address generation circuit 430 is set in the instruction address register 411 via the signal line 128. At the same time, if the EX stage BHT update instruction signal is given, the output of the address generation circuit 430 is set to the instruction address recovery register 428, and the instruction address register 411 instead stores the output of the branch information register (QR4) 420. The instruction address of the instruction in the EX stage is set via the signal line 151, and one machine cycle later, if all inputs to the instruction prefetch control circuit 423 are "0", the instruction address recovery is performed one machine cycle before. The address set in the register is transferred to the instruction address register 4 via the signal line 162.
control so that it is set to 11.

EX, QC of signal line 147.140.129.121,
O.T.

When the prediction failure signals of each stage of OA are all “O”, B is sent from the branch history table 410 via the signal line 106.
When the HT-HIT signal is given, the instruction prefetch control circuit 423 selects the IC output from the branch history table 410.
The predicted branch address of the instruction in the stage is controlled to be set in the instruction address register 411 via the signal line 105. At this time, if the EX stage BHT update instruction signal is also given at the same time, the branch destination address read from the branch history table 410 on the signal line 105 is set in the instruction address recovery register 428, and the instruction address register 411 is filled with the branch destination address instead. The instruction address of the instruction in the EX stage is the branch information register (QR4)
420 via the signal line 151, and its l
After a machine cycle, if all inputs to the instruction prefetch control circuit 423 are "O", control is performed so that the contents of the instruction address recovery register 428 that were set one machine cycle ago are set in the instruction address register 411.

Signal line 147, 140, 129.121 (7) EX,
QC, O.T.

Prediction failure signal of each OA stage and B of signal line 106
When the EX stage BHT update instruction signal is given from the EX stage prediction confirmation circuit 427 via the signal line 148 when all the HT-HIT signals are "0", the instruction prefetch control circuit 423 sends the signal line to the instruction address recovery register 428. 107, the output of the instruction address adder circuit 412 is sent to the instruction address register 411, and the instruction address of the instruction in the EX stage is sent to the branch information register (QR).
4) Cent from 420 via signal line 151, part 1
After a machine cycle, if all inputs to the instruction prefetch control circuit 423 are 0'', control is performed so that the address set in the instruction address recovery register 428 one machine cycle ago is set in the instruction address register 411.

Next, the operation of this embodiment will be explained in detail with reference to FIG. 1 and time charts.

FIG. 17 shows that erroneous branch information that specifies the address of instruction A1, which is not a branch instruction, as the address of the branch instruction exists in the branch history table 410, and the instruction prefetch control circuit 423 executes the instruction following instruction A1 according to the erroneous branch information. 3 is a time chart showing an operation in which an instruction C1 is extracted and executed as an instruction.

Referring to FIGS. 1 and 17, machine cycle 0
At time , the address A1 of an instruction Al that is not a branch instruction is set in the instruction address register 411,
The Ic stage of instruction Al is executed. address<At
> is a signal &i! 101 to the instruction storage circuit 408 for fetching the instruction word, and is also provided to the branch history table 410 at the address <AI>
Branch information that specifies the address of the branch instruction is retrieved.

As a result, incorrect branch information is retrieved and the BHT-HIT
A signal is output on signal line 106. Therefore, the instruction prefetch control circuit 423 inputs the branch destination address obtained from the branch information to the input selector of the instruction address register 411.
The signal line 105 to which C1> is output is instructed to be selected.

At the time of the next machine cycle 1, the branch destination address C1 due to the incorrect branch information is set in the instruction address register 411, the IC stage of the instruction CI is executed, and the ID stage of the instruction AI is executed. Ru. Since the instruction A1 is not a branch instruction, the instruction decoding circuit 403 outputs "0" to the signal 113 indicating that the instruction decoding result is a branch instruction, and confirms the OAX stage prediction that the instruction AI is not a branch instruction. In addition to notifying the circuit 424, the instruction word length of the instruction AI is sent to the branch 1n report register (
QRl ) 417 to signal line 112 . At the same time, the address A1 of the instruction AI held in the branch information register (QRO) 416, the V bit, and the V bit of the branch destination address C1 are output to the signal line 115.

At the time of machine cycle 2, the ID stage of the instruction C1 and the IC stage of the instruction C2 subsequent to the instruction CI are executed, and the OAX stage of the instruction A1 is executed. At the same time, the OAX stage prediction confirmation circuit 424 determines that branch information exists even though the instruction A1 currently in the OA stage is not a branch instruction, based on the information given via signal lines 113 and 115 in the previous machine cycle. An OA stage prediction failure signal indicating that a subsequent instruction has been prefetched to the signal line 121 is output to the signal line 121. At the same time, the address generation circuit 430 generates a branch information register (QR2) 4.
Address <AI> of instruction AI held by 18 and instruction A1
N of instruction A1.

The address A2> of the subsequent instruction on the GO side is generated and output onto the signal line 128. The instruction prefetch control circuit 423
OAX stage prediction confirmation circuit 424 output signal line 12
1 OA stage prediction failure signal causes the input selector of the instruction address register 411 to receive the OA stage prediction failure signal on the signal line 128.
An instruction is given to select the address A2> on the branch N0GO side of the instruction At of the X stage. Further, since the OA stage prediction failure signal is output, all operations of instructions CI and C2 subsequent to the prediction side in the stage before the OAX stage are canceled.

In machine cycle 3, the OT stage of instruction Al is executed, and at the same time, the address <A2> of the instruction subsequent to instruction A1 is written to the instruction address register 411.
The IC stage of instruction A2 is also executed. Flip-flop 436 is set to l'' in response to the OA stage prediction failure signal output in the previous machine cycle, and indicates that the branch information of instruction A1 currently in the OT stage is incorrect and must be updated correctly. show.

In the next machine cycle 4, instruction A1 executes the ○C stage and the ID stage of instruction A2.

The IC stage of instruction A3 subsequent to instruction A2 is executed. The flip-flop 437 includes the flip-flop 43
6 is received, “1” is set, and the flip-flop 43
8 holds "θ', and also indicates that the branch information of instruction A1 currently in the OC stage is incorrect and needs to be updated correctly, and that the subsequent instruction prefetch according to the prediction for instruction A1 is canceled. This indicates that the instruction prefetch operation to the N0GO side has already been executed anew.

In machine cycle 5, the EX stage of instruction AI is executed. Since the instruction A1 is not a branch instruction, the instruction execution circuit 407 outputs "0" indicating branch N0GO to the branch success/failure signal on the signal line 149. Therefore, the selection circuit 422 selects the address A obtained by adding the address <A1> of the instruction AI held in the branch information register (QR4) and the instruction word length of the instruction A1 in the address generation circuit 432.
2> is selected and output on the signal line 155. Further, the address A1> of the instruction A1 is output to the signal line 151.

On the other hand, flip-flops 439 and 440 receive the contents of flip-flops 437 and 438 through the OC stage prediction confirmation circuit 426, and are set to 1'' @ Q 11. signal and the branch information register (QR3) provided via signal line 146 in the previous machine cycle.
) 419 and the flip-flops 439 and 440, the EX stage BHT update instruction signal on the signal line 14 is output as "
1" and outputting "0" to the EX stage prediction failure signal on the signal line 147 indicates that branch information regarding instruction A1 exists, and the subsequent instruction is prefetched to the branch Go side according to that information. Nevertheless, instruction A1
does not actually perform a branch operation, however, since the subsequent erroneous branch prefetch operation has been canceled and the instruction fetch operation to the branch N0GO side has already been performed,
The EX stage indicates that there is no need to instruct redoing the instruction prefetch, and also indicates that it is necessary to update the branch information regarding the instruction A1. In response, the instruction prefetch control circuit 423 instructs the input selector of the instruction address register 411 to select the address <Al> of the instruction AI on the signal line 151, and instructs the input selector of the instruction address recovery register 428 to select the address <Al> of the instruction AI on the signal line 151. The signal line 107
Instruct to select the address <A2>+24 above.

At this time, if branch information corresponding to the address <A2>+16 held by the instruction address register 411 exists in the branch history table, and the BHT-HIT signal is
6, the instruction prefetch control circuit 423 sends the input selector of the instruction address recovery register 428 a branch indicating the branch information retrieved from the branch history table 410 outputted on the signal line 105. The destination address is also O for instruction A2 in the OA stage.
If an OA stage prediction failure signal is given from the A stage prediction confirmation circuit 424 via the signal line 121, the signal line 12
Instruct the user to select the address above 8.

In the next machine cycle 6, instruction A1 executes the HU stage in which the branch information for instruction A1 in branch history table 410 is updated. First, the flip-flop 441 is set to "1" in response to the EX stage BHT update instruction signal output on the signal line 148 in the previous machine cycle, and its output is sent to the branch history table 410 via the signal line 154. It will be done. Also, in the register 434, the signal line 155 is also stored in the previous machine cycle.
The instruction address A2〉 that was output on the signal line 151 in the previous machine cycle is set in the instruction address register 411, and the instruction address A1〉 that was also output on the signal line 151 in the previous machine cycle is also set in the instruction address recovery register 428.
The address <A2>+24, which was output on the signal line 107 in the previous machine cycle, is sent to each of the addresses.

In response, instruction A in branch history table 410
The branch information for A1 is updated, the v bit of the branch information for A1 is reset, and from now on the instruction A
I is no longer treated as a branch instruction. On the other hand, at this time, the instruction prefetch control circuit 423 controls the instruction address register 41
The input selector No. 1 is instructed to select the address <A2>+24 held by the instruction address recovery register 428 that is output on the signal line 162.

At this time, for instruction A2 in the OT stage, O
When an OT stage prediction failure signal is given from the T stage prediction confirmation circuit 425 via the signal line 129, the instruction prefetch control circuit 423 causes the manual selector of the instruction address register 411 to select the address on the signal line 139. , and the instruction A3 in the OA stage is outputted from the OA stage prediction confirmation circuit 424 via the signal line 121.
If the A stage prediction failure signal is given, signal line 128
Instruct them to select the address above.

After machine cycle 7, the instruction address register 411
The instruction prefetch operation continues according to address <A2>+24, which was sent to <A2>+24.

FIG. 18 shows a BCT in which there is no corresponding branch information in which the V bit is “l” in the branch history table 410.
This is a time chart showing the execution of instruction B1, which is an instruction or an unconditional branch instruction. When B1 is a BCT instruction, the count value specified by instruction Bl is not "1", but
Even if a counting operation of -1 is performed, the counting result will not be "0".Actually, this shows the case of a BCT instruction that performs a branch.

Referring to FIG. 1 and FIG. 18, at the time of machine cycle 0, the address of instruction B1, which is a BCT instruction or an unconditional branch instruction, is set in the instruction address register 411, and the IC stage of instruction B1 is executed. Ru. The address B1> is applied to the instruction storage circuit 408 via the signal 101 to fetch the instruction word, and is also applied to the branch history table 410, where the instruction B1 is
The branch information corresponding to 1 is taken out, and at the same time, it is also given to the instruction address addition circuit 412, and the address
l〉+8 is generated. Since there is no branch information corresponding to instruction B1 in the branch history table 410, “0” is output as the BHT-HIT signal on the signal line 106. In response, the instruction prefetch control circuit 423 sends the signal line 1 to the input selector of the instruction address register 411.
07 to select the address B1>+8.

At the time of the next machine cycle 1, the address <31>+B is set in the instruction address register 411, and the IC of the subsequent instruction A1 on the branch N0Go side of the instruction B1 is set.
The stage is executed. At the same time, the branch information register (Q
RO) 416 contains the address B1> and V of the instruction B1.
"0" is written as a bit, and the ID stage of instruction B1 is executed.

The instruction decoding circuit 403 uses a signal line 114 to determine that the instruction Bl is a BCT instruction or an unconditional branch instruction.
Output to.

At the time of machine cycle 2, the OA stage of instruction B1, the ID stage of instruction AI, and the IC stage of instruction A2 subsequent to instruction A1 are executed. register 43
5 indicates on the signal line 122 that the instruction Bl is a BCT instruction or an unconditional branch instruction in response to the output of the signal line 114 of the previous machine cycle. The branch information register (QRl) 417 contains a branch information register (QRl).
address held by O) in the previous machine cycle <B
1> and the V bit which is “0” is set, and the ■ bit is further output to the signal line 126. The instruction address generation circuit 401 generates a branch destination address for the instruction B1, and when the instruction B1 is a BCT instruction, the value of the general-purpose register holding the count value specified by the instruction B1 is output from the operand address generation circuit 404 to the signal line 120. Comparison circuit 43 via
given to 3. The comparison circuit 433 detects that the given count value is not "1" and sets the count value 1 on the signal line 123.
Outputs “0” as a signal.

In machine cycle 3, the ○T stage of the instruction B1 is executed, the branch destination address of the instruction B1 is converted to the real address <C1> by the instruction address conversion circuit 402, and the subsequent instruction on the branch N0GO side of the instruction B1 is A
1. A2. A3 OA.

ID and IC stages are executed. OT stage prediction 6
1 L'2 circuit 425 uses the information given via signal lines 122.123.126 in the previous machine cycle to
BCT where the instruction currently in the OT stage is branch Go
Even though it is an instruction or an unconditional branch instruction, the corresponding branch information is not included in the branch history table 41.
0 was not hit, and the prefetching of subsequent instructions to the branch N0GO side continued. Therefore, it was necessary to execute prefetching of the instruction B1 again to the branch Go side, and branch information regarding instruction B1. In order to indicate that it is necessary to update correctly, an OT stage prediction failure signal is output to the signal line 129, an OT stage BHT update instruction signal is output to the signal line 130, and an OT stage GO preemption instruction signal is output to the signal line 131. do. In response to this OT stage GO preemption instruction signal, the selection circuit 421 selects the signal line 13
The branch destination address of the instruction Bl outputted to the signal line 139 is selected and outputted onto the signal line 139. The instruction prefetch control circuit 423 uses the signal line 1 output from the OT stage prediction confirmation circuit 425.
The OT stage prediction failure signal No. 29 instructs the input selector of the instruction address register 411 to select the branch destination address <C1> of the instruction B1 on the signal line 139.

Furthermore, since the OT stage prediction failure signal is output, instructions AI, A2 . All operations of A3 are canceled.

In machine cycle 4, the OC cycle of instruction B1 is executed, and at the same time, the branch destination address <C1> of instruction B1 is set in the instruction address register 411, and the IC stage of instruction C1 at address C1> is also executed. Flip flop 43? , 43s receive the OT stage BHT update instruction signal and the OT stage Go preemption instruction signal output in the previous machine cycle, and are both set to "11".

In the next machine cycle 5, the EX stage of instruction B1 is executed. If the instruction B1 is a BCT instruction, the instruction execution circuit 407 performs the specified counting operation, and since the result is not "0", the instruction execution circuit 407 sets "1" indicating branch GO to the branch success/failure signal on the signal line 149. When B1 is an unconditional branch instruction, "1" is also output as the branch success/failure signal on the signal line 149. In response, the selection circuit 422
selects the branch destination address <C1> of the instruction Bl held in the branch information register (QR4) 420 and outputs it onto the signal line 155. At the same time, the address <31> of the instruction B1 held in the branch information register (QR4) 420 is output onto the signal line 151. On the other hand, flip-flop 43
9.440 receives the contents of flip-flops 437 and 438 through the OC stage prediction confirmation circuit 426, and both are set to "1". The EX stage prediction confirmation circuit 427 receives the branch success/failure signal on the signal line 149 and the branch information of the instruction B1 held in the branch information register (QR3) 419 given via the signal line 146 in the previous machine cycle. "1" is output as the EX stage BHT update instruction signal on the signal line 148 from the ■ bit which is "0" and the flip-flops 439 and 440, and the signal line 1
By outputting "O" to the EX stage prediction failure signal of 47, instruction Bl does not branch even though there is no branch information for instruction Bl and the subsequent instruction is prefetched to the branch N0GO side. However, since the instruction on the subsequent branch N0GO side has been canceled and the instruction on the branch Go side has already been fetched, it is not necessary to instruct the EX stage to redo the instruction prefetch. Indicates that branch information needs to be updated. In response, the instruction prefetch control circuit 423 sends the address of the instruction B1 on the signal line 151 to the input selector of the instruction address register 411.
instruction address recovery register 4.
The input selector 28 is instructed to select the address <CI>+16 on the signal line 107.

At this time, if the address <C1>+8 held in the instruction address register 411 is stored in the branch history table 41
If a BHT-HIT signal from 0 is applied via the signal line 106, the instruction prefetch control circuit 423 selects the branch extracted from the branch history table 410 on the signal line 105 for the input selector of the instruction address recovery register 428. Prompts you to select an address.

In the next machine cycle 6, instruction B1 updates the branch history table 410) and executes the U stage. The register 434 contains the instruction B1 on the signal vA155.
The branch destination address <C1> of the instruction address register 411 is set to the signal %151.
<CI>+16 is cented for each. On the other hand, the flip-flop 441 is connected to the signal line 1 in the previous machine cycle.
It is set to "1" in response to the EX stage BHT update instruction signal outputted on 48, and its output is given to branch history table 410 via signal line 154. In response, the branch history table 410 stores the branch information of address B1> with CI> as the branch destination address, and from now on, the instruction Bl is predicted to have C1> as the branch destination address. become.

On the other hand, at this time, the instruction prefetch control circuit 423 instructs the input selector of the instruction address register 411 to select the address <CI>+16 held by the instruction address recovery register 428 that is output on the signal line 162. At this time, if an OA stage prediction failure signal is given from the OA stage prediction confirmation circuit 424 via the signal vA121 for the instruction CI in the OA stage, the instruction prefetch control circuit 423 sends a signal line to the input selector of the instruction address register 411. 128 to select an address.

From machine cycle 7 onwards, the instruction prefetch operation continues according to the address <CI>+16 set in the instruction address register 411.

FIG. 19 is a time chart showing the execution of the BCT instruction BCTI for which there is branch information corresponding to the branch history table. shows the case of a BCT instruction in which the result is "O" and no branch is actually performed.

Referring to FIGS. 1 and 19, machine cycle 0
At the time of , the address of instruction BCTI <BCTI>
is set in the instruction address register 411, and the instruction BC
The TI's IC stage is executed. address<BCTI
> is applied to the instruction storage circuit 408 via the signal line 101, the instruction word is taken out, and is also given to the branch history table 410, where the branch information about the instruction BCTI is taken out. Branch history table 4
The branch information extracted from 10 is output onto signal line 105. At the same time, a BHT-HIT signal is output onto signal line 106. In response to this, the instruction prefetch control circuit 423 sets the manual selector of the instruction address register 411 to
An instruction is given to select the branch destination address <(, l>) of the instruction BCTI output to the signal line 105.

At the time of the next machine cycle 1, the instruction BCTI
The branch destination address C1> is the instruction address register 41
1, the IC stage of instruction C1 is executed, and the ID stage of instruction BCTI is executed. The instruction decoding circuit 403 outputs to the signal line 114 that the instruction BCTI is a BCT instruction, and at the same time outputs the signal to the signal line 11.
The instruction word length of instruction BCTl is output on 2.

In machine cycle 2, the OA stage of instruction BCTI, the 10th stage of instruction CI, and the IC stage of instruction C2 following instruction C1 are executed. register 435
In response to the output of the signal line 114 of the previous machine cycle, the signal line 122 indicates that the instruction BCTI is a BCT instruction.
Shown above. In the branch information register (QR1) 417, the branch information of the instruction BCTI held in the branch information register (QRO) in the previous machine cycle and the instruction word length of the instruction BCTI are set, and the ■ bit is set in the signal line 126. Output. The instruction address generation circuit 401 generates the instruction BCT1
The operand address generation circuit 404 outputs the value of the general-purpose register holding the count value specified by the instruction BCTI to the comparison circuit 43 via the signal line 120.
Output to 3. The comparison circuit 433 determines that the given count value is “
1'' is detected and a count value 1 signal is output to the signal line 123.

In machine cycle 3, the OT stage of the instruction BCTI is executed, and the branch destination address of the instruction BCTI is converted into a real address by the instruction address conversion circuit 402, and the OT stage of the instruction C3 following instructions C1, C2, and C2 is executed.
A, ID, and IC stages are each executed. The OT stage prediction confirmation circuit 425 determines whether the instruction BCTI in the OT stage is a branch N0GO BCT instruction based on the information given via the signal lines 122, 123, or 126 in the previous machine cycle. The branch information hinted in the branch history table 410 that the subsequent prefetching to the branch GO side was performed, and therefore the subsequent prefetching of the instruction BCTI to the branch N0GO side needs to be executed again, and the instruction In order to indicate that the branch information regarding BCTI needs to be updated correctly, an OT stage prediction failure signal is output to the signal line 129, an OT stage B HT update instruction signal is output to the signal line 130, and the OT stage B HT update instruction signal is output to the signal line 131. "O" is output as the OT stage Go preemption instruction signal. In response, the selection circuit 421 selects the address <Al> of the next instruction on the branch N0GO side of the instruction BCTI outputted to the signal line 138 by the address generation circuit 431 and outputs it to the signal line 139, thereby preempting the instruction. The control circuit 423 controls the instruction address register 411
Address A on signal line 139 for the input selector of
Instruct the user to select 1>. Further, due to the output of the OT stage prediction failure signal, the operations of the instructions C1, C2, and C3 subsequent to the branch GO side before the OT stage are all canceled.

In machine cycle 4, the 0C cycle of the instruction BCTI is executed, and at the same time, the instruction address register 4112 is set to the instruction A1 that follows the branch N0GO side of the instruction BCTl.
address A1> is sent, and the IC stage of instruction AI is executed. Flip-flops 437 and 438 output the OT stage BHT in the previous machine cycle.
In response to the update instruction signal and the OT stage GO prefetch instruction signal, they are set to @1'' and 10'', respectively. The OC stage prediction confirmation circuit 426 checks the instruction B held in the branch information register (QR2) 418 in the previous machine cycle.
The predicted branch destination address <C1> of CTI and the V bit are sent via the signal line 137, and the actual branch destination address obtained by the specification of the command word of the instruction BCT1 is sent to the signal line 13.
3 from the instruction address conversion circuit 402, and it is detected whether the predicted branch destination address <C1> is correct. However, since the flip-flop 437 is set to "1", even if the branch destination address <C1> is incorrect, the OC stage prediction failure signal will not be output to the signal line 140, and the branch of the instruction BCTI at the OT stage will not be output. The prefetching to the branch GO side does not start again by canceling the operation of redoing the prefetching to the N0GO side.

In the next machine cycle 5, the EX stage of instruction BCTI is executed. The instruction execution circuit 407 executes the instruction BCT
Since the counting operation specified by I is performed and the result is "O", a branch N0 is sent to the branch success/failure signal on the signal line 149.
Outputs “0” indicating GO. In response, the selection circuit 422 selects the command BC output from the address generation circuit 432.
The address of the instruction A1 following the branch N0GO side of TI<
AI> is selected and output to the signal line 155. At the same time, the address <BCTI> of the instruction BCTI held in the branch information register (QR4) 420 is output to the signal line 151. On the other hand, the flip-flops 439 and 440 receive the contents of the flip-flops 437 and 438 through the oC stage prediction confirmation circuit 426 and are set to "1" and '0', respectively.
49 branch success/failure signal and signal m1 in the previous machine cycle.
Branch information register (QR3) given via 46
419 (7) Branch ta of held instruction BCTI
■ bit of tta, and flip-flop 439.4
40, outputs "1" as the EX stage BHT update instruction signal on the signal line 148, and outputs "O" as the EX stage prediction failure signal on the signal line 147, thereby proceeding to the branch GO according to the branch information of the instruction BCTI. Despite prefetching the subsequent instruction, the instruction BCTI is actually a branch N0GO; however, the subsequent erroneous instruction prefetching operation is canceled and the branch N0GO
; Indicates that there is no need to instruct redoing of instruction prefetching in the EX stage because the instruction fetching operation to the O side is being performed, and also indicates that it is necessary to update the branch information of the instruction BCTI. In response to this, the instruction prefetch control circuit 42
3 is the address of the instruction BCT1 on the signal line 151 for the input selector of the instruction address register 411<BCTI
> and instructs the input selector of the instruction address recovery register 428 to select the address <AI>+16 on the signal line 107. At this time, if the address held by the instruction address register 411<
If branch information corresponding to At>+8 exists in the branch history table 410 and the BHT-HIT signal is given via the signal line 106, the instruction prefetch control circuit 423 controls the input selector of the instruction address recovery register 428. instructs to select the branch destination address indicated by the branch information extracted from the branch history table 410 on the signal line 105. .

In the next machine cycle 6, instruction BCT1 executes the HU stage in which the branch information for instruction BCTI in branch history table 410 is updated. The instruction address <BCTI> is sent to the instruction address register 411, and the flip-flop 441 is set to "1" in response to the EX stage BHT update instruction signal output to the signal line 148 in the machine cycle of Jing. It is applied to branch history table 410 via signal WA154.

In response, instruction B in branch history table 410
The V bit of the CTI branch information is reset. On the other hand, at this time, the instruction prefetch control circuit 423 instructs the input selector of the instruction address register 411 to select the address <AI>+16 held by the instruction address recovery register 428 that is output on the signal line 162. At this time, regarding the instruction A1 in the OA stage, the OA stage prediction confirmation circuit 424 sends an output signal via the signal line 121.
Given the AX stage prediction failure signal, %12 to the signal
Instruct the user to select the address above 8.

After machine cycle 7, the instruction address register 411
Instruction prefetch operations continue according to the address set in .

Figure 20 shows the execution of an unconditional branch instruction for which branch information exists in the branch history table and a subsequent instruction is prefetched to the branch Go side, or a conditional branch instruction B1 that actually becomes a branch Go. This is a time chart showing a case where the branch destination address indicated by the branch information for the instruction B1 is actually different from the branch destination address designated by the instruction B1.

Referring to FIGS. 1 and 20, at the time of machine cycle 0, the address <Bl> of instruction B1, which is an unconditional branch instruction or a conditional branch instruction, is sent to the instruction address register 411, and the IC stage of instruction B1 is executed. be done. The address <B1> is applied to the instruction storage circuit 408 via the signal line 101 to retrieve the instruction word, and is also applied to the branch history table 410 to retrieve the branch information for the instruction B1. As a result, the branch history table 410 takes out the branch information for the instruction B1 and sends the branch destination address <C1> to the signal line 105.
At the same time, BHT-HIT is output on the signal line 106.
Output a signal. In response to this, the instruction prefetch control circuit 4
23 instructs the input selector of the instruction address register 411 to select the signal line 105 to which the predicted branch destination address C1> is output.

In the next machine cycle 1, the predicted branch destination address <C1> is written to the instruction address register 411, and the IC stage of the instruction C1 is executed, as well as the ID stage of the instruction B1.

In machine cycle 2, the ID stage of the instruction CI and the IC stage of the instruction C2 following the instruction C1 are executed, the ○A stage of the instruction B1 is executed, and the ○A stage of the instruction B1 is executed.
1 branch destination address is calculated by instruction address generation circuit 401 and the logical address is output on signal line 119.

In machine cycle 3, the OT stage of instruction B1 is executed, and the branch destination address of instruction B1 is converted by the instruction address conversion circuit 402 into a real address Dl>, which is output on the signal line 133, and the branch destination address of instruction B1 is ,C3
The OA, ID, and IC stages of are executed respectively. Branch information of the instruction B1 is set in the branch information register (QR2) 41B, and the predicted branch address <CI> and the V bit are output onto the signal line 137.

In machine cycle 4, instructions Bl, C1°C2, C
3. The OC, OT, OA, ID, and IC stages of C4 are respectively executed. oC stage prediction confirmation circuit 42
6 is the predicted branch destination address C1> of the instruction Bl given via the signal line 137 in the previous machine cycle, the V bit, and the instruction B given via the signal line 133.
The predicted branch destination address <C1> is compared with the actual branch destination address <Dl> specified by instruction word 1.
is detected to be incorrect, outputs an OC stage prediction failure signal to the signal line 140, and outputs an OC stage prediction failure signal to the signal line 156.
The C stage BHT update instruction signal is output to the signal line 141.
Each outputs a C stage GO prefetch instruction signal. The branch information register (QR3) 419 is set with the actual branch destination address <Dl> of the instruction B1 output on the signal line 133 in the previous machine cycle, and outputs the address <Di> on the signal line 143. Instruction prefetch control circuit 42
3 instructs the input selector of the instruction address register 411 to select the address <Dl> on the signal line 143 in response to the OC stage prediction failure signal on the signal line 140. Furthermore, due to the output of the OC stage prediction failure signal, the instructions C1, C2, which were prefetched according to the incorrect branch destination address C1 shown in the branch information of instruction B1,
All operations of C3 and C4 are canceled.

In machine cycle 5, instruction address register 4
Address Dl>, which is the actual branch destination address of the instruction B1, is set in 11, and the IC stage of the instruction D1 is executed, and the EX stage of the instruction B1 is executed. If the instruction 81 is a conditional branch instruction, the instruction execution circuit 407 determines the branch condition specified by the command word of the instruction Bl, and as a result, indicates a branch G to the branch success/failure signal on the signal line 149.
If the instruction El is an unconditional branch instruction, it also outputs "l" to the branch success/failure signal on the signal line 149. In response, the selection circuit 422 selects the actual branch destination address <pl> held in the branch information register (QR4) 420 and outputs it onto the signal line 155. or,
The address <B1> of the instruction B1 is output to the signal line 151. Flip-flops 439 and 440 receive the oC stage BHT update instruction signal output in the previous machine cycle and the OC stage G.

Upon receiving the preemption instruction signal, both are set to "l". The EX stage prediction confirmation circuit 427 determines that the incorrect subsequent instruction has been fetched according to the branch information for instruction Bl, but it has already been canceled and the instruction has been prefetched according to the correct address on the branch GO side. There is no need to instruct the redo of command preemption;
However, to indicate that the branch information for instruction B1 in the branch history table 410 needs to be corrected, "0" is set to the EX stage prediction failure signal on the signal line 147.
The EX stage BHT update instruction signal on the signal line 148 is “
1". In response, the instruction prefetch control circuit 4
23 is used to select the address B1 of the instruction B1 on the signal line 151 for the input selector of the instruction address register 411, and the instruction address recovery register 428.
Address on signal line 107 for human selector <DI
>+8. If at this time,
Address held by instruction address register 411<DI
If the branch information corresponding to An instruction is given to select the branch destination address indicated by the branch information retrieved from step 410.

In the next machine cycle 6, the HU stage of instruction B1 is executed, and the branch information for instruction B1 is updated. The instruction address register 411 is set to the address B1 of the instruction B1, the register 434 is set to the correct branch destination address D1 of the instruction B1, and the flip-flop 441 is set to the EX stage BHT output in the previous machine cycle. “1” is set in response to the update instruction signal, and the output is the signal! ! It is given to the branch history table 410 via jl154. In response, the branch information for the instruction Bl in the branch history table 410 is updated to indicate Dl> as the branch destination address. Meanwhile, at this time, the instruction prefetch control circuit 423 instructs the manual selector of the instruction address register 411 to select the output of the instruction address recovery register 428.

In machine cycle 7, the instruction address saved in the instruction address recovery register 428 is set in the instruction address register 411, and thereafter the instruction prefetch operation continues according to that address.

FIG. 21 is a time chart showing the state of execution of a conditional branch instruction BC1 in which there is branch information corresponding to the branch history table 410 and a subsequent instruction prefetch operation is performed on the branch Go side. The branch destination address indicated by is different from the branch destination address actually specified by the instruction BCI, and furthermore, the branch destination address indicated by the conditional branch instruction BCI
indicates a case where the branch condition is determined and the branch is NOGO.

Referring to FIGS. 1 and 21, the machine cycle O
, the address <BCI> of the conditional branch instruction BCI is set in the instruction address register 411, and the instruction BCI
The following IC stages are executed.

At the same time, the branch information of the instruction BCI is stored in the branch history table 4.
10 and as the predicted branch destination address
C1> is output on the signal line 105, and the BHT-HIT signal is output on the signal line 106.

In response, the instruction prefetch control circuit 423 sends signal line 1 to the input selector of the instruction address register 411.
Instructs to select address <CI> on 05.

In the next machine cycle 1, the predicted branch destination address (C1) of instruction B C1 is stored in the instruction address register 4.
11, the IC stage of instruction C1 is executed, and the 10 stage of instruction BCI is executed.

In machine cycle 2, the ID stage of the instruction C1 and the IC stage of the instruction C2 following the instruction C1 are executed, and the OAX stage of the instruction BCI is executed, and the branch destination address of the instruction BCI is set to the instruction address generation circuit 401.
The logical address is output on signal line 119.

In machine cycle 3, the OT stage of the instruction BCI is executed, and the branch destination address of the instruction BCI is converted by the instruction address conversion circuit 402 into a real address Dl> and output onto the signal line 133. Simultaneous two instructions C1, C
2, C3 OA, ID.

Each IC stage is also executed. Branch information of the instruction BCI is set in the branch information register (QR2) 418, and the predicted branch destination address <C1> and the V bit are output onto the signal line 137.

In machine cycle 4, instructions BCI, C1, C2
, C3, and C4, the QC, OT, OA, and 10°Ic stages are executed, respectively. The OC stage prediction confirmation circuit 426 receives the predicted branch destination address <C1> and ■ bit of the instruction BCI given via the signal line 137 in the previous machine cycle, and the instruction BC1 given via the signal line 133. It compares the predicted branch destination address <Dl> with the actual branch destination address specified by the instruction word, detects that the predicted branch destination address <Cl> is incorrect, and outputs an OC stage prediction failure signal to the signal line 140. At the same time, an OC stage BHT update instruction signal is sent to the signal line 156.
The six branch information registers (QR3) 419, which each output an OC stage GO prefetch instruction signal to the signal line 141, are set with the actual branch destination address <Dl> that was output to the signal line 133 in the previous machine cycle. Signal line 1
The address <Dl> is output on 43. In response to the OC stage prediction failure signal on the signal line 140, the instruction prefetch control circuit 423 instructs the input selector of the instruction address register 411 to select the address <Dl> on the signal line 143. Furthermore, since the OC stage prediction failure signal is output, the operations of the instructions C1, C2, C3, and C4, which were prefetched according to the incorrect branch destination address C1> indicated by the branch information of the instruction BCI, are all canceled.

In machine cycle 5, instruction address register 4
The branch destination address <Dl> obtained from the instruction word of the instruction BCI is set in 11, and the IC stage of the instruction D1 is executed, and the EX stage of the instruction BCI is executed. The instruction execution circuit 407 executes a conditional branch instruction BCI.
The branch condition specified by the instruction word is determined, and as a result, the branch success/failure signal on the signal line 149 indicates branch N0GO.
0". In response, the selection circuit 422 selects the address <At> which is the sum of the instruction address <BCI> of the instruction BCI output from the address generation circuit 432 and the instruction word length of the instruction BCI, Output on signal line 155.

Further, on the signal line 151, the address of the instruction BCI <B
CI> is output. flip flop 439,440
is the oC stage BH output in the previous machine cycle
Upon receiving the T update instruction signal and the OC stage GO prefetch instruction signal, both are set to "1". The EX stage prediction confirmation circuit 427 receives the V bit of the instruction BCI held in the branch information register (QR3) 419 via the signal line 146 in the previous machine cycle, the branch success/failure signal on the signal line 149, and the output of the flip-flops 439 and 440. Upon receiving the output, "1" is output to the EX stage prediction failure signal on the signal line 147 and the EX stage Bl (T update instruction signal) on the signal line 148, and the branch information of the instruction BCI is incorrect.
Although the prefetching of the subsequent instruction has already been instructed to the branch GO side, the instruction BCI is actually a branch N0GO, so the branch information regarding the BCI in the branch history table 410 is updated correctly, and the subsequent instruction is sent to the branch N0GO side. Indicates that it is necessary to redo the prefetch. In response, the instruction prefetch control circuit 423 sends signal line 1 to the input selector of the instruction address register 411.
51, and the input selector of the instruction address recovery register 428 is instructed to select the address <A1> on the signal line 155.

In the next machine cycle 6, the HU stage of instruction BCL is executed and branch information for instruction BCI is updated. The instruction address register 411 contains the instruction BCI.
The address <BCI> of the instruction BCI is set, and the address <A1> of the branch N0GO side of the instruction BCI is set in the instruction address recovery register 428 and register 434. or,
The flip-flop 441 is set to “1” by the EX stage BHT history innovative instruction signal output in the previous machine cycle.
is sent, and its output is provided to branch history table 410 via signal line 154. In response, the V bit of the branch information for the instruction BCI in the branch history table 410 is reset. Meanwhile, at this time, the instruction prefetch control circuit 423 instructs the input selector of the instruction address register 411 to select the output of the instruction address recovery register 428 that holds the address <AI> on the branch N0GO side of the instruction BCI. .

In machine cycle 7, instruction address register 4
Address <A1> is set to 11, and instruction A1 subsequent to instruction BCI is fetched.

Thereafter, the instruction prefetch operation continues according to the address set in the instruction address register 411.

〔Effect of the invention〕

Next, the effects of the present invention will be explained with reference to FIG. 20.

FIG. 20 shows a case where the subsequent instruction C1 is prefetched according to the branch information on the branch history table for the unconditional branch instruction B1, but the branch destination address specified by the branch information is incorrect. As soon as the branch destination address specified by the instruction is actually determined, a circuit is installed in the OC stage to check whether the branch destination address in the branch information is correct.
Instructed in the OC stage of instruction B1, machine cycle 5
At the point in time, the IC that takes out the correct subsequent instruction Di
stage is running. In this case, the number of lost cycles due to incorrect branch information is 4 machine cycles, but in the conventional technology to which the present invention is not applied, the IC stage of the correct subsequent instruction Di is executed based on the branch history for instruction Bl. H to update branch information on the table
It is machine cycle 7 after the U stage, and 6 machine cycles are lost.

As explained above, when executing a branch instruction with incorrect branch information for a branch destination address, the present invention makes it possible to correctly prefetch the subsequent instruction with fewer loss cycles compared to the conventional technology. effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
3 is a diagram showing the storage format of the storage units 501 and 502 in FIG. 2. FIG. 4 is a block diagram of an embodiment of the branch history table 410 in FIG. Block diagram: FIG. 5 is a diagram showing an example of the arrangement of instruction words in the instruction storage circuit 408 of FIG. 1; FIG. 6 is a block diagram of an embodiment of the priority circuit 507 of FIG. 2; 8 is a diagram showing the storage format of the branch information registers 417 to 420 in FIG. 1, and FIG. 9 is a diagram showing the storage format of the branch information register 413 in FIG. 1. FIG. 10 is a diagram for explaining the correspondence between instruction words in the circuit 408 and branch information in the branch history table 410. FIG. 10 is a diagram for explaining the instruction prefetching operation by the branch history table 410 in FIG. 9. FIG. is a block diagram of an embodiment of the OA stage prediction confirmation circuit 424 in FIG. 1, FIG. 12 is a block diagram of an embodiment of the OT stage prediction confirmation circuit 425 in FIG. 1, and FIG. 13 is a block diagram of an embodiment of the OT stage prediction confirmation circuit 425 in FIG. FIG. 14 is a block diagram of an embodiment of the confirmation circuit 426; FIG. 14 is a block diagram of an embodiment of the EX stage prediction confirmation circuit 427 in FIG. 1; FIG. 15 is a block diagram of an embodiment of the instruction prefetch control circuit 423 in FIG. , Figure 16 is a diagram showing an overview of the instruction processing flow, and Figure 17 shows a case where branch information corresponding to an instruction that is not a branch instruction is registered in the branch history table, and the instruction is prefetched according to the incorrect branch information. Figure 18 is a time chart for explaining the operation in the case where the corresponding branch information is not registered in the branch history table in the execution of an unconditional branch instruction or a BCT instruction that actually branches. Figure 19 is a time chart for explaining the operation when branch information corresponding to a BCT instruction that does not actually branch is registered in the branch history table and instructions are prefetched according to the branch information. The time chart in Figure 20 shows that branch information corresponding to an unconditional branch instruction or a conditional branch instruction that actually branches is registered in the branch history table, and when an instruction is prefetched according to the branch information, the branch A time chart for explaining the operation when the branch destination address indicated by the information is incorrect, and FIG. 21 show that branch information corresponding to a conditional branch instruction that does not actually branch is registered in the branch history table. , is a time chart for explaining an operation when an instruction is prefetched according to the branch information and the branch destination address indicated by the branch information is incorrect. 1 to 21, 401...Instruction address generation circuit 402...Instruction address conversion circuit 403...Instruction decoding circuit 404...Operand address generation circuit 405...
Operand address conversion circuit 406... Operand read circuit 407... Instruction execution circuit, 408... Instruction storage circuit 409... Instruction buffer 410... Branch history table (BHT) 411...
...Instruction address register 412...Instruction address addition circuit 413...Branch information buffer, 414...Instruction alignment circuit 415...Branch information switching circuit 416...Branch information register (QRO) 417...
・Branch information register (QRI) 418... Branch information register (QR2) 419... Branch information register (Q
R3) 420...Branch information register (QR4) 421
．． 422... Selection circuit, 423... Instruction prefetch control circuit 424... OA stage prediction confirmation circuit 425...
・OT stage prediction confirmation circuit 426...OC stage prediction confirmation circuit 427...EX stage prediction confirmation circuit 4
28...Instruction address recovery register 430.431
, 432...Address generation circuit 433...Comparison circuit, 434.435...Register 436.437.43
8,439,440,441...Flip-flop 5
01.502... Storage section 503.504, 505, 506... Test circuit 50
7... Priority circuit, 508... Selection circuit 5
09...OR circuit, 601, 602, 603.604
...AND circuit 605.606,607.608...
・OR circuit, 701...-number circuit 702...size comparison circuit, 703...AND circuit 1101.1102・
...Flip-flop 1103...Knot circuit, 11
04...AND circuit 1201.1202.1203.
1204...Flip-flop 1206, 1207.
...Truth circuit 1208, 1209.1210...AND circuit 121
1.1212.1213...OR circuit 1301, 13
02...Register, 1303...Flip-flop 1306...Comparison circuit, 1307...Truth/False circuit 13
08...AND circuit, 1309.1310...OR circuit 1401...flip-flop 1402, 1403.1404...truth circuit 1405
, 1406... NAND circuit 1407, 1408... AND circuit, 1409...
OR circuit 1501...Flip-flop 1502, 1503.1504.1505.1506.
1507...Truth circuit 1508.1509,1510
．． 1511, 1512.1513, 1514.1515
, 1516° 1517, 1518...AND circuit.

Claims (1)

[Scope of Claims] In an instruction prefetching device in an information processing device, branch history table means stores a plurality of pairs of information specifying an address of a branch instruction and branch information including a branch destination address of the branch instruction; a first checking means for checking whether information specifying an address of an instruction to be prefetched in the instruction prefetching operation is registered in the branch history table means when performing an instruction prefetching operation; a second checking means for checking whether the information specifying the branch destination address included in the corresponding branch information is correct before determining the branch condition of the prefetched instruction; and registration by the first checking means. control to read corresponding branch information from the branch history table means and continue the instruction prefetching operation according to the branch information in response to the result of the first and second checking means; and instruction prefetch control means for controlling a subsequent erroneous instruction prefetch operation to be corrected without waiting for execution of the prefetched instruction when an instruction prefetch operation is performed in accordance with branch information specifying a branch destination address. An instruction prefetching device characterized by: