JPS62158558U

JPS62158558U -

Info

Publication number: JPS62158558U
Application number: JP4385386U
Authority: JP
Priority date: 1986-03-27
Filing date: 1986-03-27
Publication date: 1987-10-08

Description

[Brief explanation of drawings]

第１図はこの考案の一実施例を示すブロツク図
、第２図はこの考案の他の実施例を示すブロツク
図、第３図は第２図のブロツクをさらに具体的に
示す回路図、第４図は第３図の回路の動作を説明
するのに示したタイミングチヤート、第５図はＶ
ＴＲのサーボ回路を示すブロツク図、第６図は第
５図のフイルタの構成を示す図、第７図は第６図
の加算器の例を示す図である。４３……加算器、４４……判定回路、４５……
レジスタ。 FIG. 1 is a block diagram showing one embodiment of this invention, FIG. 2 is a block diagram showing another embodiment of this invention, FIG. 3 is a circuit diagram showing the block of FIG. 2 in more detail, and FIG. Figure 4 is a timing chart shown to explain the operation of the circuit in Figure 3, and Figure 5 is a timing chart for explaining the operation of the circuit in Figure 3.
6 is a block diagram showing the servo circuit of the TR, FIG. 6 is a diagram showing the configuration of the filter shown in FIG. 5, and FIG. 7 is a diagram showing an example of the adder shown in FIG. 6. 43... Adder, 44... Judgment circuit, 45...
register.

Claims

[Scope of utility model registration request]

an adder to which first and second addition data are serially supplied; a sign bit of the first and second addition data is taken in from the input side of the adder; these contents and the calculation result of the adder; determining means for performing a logical determination with the output content of the means for taking in the sign bit of the adder to obtain a determination output of overflow or underflow of the adder; An adder auxiliary circuit comprising: setting means for setting predetermined values to respective registers that receive outputs from the adder.