JPS6215828B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece, and more particularly to a drive system for a pulse motor as an electromechanical conversion mechanism thereof. An object of the present invention is to reduce the power consumption of such a pulse motor. Another object of the present invention is to detect or anticipate and instantly correct malfunctions that may occur during low power consumption driving, and to control such that malfunctions or corrections are not detected in the external operation of the watch, such as the operation of the second hand. The goal is to provide a method.

Since the so-called quartz wristwatch, which uses a quartz oscillator as a time standard oscillator, was put into practical use, it has become widely popular due to its high precision and reliability. During that time, technological innovations in crystal wristwatches have been remarkable, and their power consumption, which initially required 20-plus microwatts, can now be achieved at around 5 microwatts. However, if we look at the breakdown of the current power consumption of 5 μW, it will be 1.5 to 2 μW due to the oscillation of the crystal oscillator, frequency division, etc.
W, 3 to 3.5 μW for a pulse motor, which is quite unbalanced. In other words, the power consumption of the electromechanical conversion mechanism accounts for 60 to 70% of the total power consumption, so we will continue to strive for further lower power consumption. Reducing the power consumption of this pulse motor is likely to be effective. However, the conversion efficiency of current pulse motors is quite high, and it is quite difficult to increase the efficiency further. However, conventional pulse motors have been designed to operate satisfactorily even under the worst conditions due to requirements such as an load-resistant mechanism such as a calendar mechanism, resistance to environments such as temperature and magnetism, and resistance to disturbances such as vibration and shock. For this reason, the motor was required to have the ability to withstand a constant load under certain driving conditions, but in reality, a watch body is under such load only for about 4 to 5 hours a day. Most of the time there is no load. In other words, if the watch body is always in an unloaded state, the motor mechanism does not need to be designed to withstand such a large load, and in that case, power consumption can be reduced considerably. Since the environment is harsh, it was necessary to use a pulse motor that can supply large amounts of power and obtain large outputs in order to guarantee this.

The present invention corrects the above-mentioned irrationality by driving the pulse motor with less power when the load is small, and with high power when the load is large, and greatly reduces the power consumed by the pulse motor. It is intended to reduce Moreover, this drive system is constructed using reliable all-electronic means without mechanical contacts, and achieves stable drive that can cope with variations due to motor type and mass production.

The present invention will be explained below.

Figure 1 shows an example of a pulse motor for an electronic wristwatch. In the figure, 1 is a permanent magnet rotor magnetized to two poles, and stators 2 and 3 are arranged facing each other with rotor 1 in between. However, these stators 2 and 3 are each connected to a yoke 5 around which a coil 4 is wound to form a set of stators. The stators 2 and 3 have circular arc portions 2a and 3a eccentric to the center of the rotor 1 so that the rotor 1 can rotate in a fixed direction, and the positions of the magnetic poles (N and S) when the rotor 1 is at rest are adjusted. The stators 2 and 3 are shifted to one side. This type of pulse motor has been in practical use for some time and was driven by a circuit block as shown in FIG. A crystal oscillator 10 is driven by an oscillation circuit 11, its frequency is divided by a frequency divider 12, and a waveform shaper 13 generates two pulses having an appropriate time width and a 180° phase difference at an appropriate time interval. is formed.

As an example, let's consider a pulse of 7.8 msec every 2" and explain this below.
Driver 1 consisting of CMOS inverter
4 and 15, and the output is sent to terminal 4 of coil 4.
a, 4b. FIG. 3 is a detailed diagram of this driver section. When a signal 18 is applied to the input terminal 16 of one inverter 14, a current flows as shown by an arrow 19, and conversely, the other inverter 15
When a similar signal is applied to the input terminal 17 of the arrow 1
Current flows in a route symmetrical to 9. That is, by alternately applying signals to the input terminals 16 and 17 of both inverters, the current flowing through the coil 4 can be alternately reversed, and specifically, the current flowing through the coil 4 of 7.8 msec is alternately reversed every second. can be passed to. With such a drive circuit, N and S poles are alternately generated in the stators 2 and 3 of the step motor shown in Figure 1, and the rotor 1 can be rotated 180 degrees by repulsion and attraction from the magnetic poles of the rotor 1. . The rotation of the rotor 1 is transmitted to the fourth wheel 7 via the intermediate wheel 6, and further transmitted to the third wheel 8, second wheel 9, and further to the cylinder pinion, hour wheel, and calendar mechanism (not shown), and the hour hand. , operates an indicating mechanism consisting of a minute hand, second hand, calendar, etc.

The pulse motor shown in FIG. 1 operates in principle as explained above, and has been used as a conversion mechanism for electronic wristwatches.

In the drive circuit shown in FIG. 3, when a high level signal is applied to the terminal 17 and a signal 18 is applied to the terminal 16, and a current flows as shown by an arrow 19, a voltage drop based on the drive current occurs in the MOS transistor 15 due to the channel impedance. A signal waveform corresponding to this current can be detected at the generating terminal 4b. The current waveform is as shown in FIG. 4, for example. Fourth
In the figure, section A is a drive section, in this case 7.8 msec, and the current flowing in this section A is the current consumed by motor drive. The reason why the current waveform in section A shows a complicated shape as shown in the figure is that in addition to the current generated based on the voltage applied by the drive circuit, there is also an induced current in the coil due to the rotation of the driven rotor. This is because they are superimposed. Section B is the section after the drive pulse is applied, and the rotor rotates due to inertia and vibrates until it stops at a stable position.At this time, in this section, the P-channel MOS transistors of the drive inverters 14 and 15 in FIG. Since it is turned on, an induced current flows to the coil 4 in response to the movement of the rotor in a loop between the coil 4 and this transistor. This is why the waveform in section B in FIG. 4 is pulsating. Therefore, the shape of this driving current waveform and the induced current waveform after driving can almost correspond to the rotational position of the rotor.

Now, waveform 20 and waveform 20' in FIG. 4 are a series of waveforms, and this is when the load on the rotor is very small. Waveform 22 and waveform 22' are also a series of waveforms, and in this case, the load on the rotor is large and the rotor is close to its operating limit, while waveform 21 and waveform 21' represent a load that is approximately 1/2 of the maximum allowable load. This is the case when it is multiplied. If you carefully observe the current waveform when the load is changed in this way, you will see that the waveform extends to the right as the load increases.
This is because the rotation of the rotor slows down as the load increases, and it has been experimentally confirmed that the rotor vibration frequency and amplitude become low until it stops at a stable position. Considering this phenomenon in reverse, it can be understood that if the load on the rotor is always in a no-load state, the rotor can be driven with a short pulse width of 7.8 msec. In fact, even if the pulse width is shortened, the motor still operates and the output torque decreases. This situation is shown in FIG. FIG. 5 shows the output torque characteristic T and the power consumption characteristic I when the drive pulse width is changed.
The aforementioned drive pulse width of 7.8 msec corresponds to _P2 in this figure. That is, the output torque is T ₂ with a pulse width of P ₂ and the power consumption is I ₂ . As mentioned above, this output torque T ₂ is set so as to be able to sufficiently withstand the load encountered by the watch body. However, if the load on the rotor is small or negligible, the output torque can be small and the drive pulse width can be shortened.
Therefore, power consumption can also be reduced. For example, if driven with a pulse width of P ₁ , the output torque is T ₁ and the power consumption is only I _1.The present invention focuses on this point, and by detecting the load on the rotor, When the load is small, it is driven with a narrow pulse width, and when a large load is applied, it is driven with a wide pulse width, which is a rational and low power attempt. As mentioned before, the overwhelming majority of people are in a no-load state, so the effect of reducing power consumption is very large. For example, as shown in Figure 5, when driving with a pulse width of P ₁ during no load (20 hours) and with a pulse width of P ₂ during load (4 hours), and assuming that I ₁ /I ₂ = 1/2. , the average power consumption is I=I ₁ ×20+I ₂ ×4/24=14/24I ₂ ≒0.
58I ₂ , which requires less than 60% of the power compared to the conventional method, which was driven with a constant pulse width of P ₂ , resulting in a significant reduction in power consumption.

By the way, although it was briefly mentioned above that "load is detected...", it goes without saying that this method of detecting load is a major point of the present invention. Next, a method for detecting this load will be described. Looking at the current waveform flowing through the coil in FIG. 4, it can be seen that the current waveform changes as the load increases. That is, in drive section A, the positions of maximum and minimum shift to the right as the load increases. The magnitude of the load can be determined by focusing on this point, but the amount of change in this waveform is extremely small, making it difficult to absorb variations in mass production and requiring extremely delicate control.

Therefore, the present invention focused on section B after application of the drive pulse. Also in this section B, as the load increases, for example, the point where the minimum value is first shifted to the right. Moreover, compared to the amount of change in the waveform in section A,
A change several times larger can be obtained. Therefore, it is easier to detect the magnitude of the load based on the induced current waveform in this section B than in the above-mentioned section A, and the reliability is also higher. This phenomenon is the same when the drive pulse width is shortened, and the situation is shown in Figure 6.The drive shown in Figure 6 has a narrower drive pulse width than the one in Figure 4, so it can withstand small loads. However, the drive current waveform 23 at no load, the induced current waveform 23' after driving, and the drive current waveform 2 at the operating limit load.
4 Similarly, the relationship with the induced current waveform 24' after driving is the same as that shown in FIG. The load is detected by the method described above, but the configuration of the present invention normally drives the motor with a narrow drive pulse assuming no load, and always detects the size of the load from the induced current waveform after driving.
When the load is small, driving continues with the initial narrow driving pulse width. When the load increases and approaches the limit of driving with a narrow driving pulse width,
From the next drive, drive is performed with a wide drive pulse width for a certain period of time, and then the drive is returned to the initial narrow drive pulse width. The present invention generally has such a configuration, but the seventh
This will be explained in more detail with reference to the block diagram in the figure.

FIG. 7 is a block diagram showing the configuration of the present invention, where 25 is a time standard oscillator, 26 is a circuit including an oscillation circuit, a frequency dividing circuit, etc., 27 is a pulse motor drive circuit, and 28 is a pulse motor. The configuration is the same as a conventional electronic wristwatch. 29 is a load detection circuit that detects the load based on the induced current waveform after application of the drive pulse as explained in FIGS. 4 and 6.
0 is a control circuit that controls the drive of the pulse motor 28 according to the load condition detected by the load detection circuit 29, and normally controls to supply a narrow drive pulse when there is no load and a wide drive pulse when there is a load. . This control system will be explained with reference to FIG. 8th
The figure shows the state of the driving pulses, and the states supplied as described above in the section of the pulse motor are shown as pulses 31 and 32. pulse 3
1 and 32 are narrow pulse widths in the no-load state. After applying the pulses 31 and 32, the detection circuit of FIG. 7 detects a load condition, which is either no load or a small load condition. That is, since the load detection after pulse 31 was determined to be no load, the next pulse 32 has a narrow pulse width, and since the load detection after pulse 32 was also determined to be no load, the next pulse 33 also has a narrow pulse width. In load detection after pulse 33, it was determined that the vehicle was in a loaded state. In this case, several tens of milliseconds after the pulse 33, a second drive pulse 34 with a wide pulse width is applied with the same polarity as the pulse 33 (that is, the same current direction). For the subsequent constant number of pulses, wide pulse width pulses 35, 36 are applied, and then the initial narrow pulse width pulses 37, 38, . . . are applied again. To explain the relationship between the pulse 33 and the pulse 34, when a large load is detected by driving the pulse 33, the pulse 34 with a wide pulse width is applied after several tens of milliseconds. This is because the load is determined to be large when the load is detected after pulse 33, but it is difficult to determine whether the rotor has operated at this time, because the induced current waveform in Figure 6 shifts to the right as the load increases. Attenuate. When the rotor does not operate, no induced current is produced, but it is difficult to distinguish this from the situation in which the rotor operates smoothly when the load is close to its limit. If the load increases gradually, even if the load is determined to be large, the rotor will still be operating at the pulse 33 at that time, and if the load suddenly becomes too large to be driven by a narrow pulse width, the rotor will not operate at the pulse 33. It doesn't work. It is difficult to distinguish between the two.
Therefore, it is easy to set the load detection after pulse application so that there is some margin. In this configuration,
Apply pulse 34. When the rotor is actuated by pulse 33, pulse 34 is a pulse in the same direction as pulse 33, so this pulse 34 becomes a pulse with an opposite phase, and the rotor does not rotate. Also, if the rotor does not operate with pulse 33, it will be driven with pulse 34. At this time, the rotor will be driven with a delay of several tens of milliseconds, but this will not be recognized by the eye as an operation of the second hand. There is no need to worry about unsightliness caused by this. Next, after detecting the load, the wide pulse width pulse 35,3
The reason for configuring 6 to continue for a constant number of pulses is as follows.
The largest load on the rotor is the calendar mechanism, which lasts for 3 to 4 hours, so if you immediately return to a narrow pulse width, it will be judged as being loaded again, and if you repeat this, two pulses will be generated for each operation. power consumption increases,
Low power consumption becomes meaningless. In addition, the load on the rotor is not only due to the calendar mechanism, but also single loads such as magnetic fields, low temperatures, and disturbances. In such a case, it is desirable that the number of continuous pulses with a wide pulse width be as small as possible. In consideration of such a phenomenon, it is desirable to set the number of continuous pulses to several tens of seconds to several tens of minutes. The configuration of the present invention has been described above. Next, specific embodiments of the present invention will be described. Figure 9 shows
1 is an example of a load detection circuit and a drive pulse control circuit of a timepiece according to the present invention. In FIG. 9, 25 is an oscillation circuit, 26 is a frequency dividing circuit, 28 is a motor, and 2
7 is a drive circuit, 29 is a motor load detection circuit, 3
0 is a control circuit, each corresponding to a block in FIG. Hereinafter, the circuit elements will be explained one by one. The NAND GATE output of 39 is a clock for creating a narrow pulse when driving the motor in a no-load state, and for example, generates a clock pulse that is delayed by 5 msec with respect to the falling edge of a 1 second signal. At this time, the delay flip-flop 42 delays the input one-second signal by 5 msec and outputs it, and a narrow pulse with a width of 5 msec is generated at the output of the gate 46. The flip-flop 44 is a delay flip-flop with a 128 HZ clock input, and its output is delayed by 7.8 msec with respect to the input 1 second signal. Therefore, a pulse with a width of 7.8 msec is obtained at the output of the gate 47, and this is used as a wide pulse for driving when a load is applied. gate 40
42, 44 and 44 are clocks for generating pulses for determining the no-load state and the loaded state for the time until the minimum portion of the current waveform generated by the rotor operation appears immediately after the application of the drive pulse; A similar operation yields judgment reference pulses at the outputs 43 and 48.

10 corresponds to the output narrow pulse of the gate 46, and 59 corresponds to the criterion pulse of the gate 48 output. The gate 41 is a gate for forming a correction pulse, and the pulse width is a wide pulse of 7.8 msec, and the generation position is delayed by, for example, 30 msec with respect to the pulse of the gate 46 or 47. An example is shown in FIG. 1066. Input terminal 57 of gate 41
is a correction signal to be described later, and the correction signal is
Only when it becomes HIGH, a correction pulse is generated at the output of 41 and supplied to the subsequent stage. Gate 39, 40, 4
The input signal No. 1 is a signal for obtaining the pulse,
The outputs of the counters 26 are combined appropriately. The gates 89 and 49 pass the pulses to the driving inverter 1.
This is a circuit that separates signals 4 and 15 and outputs them alternately every second. The gate 50 inputs one count input to the counter 52 when a correction pulse is issued to the output terminal 41 while the counter 52 is at zero. Once the counter 52 starts counting, the gate 50 remains in the OFF state until all outputs of the counter 52 return to zero. gate 5
When 52 enters a counting state by the output of 0, the gate of 51 opens and continues to send a 2 second signal to 52 as a count signal until all outputs of 52 become zero. The counter 52 has the number 10 as described above.
It is set appropriately between seconds and several tens of minutes, and serves as a timer that continues to output a wide pulse drive signal for the above-mentioned time period after detecting that the motor is in a loaded state. 47 is the output of the counter 52,
It is used as a gate input, and outputs a wide pulse to the subsequent stage while 52 is in the counting state. Block 29 in FIG. 9 is an example of a circuit that detects the motor load from the operating state of the motor after application of the drive pulse. Reference numerals 53 and 54 are transmission gates that alternately select the outputs of the drive inverters 14 and 15 in accordance with the motion signal.

The outputs of 53 and 54 are combined and input to a differential amplifier 55 via a capacitor. Of the output signals 53 and 54, waveforms in a no-load state and a waveform in a loaded state are shown in FIGS. 60 and 61, respectively. The differentiating circuit operates as a peak detector in this case, and the signal obtained by passing the differentiating circuit output through two further inverters becomes a rectangular wave that is inverted at each peak, 62 for 60, 64 for 61, etc. I get a signal.

The output of the inverter is delayed by the CR time constant circuit and becomes one input of the NAND gate 56, and by using the intermediate output of the two inverters as the other input of the NAND gate 56, the signals 63 and 65 in FIG. get. Signal 63 is output waveform 60
, and the signal 56 corresponds to the output waveform 61. Comparing the output waveforms 60, 61 with the signals 63, 65, it is clear that the pulses of the signals 62, 63 indicate predetermined peak positions of the output waveforms. The load state is detected by determining whether the pulse positions of the signals 63 and 65 are inside or outside the above-mentioned determination reference pulse 59, and the former case is determined to be a no-load state, and the latter case is determined to be a loaded state. judge. Therefore, signal 63 indicates a no-load condition, and signal 65 indicates a loaded condition. Note that the output signals 63 and 65 of the NAND gate output pulses in the negative direction.

Next, the correction pulse generating means will be described. The gate 104 outputs a load detection signal which is the output of the gate 56, a judgment reference pulse signal 59 which is the output of the gate 48, and a signal obtained by delaying the 1 second signal which is the output of the delay flip-flop 44 by 7 to 8 _msec . is taken as input. The output signal of the delay flip-flop 44 serves as a mask signal for determining the detectable period at the gate 104. With the above configuration, the detection signal when there is no load (Fig. 10, 6
3) passes through the gate 104, but the detection signal 65 when there is no load is prohibited. Line 57 is the output of the flip-flop formed by gates 107 and 108, and the set input is formed by gates 106 and 105. The 1 second signal input to the gate 106 determines the desired set state of the flip-flop, and the output 57 is always set to H in the load detection state. When a signal detecting a no-load state passes through gate 104 in this state, it passes through gates 105 and 106, resets the flip-flop, and sets output 57 to the L state.
However, when the load is heavy, the reset signal is not input, so the output 57 remains set to H. If the output 57 remains high, the gate 41 that generates the correction pulse will be in a state where it will generate a correction pulse, so the correction pulse will be supplied to the coil through the gate 89 or 49 for the drive circuit. Nao gate 10
The other input of the counter 52 receives a signal that prohibits passage of the detection signal at the same time the counter 52 starts operating. Note that the correction pulse is set to have a pulse width larger than the normal drive pulse by the gate 41, and a pulse having the same polarity as the drive pulse for which the heavy load state was detected is supplied. That is, NAND gate 90
and 91 and NAND gates 92 and 93, a 2-second signal is applied as a gate signal, and in particular, since NAND gates 90 and 91 are connected through an inverter 94, a 2-second signal of opposite polarity to that of NAND gates 92 and 93 is applied. has been done.

As a result, the normal drive pulse that has passed through the OR gate 95 is connected to the NAND gate 90 and the NAND gate 9.
2 alternately every second and is supplied to the drive circuit. Further, when a heavy load condition is detected from the induced current generated in the coil after application of the drive pulse, the correction pulse 66 is outputted with a delay of several tens of milliseconds from the drive pulse, as described above.

The correction pulse is input to NAND gates 91 and 93, but since NAND gates 91 and 93 share the gate signals of gates 90 and 92, respectively, the correction pulse is a pulse with the same polarity as the drive pulse and is input to the drive circuit. Supplied. As a result, for the case of waveform 61, a correction pulse 66 is subsequently applied, which completes the rotation of the rotor. However, as described above, this also includes the case where the rotation of the rotor is completed before 66 is applied.
The correction pulse 66 is also input to the counter 52 via the gate 50, turning on the gate 51 and putting the counter 52 in the counting state. Thereafter, the gate 47 is kept in the ON state for a certain period of time to continue supplying the wide pulse drive signal. While a wide pulse is being applied,
Since the output of inverter 112 is input to gate 105, gate 57 is in the LOW state and no correction pulse is output. This is because the motor is considered to have sufficient output torque during wide pulse driving. Further, the detection operation for the correction pulse is prohibited by sending the judgment reference pulse signal 59 to the gate 104.
This is done by inputting (Fig. 10). That is, after the determination reference pulse 5 falls, the gate 104 serves as a prohibition circuit that prohibits passage of all detection signals. Therefore, load detection is prohibited for any of the correction pulses for correcting the drive pulse with the 7.8 _msec pulse width, which has a larger effective value, as described above, and unnecessary power consumption can be reduced.

As described above, in this embodiment, the drive pulse generation circuit in the normal light load state is 9 in FIG.
A circuit for generating a drive pulse having a pulse width of 5 msec is surrounded by a frame 110 and is formed by a delay flip-flop 42, a gate 39, a gate 46, and an inverter 96.
128Hz for a drive pulse with an 8msec pulse width
It is formed by a delay flip-flop 44 having a clock signal of 1, a gate 47 and an inverter 96. The load detection circuit 29 shown in FIG. 9 is used as the load detection circuit, and the correction pulse generation circuit is surrounded by a frame 98 in FIG.
and a gate 91 that supplies the output of the gate 41 to the drive circuit as a correction pulse having the same polarity as the drive pulse.
93.

As the peak detection circuit, various systems can be considered in addition to the 55 differential amplifier circuit. Figure 18 shows
This is a block diagram of a peak detection circuit using a delay circuit. In the figure, 53 and 54 are transmission gates, and 8
0 is a general amplifier replacing 55 in FIG. 9, 81 is a delay circuit, and 82 is a comparator to which the outputs of 80 and 81 are input. An example of the amplifier 80 is shown in FIG. 13 or 14. Since the motor drive detection waveforms 23, 24, etc. mentioned above are signals of several mV to several tens of mV that are substantially generated near the power supply level, the resistor 6
The voltage is divided by 6 and 67 and converted to the input operating level of the amplifier. A waveform shown in FIG. 16 76 appears at the terminal 68. FIG. 14 is an improved circuit of FIG. 13, in which a MOS transistor is inserted in place of the resistor 67, and it has a return circuit that controls the channel impedance of the transistor 69 so that the amplifier input level becomes the operating level. , block 7
0 is a circuit that detects the output level. FIG. 15 shows a simple embodiment of the delay circuit 81, in which 71,
73 is a transmission gate, and 72 and 74 are load capacitors. In this case, the input signal 76 at terminal 68 is delayed as 77 at the output terminal. FIG. 17 schematically represents this waveform, and the input signal 76 is connected to the transmission gate 7.
1, it is transmitted to the capacitor 72 and the terminal voltage waveform of 72 becomes 79. Furthermore, a waveform 77 appears at the output terminal 75 by the transmission gate 73. Comparator 82 outputs a rectangular signal shown at 78 when waveforms 76 and 77 are input.

As the delay circuit, the one shown in FIG. 15 is suitable, but since the input signal frequency is relatively low, a bucket brigade type data transfer element or the like is also suitable.

It has been confirmed that the load detection method of the present invention operates effectively even against magnetic fields or shocks applied to the watch body. FIG. 19 shows a detected current waveform when a DC magnetic field is applied in the direction of the coil of the pulse motor. 83 is a case where the directions of the magnetic field induced in the motor inner core by an external magnetic field and the driving magnetic field are opposite to each other, and 84 is a case where both magnetic fields are in the same direction.
At 83 and 84, waveforms 85 and 86 have zero external magnetic field, and can be considered to be substantially the same waveforms. 87,8
8 is a waveform when the external magnetic field is 40 Gauss. According to the waveform, the operation in the direction 83 becomes more difficult as the external magnetic field becomes stronger, and exhibits the same characteristics as the operation when the load becomes large. Therefore, the timepiece circuit according to the present invention exhibits effective operation even under the influence of external magnetic fields, and it has been experimentally confirmed that the strength against external magnetic fields is no different from that of conventional timepieces. 19th
In the case of FIG. 87, since the minimum position of the waveform appears after the determination reference pulse, a correction signal indicated by 87' is added. From the above explanation, it can be easily inferred that the present invention has an effective effect on impact resistance as well.

Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the embodiments described here, and various improvements, changes, and applications are possible. For example, the pulse motor is not limited to the pulse motor described here. A conversion mechanism other than a motor may be used, and even a pulse motor shown in FIG. 11 among pulse motors can be used with exactly the same configuration. The pulse motor in Fig. 11 has rotor 1
00 is made of a permanent magnet, and the stator 101 is of a one-piece type without a gap, unlike in FIG. 1, and has notches 10 for determining the static position of the rotor.
2,103 are formed. 104 is a drive coil. In such a pulse motor, since the stator 101 is connected, the induced current after driving is slightly different from that in FIGS. 4 and 6, as shown in FIG. 12. However, the waveform 105,1 at no load
05', and the waveforms 106 and 106' under load are basically the same and can be realized using the same method.

As described above, according to the present invention, the rotor load condition is detected by the induced current generated in the coil of the pulse motor, and when a heavy load condition is detected by the load detection circuit, a correction pulse having an effective value larger than the drive pulse is continuously applied. In addition to having a configuration in which the correction pulse is output, a means for prohibiting load detection is provided for the correction pulse, thereby preventing malfunction and reducing wasteful power consumption.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a pulse motor of an electronic wristwatch according to the present invention. FIGS. 2 and 3 are diagrams showing conventional circuit configurations, and FIG. 4 is a diagram showing a current waveform of a pulse motor drive coil in a conventional timepiece. Fifth
The figure is a diagram showing the relationship between output torque and power consumption with respect to the drive pulse width of the pulse motor. FIG. 6 is a coil current waveform diagram when the motor is driven with a pulse width narrower than the conventional drive pulse. FIG. 7 is a diagram showing a circuit block of a timepiece according to the present invention.
FIG. 8 is an example of a time chart of motor drive pulses by the circuit according to the present invention. FIG. 9 is a diagram showing a specific example of the block circuit of FIG. 8. FIG. 10 is an example of a time chart of the load detection section in FIG. 9. FIG. 11 is a diagram showing an example of a pulse motor of an electronic wristwatch according to the present invention. FIG. 12 is a coil current waveform diagram during narrow pulse driving in the pulse motor of FIG. 11. FIGS. 13 to 18 are diagrams showing other examples of the load detection section in FIG. 9. FIG. 19 is a diagram showing changes in the coil current waveform when a DC magnetic field is applied to the electronic wristwatch according to the present invention. 25... Oscillator circuit, 26... Frequency dividing circuit, 27... Drive circuit, 28... Motor, 29... Load detection circuit, 3
0...Control circuit, 31-33...Narrow pulse drive signal,
34... Correction signal, 35... Wide pulse drive signal, 59
... Load determination reference pulse, 60... No-load detection signal, 61... Load detection signal, 98... Correction pulse generation circuit, 99... Drive pulse generation circuit.

Claims (1)

[Claims] 1 an oscillation circuit 25, a frequency division circuit 26 that frequency divides the output signal of the oscillation circuit, a drive circuit 27 that outputs a drive pulse based on the output signal of the frequency division circuit,
a pulse motor 2 driven by the drive circuit;
8, a load detection circuit 29 detects an induced current generated in the coil of the pulse motor after application of a drive pulse; and an output of the load detection circuit connected between the frequency dividing circuit and the drive circuit. a control circuit 30 that is controlled by a signal, and the control circuit includes a circuit 99 that generates the drive pulse based on the output signal of the frequency dividing circuit.
and a circuit 98 for outputting a correction pulse having an effective value larger than the drive pulse, based on the heavy load detection signal of the load detection circuit and the output signal of the frequency dividing circuit, following the drive pulse, and the detection circuit An electronic timepiece characterized in that it includes an inhibition circuit 104 that inhibits a load detection operation for the correction pulse based on the output signal of the frequency dividing circuit.