JPS62156753A - multiprocessor system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Summary] A main processor, at least one sub-processor, a communication bus and a system control bus connecting these, and each of these processors and the bus has an O
The system is duplicated into system 1 and system 1, and the processors and buses of system O always send and receive data only within system 0, and the processors and buses of system 1 always send and receive data only within system 1. be restrained by Here, the system sends a system switching instruction from the main processor to both systems (1, O) of each sub-processor, instructing that systems should be switched (O→11→O).
and means for notifying these subprocessors that the system switching instruction has been sent, thereby smoothly switching between the O system and the 1 system.

[Industrial application field]

The present invention relates to a multiprocessor system, and particularly to a multiprocessor system suitable for use in an electronic exchange.

For example, an electronic switching system is roughly divided into a network section that actually performs line switching or packet switching, and a processor section that manages this network section and controls call processing. The present invention particularly refers to the latter processor section.

Basically, one processor is sufficient for this processor section, but as the scale of the electronic exchange system increases, the network section is also expanded, and a plurality of processors are accordingly introduced. Further, the plurality of processors are divided into several processors and a main processor that comprehensively manages these sub-processors to construct one multiprocessor system. Furthermore, to improve the reliability of this multiprocessor system, it is called duplexing.

Methods will also be introduced. In other words, each component (processor, bus) is duplicated into an O system (active system) and a 1 system (protection system), and one bank ups the other.

The above system configuration method is based on the so-called one-machine concept, and can be extremely flexible from a single processor to multiple processors, and even to a duplex configuration. This is an extremely efficient method for dealing with expansion. Therefore, it is thought that such multiprocessor systems will be widely used in the future.

[Conventional technology]

In an electronic switching system, a duplex multiprocessor system as described above has one management processor (the main processor described above) and multiple call processors (the subprocessors described above, which perform call processing. ), and each processor is duplicated. In this case, switching between the 0-system and 1-system processors is one of the important operations. Conventionally, as this system switching operation,
A method is adopted in which each call processor is given the right to switch systems. In other words, any call processor can select between the 0 system and the I system.

[Problem that the invention seeks to solve]

According to the system switching method for the duplex multiprocessor system described above, regarding the control procedure between each call processor and the management processor, software must be managed each time each call processor exercises the system switching right. In the end, there is a problem that software management becomes complicated.

[Means for solving problems]

FIG. 1 is a diagram showing the principle configuration of a multiprocessor system according to the present invention. In this figure, 11-0 is an O-system main processor, 11-1 is an I-system main processor, and each has a plurality of 0-system sub-processors 12-01 to 12-Ok and a plurality of 1-system sub-processors 12-11 to 12-Ok. - Overall management of IK. Between these processors, there are communication buses 13-0, mainly 0-series and I-series, for exchanging data.
, 13-1 (for simplicity, the 1-system communication bus 13-1 is not shown, but is wired in parallel with the O-system communication bus 13-0).

Additionally, between these processors, there are system control buses 14-0 and 1 for mainly transmitting control signals.
4-1 (For simplicity, 0 system control bus 14-O
Although not shown, the 1st system control bus 14-1
(are wired in parallel with this) are wired. Here,
All processors in the 0 system and all buses in the θ system exchange data and control signals only within the 0 system, and
All processors in the system and all buses in the I system are constrained to exchange data and control signals only within the I system, which is an important prerequisite for the present invention.

In other words, communication only takes place between the same systems. By restricting communication between the same systems, the amount of hardware is considerably reduced and software management becomes considerably easier. Another important precondition is that the secondary processor is not given any system switching rights, and the main processor α
By restricting only υ to exercise the system switching right, the conventional problem can be solved more effectively.

However, in order to satisfy the above two prerequisites, the following two means are specifically required, and these means are important components of the present invention.

The first means is a system switching instruction sending section, which is indicated by reference numbers 15-0 and 15-1 in FIG. The second means is a system switching notification section, reference number 16-0 in the figure.
, 16-1. System switching instruction units 15-0 and 15-1 for system 0 and system 1 are main processors 11-0 and 11.
-1, and have the function of sending a system switching instruction from the main processor (0 system, 1 system) to each sub-processor. Signals for the switching instruction are transferred via system control buses 14-0 and 14-1 connected to the main processor. On the other hand, the system switching notification units 16-0 and 16-1 are also located in each main processor 1i-o and 11-1, and the system switching instructions have already been sent from the system switching instruction units 15-0 and 15-1. This is notified to each sub-processor (2).

[For production]

Assuming that the O system is now the active system, suppose that the main processor 1 〇 performs system switching due to some cause (for example, a failure). As a result, the 1-system main processor 11-1 operates as the active system (therefore, from the above preconditions, the 1-system sub-processors 12-11 to 12-
1 and the 1-system buses 13-1 and 14-1 become the active system). At this time, the system switching instruction unit 15-
0 is the corresponding 0 system sub-processor 12-01 to 12-Ok
Sends a system switching instruction signal to the system switching instruction section 15.
-1 is the corresponding 1-system sub-processor 12-II to 12-1
A system switching instruction signal is sent to k. Here, it is displayed that each O-system processor (12-01-12-Ok) should become a backup system, while each 1-system processor (12-01-12-Ok)
12-11 to 12-1k), it is displayed that the self should become the active system. These displays are performed in the O-system switching instruction sending units -01 to 17-Ok and the 1-system switching display units 17-1l-17-1k in FIG. However, it is not necessary to newly provide these display sections, and the existing flag register or status register may be used.

In this way, although a system switching instruction is issued from the main processor side to the sub processor side, each sub processor cannot immediately detect that its own state has been switched. If this happens, the active system and standby system on the main processor side and the active system and standby system on the sub processor side will be reversed, resulting in a serious system error.

The reason why a switching instruction cannot be detected immediately is that, in general, each subprocessor does not check the system switching display section αη, which is made up of the above-mentioned flag or status register, while it is online. The only time I go to check it is when the power is turned on or when the IPL (Initial Program
oad) is a special envoy.

Therefore, the system switching notification unit 16-0 on the main processor side.

16-1 to O-system and 1-system subprocessors 12, respectively.
-01 to 12-Ok and 12-1l to 12-1k are notified without delay that system switching has occurred, and each processor is prompted to look at its own switching display section α.

Here, the active system and standby system on the main processor side match the active system and standby system on the sub processor side.

〔Example〕

FIG. 2A is a diagram showing an example of the system configuration on the sub-processor side to which the present invention is applied, and FIG. 2B is a diagram showing an example of the system configuration on the main processor side to which the present invention is applied. The components are CC and C in Figure 2A.
8C, and in the blocks CG, MSC, and ISO in FIG. 2B (described in detail later). Note that since the following explanation will be made using an electronic exchange as an example, the above-mentioned main processor is specifically a management processor, and the above-mentioned sub-processor is specifically a call processor.

In this figure, the former is MPR (Management P
The latter is shown as CP R (Cal rocessor).
lProcessor). In FIG. 2A, call processors CPR, ~CPRk each connect to a corresponding network (Network NW!). ~N- is controlled. Each network has a built-in exchange function unit such as a communication route memory and sets a bus route. The reason why there are multiple networks NW, to NWk in this way is based on the concept of so-called load distribution.

For this reason, a plurality of call processors CPR, -CPRk are provided for each network.

Additionally, each network (N
W) is duplicated and consists of a pair of 0 system (#0) and 1 system (#l) - correspondingly, each call processor (CPR)
It also consists of a pair of 0 series (#0) and 1 series (#1). 0
The call processors (C'PR) of the system are connected to the communication bus 13.
MPRo
The call processors of the 0 system (CPR, 0 to CPR, .) can also communicate with each other via the communication bus 13-0 if necessary. Similarly, the 1-system call processors (CPR) group that has become the active system communicate with the 1-system management processor MPR via the communication bus 13-1, and the 1-system call processors communicate with each other as necessary. (CPR□
~CPR□) can also communicate via the communication bus 3-1.

Although inter-system (#Oe#1) communication is performed in each processor CPR, it is assumed that inter-system communication is not performed between other CPRs. This is to simplify hardware and software management.

Next, the internal structure of each call processor CPR will be explained.

Since both call processors have the same structure, CP
This will be explained using R as a representative. call processor CPR,
The 0 and 1 systems of CC, l5C1esc, ip
Consisting of c and MM. The names of each part are as follows.

■ CC (Central Controller)
・"Central control unit ■ ISC (Interface)
Subsystem Controller)...
Inter-system communication control device ■ CS C (Call processor 5id
e System reco-configuration
Controller) - System reconfiguration control device ■ IPC (Inter multi Pr
(Communi-Cator)
...Multiprocessor communication control device ■ MM (Ma
in Memory) = main memory device■ P B S
(Processor Bus) =Processor bus Among the above ■-■, ■, ■, and ■ are common, but ■, ■, and ■ are unique to multiprocessor systems. First, looking at the inter-system communication pavement ZRSC, this device performs inter-system communication between the O system and the 1 system, and in preparation for system switchover, it always reserves particularly important data among the latest information of the active system. The backup system is supplied to the system so that when system switching occurs, the standby system can be started up quickly.

The system reconfiguration control device C8C is located on the call processor side (also located on the management processor side), and in a multiprocessor system, when a system reconfiguration is not possible using normal communication routes, when a failure occurs, when the power is turned on, etc. Control information for controlling reconfiguration is transferred to system control bus 0.
It is a device for transferring via minutes.

The inter-multiprocessor communication control device IPC can communicate from CPR to MPR, from MPR to CPR, or from the same system C
This is a control device for performing data communication operations between PRs on the communication bus a3. That is, data communication for normal call processing is performed via this device IPC.

Next, referring to FIG. 2B, the management processor MP
The internal structure of R will be explained. However, blocks similar to those described in FIG. 2A will not be described again.

In addition, buses 13-0゜13-1 and 14-0 in Figure 2B
and 14-1 are buses 13-0 and 13- in FIG. 2A.
1, 14-0 and 14-1.

The blocks specific to FIG. 2B are as follows.

■ Management processes
sor 5ide Systemreconfigur
ation Controller) - System reconfiguration control device■ IBC (Inter multi process)
ssors Bus Control-roller)...
Communication bus control device■ PBC (Periphera)
l Bus Controller) - Peripheral Bus Control Device The system reconfiguration control device MSC described above is placed on the management processor side, and its role is the same as that of the C8C on the call processor side.

The above communication bus control device IBC controls the right to use the communication bus α (to) by the multiprocessor communication control device IPC, and performs, for example, polling. Further, the peripheral bus control device PBC controls the input/output control device 10C, and plays the role of an adapter for an external storage device (floppy disk, etc.) under the control of the IOC. Note that the block connected to the management processor MPR by a dotted line is a debug console (Con-sole) D-CN S, which is used only during software debugging.

Thus, the multiple call processors of FIG. 2A, CP
R and the management processor MPR of FIG. 2B control a plurality of networks NW, .about.NWk. In such a system, the present invention refers to how to perform system switching. For example, when there is a failure in system 0 (#0), which is the active system, the system is switched to the standby system according to a predetermined procedure. Control will be passed to system 1 (#1).

FIG. 3 is a diagram schematically showing a system switching method according to the present invention. In this diagram, communication buses 13-0 and 13-1
The upper side is the 0 system and the lower side is the 1 system, indicating that the two systems are separated. fPC is already in 2nd A
2B is the multiprocessor communication control device explained in FIG.
Rk 110 is connected to communication bus 13-O. This configuration is exactly the same for the I system (#1) as shown in the figure. The CPU in this diagram is simply shown in Figures 2A and 2B.
In the figure, MPR and CPR excluding IPC (CC
1ISC, MM, etc.), and is only summarized in order to simplify the diagram. The CPUs of the 0 system are connected to each other by a system control bus 14-O, and the CPUs of the 1 system
The U units are also connected by the system control bus 14-1,
As each system control bus, system switching instruction signal lines SS (SS-0, 5S-1) and system switching notification signal lines 5T (ST-0, 5T-1), which are particularly relevant to the present invention, are shown. .

As a precondition of the present invention, the management processor MPR takes the initiative in instructing system switching. For this purpose, a system switching instruction signal 4%SS is first wired to each call processor CPI? , ~CPRk are uniformly given system switching instructions. In this case, the system switching instruction is issued not only to the system that is the source of the system switching instruction, but also to the other system at the same time. Communication between such systems takes place through line L1. Here, a new system display will be made in each CPRO system switching display section (the block labeled 17 in FIG. 1). In other words, up until now, the l-based (0-based) objects were O-based (1
A message indicating that the system has been switched to (system) is displayed.

Subsequently, a system switching notification signal is sent from the management processor MPR side to each call processor CPR side. For this purpose, a system switching notification signal line ST is wired. Each C here
PR is instructed to look at the corresponding system switching display section Qη. Based on this instruction, each CPR operates as a new system. In this case, the switching notification is sent not only to the system after the system switching instruction but also to the other system at the same time.In the case of the system switching instruction described above, communication between systems is carried out through line L2. It is similar to

FIG. 4A shows a specific example of the system switching instruction unit according to the present invention.
It is a figure shown about the side. Further, FIG. 4B is a diagram showing an example of a system switching display unit on the CPR side that cooperates with the system switching instruction unit according to the present invention, and each of the configurations in FIGS. 4A and 4B is an O system system switching diagram. It is connected by the instruction signal 41ss-o and the 1st system 5S-1. In FIG. 4A, the left side of the center is the O system (#0), and the right side is the 1 system (#1). That is, management processors MPR-0 and MPR-
1 are arranged on the left and right, each comprising central control units CC-0 and CC-1, and an intersystem communication control unit rsc-o.
and l5C-1, system reconfiguration controller MSC-0
and MSC-1 are shown. System switching instruction unit (15-0, 15-1 in FIG. 1), which is one of the features of the present invention
is 1 in the intersystem communication control device rsc-o and l5C-L.
5-0 and 15-1, cross-wiring 1 is provided to form a type of latch circuit. This line Ll is equivalent to the line L1 shown in FIG. By this crossing, it can be guaranteed that if one is O-based, the other is always I-based. Output logic that indicates what should be the 0 series and 1 series, for example “
0゛ and “1” are the corresponding driver DRV-
0 and DRV-1 (or DRV-1 and DRV
-Q), system switching instruction signal lines 5S-O and 5S
-1 (or 5S-1 and 5S-Q). Signal lines 5S-O and 5S-1 are among system control buses 14-0 and 14-1, respectively, and these buses 14-O and 14-1 are connected to MPR-0 by connectors CN-0 and CN-1. and MPR-1.

The system switching instruction units 15-0 and 15-1 are driven because the active management processor MPR detects some kind of failure.

Assuming that the active system is MPR-0, an example of how the system switching instruction unit 15-0 is driven will be described below.

Note that the same process applies to the MPR-1 side of the 1 system, so only the O system will be explained. Further, the system switching instruction section 15-1 is automatically driven by the other system switching instruction section 15-O via the line Ll. According to this example, first the fault detection timer FDT
(Fault Detection Timer) -
0 overflows. Generally, the timer FDT is managed by software and programmed so that its count value is cleared at regular intervals. That is, unless an abnormality such as software runaway occurs, timer FDT is cleared and therefore does not overflow. If an overflow occurs, it means that some abnormality has occurred, so the overflow information is set in a predetermined bit EA in the emergency register RGI-0 via gates G1-0 and G2-0. This change in bit EA causes the emergent timing circuit f! The O system switching instruction section 15-0 is driven via MAYIM, and from this the thread switching instruction signal S5
sl) is output. The signal ssso is sent to the system switching instruction signal line 5S-0 as described above, and at the same time, the state of the system switching instruction section 15-1 of the 1st system is inverted. Also, a predetermined bit A/S in the white meat (0 series) mode register RG2-0 is switched to S. A of the A/S bit means an active system (Act), and 3 means a standby system (Stand by). Therefore, mode register RG2 in system 1
The -1 A/S bit is switched from S to A. Note that the A/S distinction is simply expressed as a logical "1" or "0" distinction. (Then, the management processor MPR
From -0, each call processor CPI of the θ system? ,~C
A switching instruction is issued to PRk. Furthermore, switching progresses simultaneously within the MPR-1 of the 1st system based on the switching information obtained from the line L1, and each call processor CPR, ~C of the 1st system
PR.

A switching instruction is also issued to . It should be noted that there are many types of failure factors, not limited to the above example, and other factors are also notified to each other by the cross-crossing line L'l. HMASUP in the figure is for prevention of emergency activation (Eo
+ergency Action 5uppress) signal. In addition, the factors P S E (Ea+ergency
5supervisor-Equip+++ent (emergency failure monitoring device) is set to a predetermined bit in the above-mentioned emergency register RGI via the 0-system and 1-system one-shot circuits 5HT-0 and 5)IT-1. However, the above ESE, EMASUPSF
Since DT and the like are not essential to the present invention, they will not be described in detail.

System switching instruction signal SSS from the above system switching instruction units 15-0 and 15-1. , 5ssl are supplied to each call processor side, and will be explained next with reference to FIG. 4B. In FIG. 4B, CPR,-0 and CPR,-
1 is the call processor (CP) of the 0 system and the l system, respectively.
R, ), and the same applies to CPRk. CPR
, -0 include the central controller CC, -O and the system reconfiguration controller esc, -o. other CPR,-1,
The same applies to CPRk-0 and CPR,l-1. Devices of the same type are connected in a cascading manner through connectors (CN) (TR in the figure is a terminating resistor). There is an existing mode register in each central control unit (CC), and a predetermined bit A/S in the register is set to -0, On 17-
1)). A/S (8ct/5tand by
) is as described in FIG. 4A. In the above example, the 0 system was operating as the active system, so the A/S bits of the 0 system and 1 system switching display sections are, for example, "0" and "1", respectively. When the management processor MPR-0 detects a failure,
The system switching instruction signal S is generated by the procedure described in FIG. 4A. . and S. 1 as logic “l” and “0” respectively,
It is incorporated into the 0-system call processor group and the 1-system call processor group, and switches the logic of the A/S bit. However, with this alone, each call processor cannot switch itself to the other system (active-protection system, protection-active system). This is because each call processor does not look at the mode register when it is online.

Therefore, the system switching notification units 16-0 and 16-1 described above are activated next. This will be explained below.

FIG. 5A is a diagram showing an example of a management processor equipped with a system switching notification section according to the present invention. Also, 5th B
The figure is a diagram showing an example of a group of call processors activated by the system switching notification unit of FIG.
Each configuration in the diagram is an O-system system control bus 14-0 and 1.
The system control bus 14-1 of the 0-system and 1-system system switching notification signal line 5T is connected to the 0-system and 1-system system control bus 14-1.
-0.

5T-1, ST'-0 and ST'-1 are important.

However, ST'-0 and ST'-1 are synchronous signal transmission lines, respectively. Note that the line L2 in FIG. 3 corresponds to the interconnection line L2 in FIG. 58.

In this figure, system switching notification units 16-0 and 1 according to the present invention
6-1 is located in the system reconfiguration control devices MSC-0 and MSC-1 on the management processor MPR side, and specifically, an emergency action designation register (Emergency ActionDesignation register).
Signation Register? ) EADR-
0 and EADR-1 as OEM bits. When this 8M bit is set to 1, it indicates that an abnormality has occurred. Writing to the 8M bit is done by software processing. S ss+),
It is sent onto the system switching notification signal line 5T-0 via the driver gate DG. At this time, the EM bit "1" is also supplied to the other system (system 1) via line L2, so
At the same time, the first system also receives notification of the occurrence of system switching through the system switching notification signal line ST-1.

Actually, the system switching notification signal (8M bits) is Ss.

It is necessary to send not only (SS□) but also a clock signal for synchronization. This clock signal is sent out as a synchronization signal CLO, and the system reconfiguration control device CSC,-0,C3C,-1 to C3Ck- receives the system switching notification signal Ssao (S5ty) on the call processor side.
0, C3Ck-1 synchronization is established. Note that if the system (2) is the active system, the synchronization signal CLI is used.

Both are generated by synchronization signal generation circuits CLG-0 and CLG-1, and synchronization signal transmission lines ST'-0 and ST'
-1 and reaches the call processor CPR side.

On the call processor CPR side of FIG. 5B, each system reconfiguration controller CSC, ~O, CSC, -1 ~csck
-o.

At C5C*4, the thread switching notification signal Ssa is output. (S s
r,) as well as a synchronization signal CLO (CLI).

If system 1 had been the active system until now, S, A, CL1 in the parentheses would be received by C8C of both systems. These signals are then preferably routed to an existing RSF flag register (RSF) within each central controller (CC).
A predetermined bit MEM (M
anage+went processor Emer
gency) is set to “1” at a predetermined timing. This timing is defined by the previous synchronization signal CLO.

It is very effective to notify each CPR of the system switching through the reset foot flag register (RSFR) in this way. This is because the restart flag is a flag that instructs the highest priority interrupt, so the software in each call processor (CPR) immediately goes to check a predetermined bit, and at this point the system switchover shown in Figure 4B occurs. The process for switching to the other system is started by looking at the display section 0n, that is, the A/S bit, and the active system is switched to the backup system, and the backup system is switched to the active system. Here, everything in the O system can be switched to the standby system, and everything in the 1 system can be switched to the active system.

Finally, I will list some examples of operations related to the present invention.

■ Power-on IPL (Initial Pro
gram Load): PI (2 ■ MPR failure: PH1 ■ rPc failure in MPR during IPL: PH2, ■ IP
IPC failure in CPR at L time: PH2 ESE emergency: PH1 The meanings of the above symbols are as described above except for PHI and PH2. PH means phase, and is usually divided into 0, 1.2, and the higher the number, the higher the degree of failure.

In other words, PH2 is the highest level and has the highest priority.

The electronic exchange cannot maintain the exchange process itself under the startup mode of PH2. In PH1, the connection suddenly changes even if you are online, but those who are talking are saved, and those who are dialing are disconnected. PHO switching is a start-up mode that is almost unnoticeable to the caller because it is relieved even during a call and during dialing.

FIG. 6 is a system transition diagram during power-on IPL.

The order of transition is (1) → (2) → (3) → (4) from the top. Each transition diagram is drawn in accordance with the system configuration shown in FIG. Furthermore, among the lines connecting MPR and CPR, no particular action occurs between the dotted lines, and actions occur only between the solid lines.

The above also applies to FIGS. 7 to 10 below. The solid line (1) in this figure is the PI (2 activation message), and the PH2 activation message is sent from the MPR to all CPRs. The solid line (2) in the figure is the PH2 activation message response, and the MPR receives the PH2 activation message response from all CPRs, the CPR becomes lPLL.
, performs restart processing.

In the same figure (3), ■ indicates inter-system data communication, ■ indicates exchange processing (data communication), and ■ indicates the SBY (standby) system from the ACT (active) system of MPR and all CPRs.
The MM copy operation begins. ■In parallel with this copy operation, the system enters exchange processing (online processing) in parallel mode.

FIG. 7 is a system transition diagram when an MPR failure occurs.

In (1) of the figure, ■ indicates exchange processing, and ■ indicates intersystem data communication. The multiprocessor system is in normal operation (
(online), the A/S (ACT/5BY) bit is rewritten by the emergency circuit.

In the same figure (2), ■ is the MPR side emergency (
MEMA), ■ indicates a PH1 startup message, and ■ indicates that a failure has occurred in the MPR.
At the same time, in ■, PH1 is sent from MPR to all CPRs.
Send startup message 7. The solid line in the same figure (3) is the PH
1 activation message response, MPR is higher than all CPR,
By receiving the PH1 activation message response, the system PH1 performs restart processing. In the same figure (4),
In (2), the CPR reads the failed hopper of the old ACT system at the end of the PH1 restart process, and when nothing is written, performs the copy operation described above. In ■, MPR reads the CC switching flag of the old ACT system at the end of PH1 restart processing,
When nothing is written, it goes down by itself. Note that ■ indicates exchange processing (data communication).

FIG. 8 is a system transition diagram in case of IPC failure in MPR during IPL. In (1) of this figure, from MPR,
Sends PH2 activation message to all CPRs. In addition, E
MC is an emergence counter that counts the number of occurrences of emergencies.

In (2) of the same figure, in (2), the MPR emergency circuit is activated because the PH2 activation message response is not returned from each CPR. ■The system PH
1 (MPR), but since the program has not been loaded, the software goes out of control and the FDT overflows again. In (3) of the same figure, ■ indicates the MPR side emergence, and M at the time of IPL.
The MPR notifies all CPRs of the IPc failure within the PR, and in (2) the MPR sends a PH2 activation message to all CPRs. In (4) of the same figure, in ■, each C
When the PH2 activation message response is not returned from the PR, the MPR emergency circuit is activated. ■
indicates an emergency on the MPR side, and the MPR notifies all CPRs of an IPC failure within the MPR, and also sends a PH2 activation message from the MPR to all CPRs. (2) Thereafter, a process similar to that at the time of power-on IPL shown in FIG. 6 is performed.

FIG. 9 is a system transition diagram in case of IPC failure in CPR during IPL. The solid line (1) in the figure is a PH2 activation message, and the PH2 activation message is sent from the MPR to all CPRs. In (2) of the same figure, in (2), the MPR receives a PH2 activation message response from each CPR. In (2), the emergency circuit is activated (FDT is overflowed) due to the CPR being unable to receive data. ■MPR tries to run system PH1, but
Since the program is not loaded, the software goes out of control and the FDT overflows. In (3) of the same figure, ■ indicates the MPR side emergency, and the MPR notifies all CPRs of an IPC failure in the CPR during IPL, and ■ MPR sends a PH2 activation message to all CPRs. do. In (4) of the same figure, in (2), the MPR emergency circuit is activated because the PH2 activation message is not received from the CPR. ■
indicates MPR side emergence, CPR during IPL
Notify internal IPC failure from MPR to all CPRs,
- Send a PH2 activation message from the MPR to all CPRs. ■After that, power-on IPL shown in Figure 6
Do the same process as when.

FIG. 10 is a system transition diagram during ESE emergency. In (1) of this figure, ■ indicates CPR.

This indicates that an ESE emergency (EMA) has occurred. ■The MPR's emergency circuit starts up,
The ESE bit of the MPR's emergency register RG turns on and a restart occurs. Simultaneously with the occurrence of this lift, A/S switching occurs and an ESE emergency (EMA) occurs. Therefore, the EES bits of both systems are turned on. In (2) of the same figure, ■ indicates the MPR side emergency, and the MPR notifies all CPRs of the occurrence of ESE emergency in the CPR, and ■
The MPR sends a PH1 activation message to all CPRs. The solid line (3) in the figure is a PH1 activation message response, and the MPR receives PH1 activation message responses from all CPRs. The solid line (4) in the figure is a PH1 execution message with an individual down request.First, the ESE bit of register RG of MPR is checked to recognize the occurrence of ESE EMA. Next, a PH1 execution message with an individual down request is sent to all CPRs. After that, MPR and all CPR go down individually.

〔Effect of the invention〕

As detailed above, according to the present invention, in a multiprocessor system in which each processor is duplicated, software management is extremely simplified, and the system can be changed from system 0 to system 1 without introducing complicated hardware. This reverse system switching can be performed, and the effect will be even greater if used in an electronic exchange.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle configuration of a multiprocessor system according to the present invention, FIG. 2A is a diagram showing an example of the system configuration on the sub-processor side to which the present invention is applied, and FIG. 2B is a diagram showing the main system configuration to which the present invention is applied. FIG. 3 is a diagram schematically showing a system switching method according to the present invention; FIG. 4A is an MPR diagram showing a specific example of a system switching instruction section according to the present invention.
FIG. 4B is a diagram showing the CPR side that is linked to the system switching instruction unit according to the present invention.
FIG. 5A is a diagram showing an example of a management processor equipped with a system switching notification unit according to the present invention, and FIG. Figure 6 is a system transition diagram at power-on IPL, Figure 7 is a system transition diagram at MPR failure, and Figure 8 is M at IPL.
FIG. 9 is a system transition diagram in case of IPC failure in PR. FIG. 9 is a system transition diagram in case of IPC failure in CPR during IPL. FIG. 10 is a system transition diagram in case of ESE emergency. 11-0, 11-1...main processor, 12-Of
〜12-Ok, 12-1〜12-1k...subprocessor, 13-0, 13-1...communication bus, 14-0
, 14-1... system control bus, 15-0, 1
5-1... System switching instruction section, 16-0, 16-1...
・System switching notification unit, 17-01 to 17-Ok, 17-1
1 to 17-1k...System switching display section, CPRa to CPR
k... Call processor, MPR... Management processor, 5S-0, 5S-1... System switching instruction signal line, 5T-0, 5T-1... System switching notification signal line, L
L, L2...Line for system interconnection.

Claims (1)

[Claims] 1. A plurality of sub-processors, a main processor that controls these sub-processors, and a communication bus and a system control bus respectively wired for communication and control between the sub-processors and the main processor. and each of the above is 0
A multiprocessor that is duplexed into a system and a system 1, and in which, during normal operation, the 0 system is restricted to perform communication and control only within the 0 system, and the 1 system is restricted to perform communication and control only within the 1 system. The system comprises: a system switching instruction unit that instructs each of the sub-processors to perform system switching between the active system and the standby system between the 0 system and the 1 system; A system switching notifying unit is provided in each of the main processors to notify each of the sub-processors of the change, and each sub-processor is provided with a system switching notifying unit that receives system switching instruction information from the system switching instructing unit and transmits the system switching instruction information. A system switching display section is provided to display a system switching display section, and each of the sub-processors receives a notification from the system switching notification section to indicate that it will perform system switching according to the information displayed on its own system switching display section. Features a multiprocessor system.