JPS62151817A - Automatic focus detecting device - Google Patents

Abstract

PURPOSE:To obtain excellent distance measurement accuracy by putting an operational amplifier in operation for a certain time before the start of integration and adjusting the offset of an integration circuit automatically. CONSTITUTION:The resistance 30a, capacitor 30b, and differential amplifier 30c of the integration circuit constitute a general Miller integration circuit and generates a large output by utilizing the amplifying operation of the amplifier 30c. The output of an operational amplifier 29c is applied to the input terminal of an operational amplifier 29c, a reference source voltage V0 is connected to the other input terminal of the operational amplifier 29c, and the output signal of a light receiving element and the output signal of the operational amplifier 29c are connected to the input terminal of the operational amplifier 29e, so that the operational amplifier 29c operates for the certain time right before the start of integration. Consequently, the offset of the integration circuit is adjusted automatically and excellent distance measurement accuracy is obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is used in photographic devices such as video cameras and still cameras, and in particular projects a spot light such as infrared light onto a subject and uses the reflected light. The present invention relates to a so-called active type automatic focus detection device that receives light using a pair of light receiving elements and obtains a focus detection signal.

[Prior Art] A conventional example in which focus adjustment is performed based on the difference in output from a pair of light receiving elements in such an active automatic focus adjustment method will first be described with reference to FIGS. 4 and 5.

In FIG. 4, spot light is projected onto a subject S from a light emitting element 2 pulse-driven by a pulse oscillator 1, and the reflected light reflected by the subject S passes through a condenser lens 3 to a pair of light receiving elements 4a, 4b. incident on . In this case, the light receiving elements 4a and 4b are movable as shown by the arrows along with the movement of a photographic lens (not shown). Light receiving element 4
The respective outputs from a and 4b are sent to synchronous detection circuits 6a and 6 synchronized with the pulse oscillator 1 via amplifiers 5a and 5b, respectively.
b removes unnecessary external light components, and the next stage integrator 7a
, 7b.

The outputs Sa and Sb of the integrators 7a and 7b (7) are the fifth
As shown in Figure (a), it gradually increases as time t passes. In this case, as shown in the figure, if Sa<Sb and the light intensity of the spot light incident on the light receiving element 4b is extremely larger than that of the spot light incident on the light receiving element 4a, the out-of-focus state occurs. be.

Furthermore, in the focused state, there is almost no difference between the outputs Sa and Sb, and the output becomes Sa-sb. The outputs Sa and Sb from the a dividers 7a and 7b are further input to an adder 8 that adds both, and a subtracter 9 that calculates the difference between the absolute values of both image powers Sa and Sb. The outputs of the comparators 9 are input to comparators 10.11 having predetermined threshold values Vl and V2 (Vl>V2), respectively, and these comparators 10.1
The outputs of 1 are connected to the arithmetic processing circuit 12, respectively.

FIG. 5(b) shows the output of the adder 8, and the outputs S, a
+Sb gradually increases with time t, and at time t1 when it reaches the threshold value Vl, the comparator 10 outputs an H level. (C) is the output of the g calculator 9, and the output l Sa −
Sb l gradually increases with time t, and at time t2 when it reaches the threshold value v2, the comparator 11 outputs an H level.

These H level outputs are used in the arithmetic processing circuit 12 to determine which time is inputted earlier or how much earlier it is inputted.

For example, if time t2 (7) at which 1sa-9bl=V2 is input earlier than time TI, then 5a=Sb
When the relationship is broken, that is, the state is out of focus. Also, before l 5a-Sbl = V2, Sa +
If the time tl at which Sb=Vl is earlier, Sa
The state is close to the output Sb, and it can be determined that the state is close to the in-focus state.

Here, a detailed circuit diagram of the synchronous detection circuit 6 and integrator 7 used in the block circuit diagram of FIG. 4 will be further explained with reference to FIG. 6. The DC component of the output of the amplifier 13a is cut through the capacitor L3b, and the output is connected to the analog switch 13c.
added to. Analog switches 13c and 13d are alternately opened and closed by synchronizing signal 5YNC. A reference voltage vO is applied to the input of the analog switch 13d, and when there is an input shown in FIG. 7(a), the potential at one end of the resistor 13e has the waveform shown in FIG. 7(b). The current flowing through the resistor 13e is proportional to the potential difference between the potential shown in FIG. 7(b) and vO. However, this is the case when an ideal operational amplifier 13f is used, and in reality, the operational amplifier 13f
An offset voltage exists between the positive input terminal and the negative input terminal of. At the input of the Miller integration circuit consisting of a resistor 13e, an operational amplifier 13f, and a capacitor 13g,
Since this offset voltage is always superimposed, even if the input to the integrating circuit is zero, a non-zero potential difference will occur in the integration result. Therefore, a voltage deviated from Va by an offset amount is applied to the positive input terminal of the operational amplifier 13f by a variable resistor 13h, and is manually adjusted so that the integration result for zero input becomes zero. However, even with this adjustment, the amount of offset changes due to changes in temperature, etc., and this has the drawback of making distance measurement accuracy unstable.

[Object of the Invention] An object of the present invention is to provide an automatic focus detection device that eliminates the above-mentioned drawbacks, automatically adjusts the offset of the integrating circuit, and obtains good Jllll distance accuracy.

[Summary of the Invention] The gist of the present invention for achieving the above-mentioned object is to provide a light projecting means for projecting a spot light toward a subject, a pair of light receiving means for receiving reflected light of the spot light from the subject. , a detection device having an integrating means for respectively integrating output signals of the pair of light receiving means and performing focus detection based on the output signals of the pair of integrating means, the integrating means comprising a first operational amplifier and a resistor. A Miller integrating circuit consisting of a capacitor is used, the output of the first operational amplifier is applied to the input terminal of a second operational amplifier, a reference power supply is connected to the other input terminal of the second operational amplifier, and the output of the first operational amplifier is connected to the other input terminal of the second operational amplifier. An output signal of the light receiving means and an output signal of the second operational amplifier are connected to an input terminal of the amplifier, and the second operational amplifier operates for a certain period of time immediately before the start of integration. It is a device.

[Embodiments of the Invention] The present invention will be described in detail based on embodiments illustrated in FIGS. 1 to 3.

In FIG. 1, 21 is a photoelectric detector, which is composed of two divided light receiving elements 21a and 21b, and has the necessary sensitivity to the emission wavelength of the infrared light emitting diode 22. The photocurrents obtained by the light receiving elements 21a and 21b are the first and second photocurrents, respectively.
It is added to the second signal processing circuit 23,24. Since the signal processing circuits 23 and 24 are exactly the same circuit, only the first signal processing circuit 23 is shown in FIG.
4 is represented by a dotted line. The output of the light receiving element 21a is input to the sensor amplifier 25, which converts the photocurrent from the light receiving element 21a into voltage. The position of this sensor amplifier 25 is easily affected by noise, so it is desirable to place it as close to the photoelectric detector 21 as possible.In addition, the light input to the photoelectric detector 21 should be such that the desired infrared signal component is Many other unnecessary external light components are also included, so in order to prevent the output of the sensor amplifier 25 from being saturated by these components, bypass frequency characteristics are provided, and circuits that remove photocurrent due to external light components are devised. is being done as necessary. A DC component of the voltage output from the sensor amplifier 25 is converted by a capacitor 26 and added to a preamplifier 27. The preamplifier 27 has a gain that is switched to three levels, for example, 1, 8, and 64, ensuring a sufficient dynamic range for the input signal. The DC component of the output of the preamplifier 27 is again filtered out by the capacitor 28 and is applied to the synchronous detection circuit 29. A pulse signal 5YNC synchronized with the light emission pulse from the light emitting diode 22 is applied to this synchronous detection circuit 29, and the potential difference between the non-emission state and the light emission state is output to the next-stage integration circuit 30. The integration circuit 30 integrates the detected output voltage and sends it to the capacitor 31. N
JM. The integration circuit 30 includes an automatic offset adjustment circuit 3.
The input offset voltage of the differential amplifier used in the integrating circuit 30 is recorded on the capacitor 33, and functions to provide a zero integral output for zero input. Note that the above description of the second signal processing circuit 24 is also omitted since it is completely the same.

The outputs Va and Vb of the two integration circuits 30 of the first and second signal processing circuits 23 and 24 are given to an adder 40, and an average value (Va-Vb)/2 of the outputs Va and Vbc7 is obtained.

The average value (Va+Vb)/2 is comparator L/-E 41.42
and the charging circuit 43. On the other hand, the constant voltage V is applied to the positive input terminals of the comparators 41 and 42.
L and VH are applied, and these voltages VL, V
H becomes a threshold voltage for determining whether integration is complete. Integral outputs Va and Vb are applied to the minus input terminal and plus input terminal of the comparator 44, respectively, and the magnitude relationship of the outputs Va and Vb is compared. A step signal ST from the logic circuit 45 is also applied to the charging circuit 43 to which the average value (Va+Vb)/2 is input, and the voltage is added stepwise to the input voltage (Va+Vb)/2, and this voltage is input to the negative voltage of the comparator 46. given to the input end. On the other hand, the comparator 46 has two positive input terminals, each with an integral output Va, V
b has been added. This comparator 46 makes it possible to compare the output Va or Ifvb with the (Va+Vb)/2-step voltage, and depending on the number of steps and the timing of inversion of the comparator 46, the integrated output Va at a predetermined time,
The potential difference of Vb can be measured.

The logic circuit 45 includes four comparators 41, 42, 44.
．． A signal from the charging circuit 43.46 is input from the logic circuit 45 to the charging circuit 43. Integrating circuit 30. It outputs signals to the synchronous detection circuit 29, infrared light drive circuit 47, and motor drive circuit 48. Further, the logic circuit 45 has five digital signal input/output lines.

It is connected to a microcomputer 49. The infrared light drive circuit 47 drives the light emitting diode 22, and the motor drive circuit 48 drives the motor 50 that moves the photographic lens.

When this automatic focus detection device is used in, for example, a video camera, since the distance to the subject changes from moment to moment, it is necessary to constantly perform focus detection and continuously adjust the photographing lens to the in-focus state. For this purpose, focus detection is performed using IDLE, I
Transitions between four modes: NTEG, HOLD, and CLEAR are performed while repeating them in sequence.

Clock pulse signal C from microcomputer 49
LK, mode signal MO[]E, and gain signal GAIN are sent to a logic circuit 45, which generates signals IREII, CLR, and a gain switching signal by combining these signals. The signal CLK is used to generate an infrared light drive signal IRED and a step signal ST to the synchronous signal 5YNC1 charging circuit 43. Also, the signal MODE
As mentioned above, four mode IDs are used during one ranging period.
Performs a transition from LE to INTEG-, HOLD-CLEAR. The signal GAIN switches the gain of the preamplifier 27, sets the maximum gain when the signal processing circuits 23 and 24 are reset, and decreases the gain of the preamplifier 27 each time a pulse of the signal GAIH is applied.
Flip-flops FLL and FHH in the logic circuit 45
The output is input to the microcomputer 49 via signal lines LL and HH.

FIG. 2 shows each control signal of the configuration diagram shown in FIG. 1. First, when the signals CLK and MODE go to H level, the signal processing circuits 23 and 24 are reset and the IDL
It becomes E mode. In this IDLE mode, both the synchronous detection circuit 29 and the integration circuit 30 have no output. The infrared light drive circuit 47 operates according to the signal IRED synchronized with the pulse of the signal CLK. While this mode continues for the necessary time, the automatic offset adjustment circuit 32 of the integrating circuit 30 performs automatic offset adjustment and stabilizes the output of infrared light.

In the synchronous detection circuit 6 and integrator 7 in the conventional neck wear shown in FIG. 4, noise components of external light are output as they are, and an adjustment element is required to remove the offset. This drawback has been improved by configuring a synchronous detection circuit 29, an integration circuit 30, and an automatic offset adjustment circuit 32 as shown in FIG.

That is, the synchronous detection circuit 29 is constituted by 29a to 29f, the resistors 29a and 29b are equal, and can be regarded as a 1-times inverting amplifier. When the signal 5YNC is at L level, the switch 29d is turned on, and the output of the transconductance operational amplifier 29c is applied to the positive input terminal of the differential amplifier 29e, and when it is at H level, it is turned off, that is, the positive input terminal of the differential amplifier 29e becomes high impedance. Become. Signal I RED
When is not emitting light, the signal 5YNC is at L level, the output of the differential amplifier 29e is Vo, and the potential of the capacitor 29f is intermediate between the input voltage at that time and vO. Furthermore, when the signal RED emits light, the signal 5YNC is at H level, and the output of the operational amplifier 29c is cut by the switch 29d, so the output of the differential amplifier 29e is
This is the inverted value of the input voltage at that time centered around the hold voltage of 9f. As a result, only a signal synchronized with the signal 5YNC is outputted from the differential amplifier 29e in proportion to its amplitude.

On the other hand, the integrating circuit 30 is composed of 30a to 30c. Resistor 30a, capacitor 30b, differential amplifier 3
0c is a general Miller integration circuit, and a differential amplifier 30
A large output can be obtained by using the amplification effect of c. Note that the capacitor 30b corresponds to the capacitor 31 shown in Figure 51. 32a and 32b are automatic offset adjustment circuits 32, and the switch 32a is connected to a signal CLR which becomes H level only in INTEG and HOLD modes.
The output of the transconductance amplifier 32b is applied to the positive input terminal of the differential amplifier 30c, and the switch 32a is turned off by the L level signal CLR, and the positive input terminal of the differential amplifier 30c becomes high impedance. become. By setting the signal CLR to H level for a certain period of time immediately before the start of integration, that is, in the IDLE mode, the output of the differential amplifier 30c becomes Vo, and the offset voltage of the differential amplifier 30c is accumulated in the capacitor 33. When the signal CLR becomes L level, the output of the operational amplifier 32b is cut off, and the integrating circuit 30 functions as a general Miller integrating circuit. Since the offset voltage is held in the capacitor 33, the offset voltage of the differential amplifier 30c is canceled out, and the integration result becomes zero for zero input.

Next, when the pulse of the signal MODE is output, the mode changes to I.
Transition to NTEG. In this mode, the integrating circuit 30 starts integrating from zero and receives the infrared light drive signal rRE.

The synchronous detection circuit 29 performs synchronous detection of the light-receiving signal from the light-receiving element 21a using the signal 5YNC synchronized with the signal 5YNC. The integrating circuit 30 integrates when there is an input from the synchronous detection circuit 29 synchronized with the signal 5YNC, and the integral outputs Va and vb fall at a falling rate proportional to the signal strength.

The average value (Va+Vb)/2 of the integrated outputs of the first and second signal processing circuits 23.24, which are the outputs from the adder 40, is
Two thresholds VL and VH are compared in the 7 parators 41 and 42, respectively, and when (Va+Vb)/2 reaches these thresholds VL and VH, the following changes occur. That is, flip-flops FLL and FHH in the logic circuit 45 are set to H level by reset, but are set to L level by the outputs of comparators 41 and 42 when (Va+Vb)/2 crosses thresholds VL and VH, respectively. Change.

The output of flip-flop FHH is always output 1! ;jHH
Furthermore, the flip-flop FLL outputs to the output line LL only in the INTEG mode. By checking the digital signals from these flip-flops FHH and FLL, the microcomputer 49 can check the integral amount with the two S1 values VL and VH. Threshold V
H determines the end of the integral operation, that is, the INTEG mode, and when the flip-flop FLL changes to L level, the infrared light drive and synchronous detection operations are forcibly stopped. In addition, the flip-flop F) IH is (Va+Vb)
When /2 reaches the threshold vH, it automatically changes to L level when transitioning to HOLD mode.

Subsequently, the MODE pulse causes the mode to transition to HOLD. In this mode, the integration circuit 30 continues to be able to perform integration, but the synchronous detection circuit 29 and the infrared light drive circuit 47
becomes inactive. During this period, the signal processing circuit 2
3.24 integral outputs Va and Vb hold each voltage value,
The difference between one of the outputs and the average value (Va+Vb)/2 is detected, and the signal CLK changes in frequency and contributes to the generation of the step signal ST in this mode. In the previous mode, INTEG mode, the output of the charging circuit 43 is equal to the output of the adder 40 as it is, the integral output Va, Vbc7) average value (va+vb)/2, but in the HOLD mode, it is output according to the signal CLK. It is charged by a step signal ST having a constant period and having a constant amount of electric power, and falls at a constant speed, as shown by the signal Vc. Then, it eventually crosses the lower level of the voltage of either the integral output Va or Vb, and at this time, the flip-flop FHH returns to the H level again. Since this change is output to the output line HH, the potential difference between the integral outputs Va and Vb can be determined by measuring the time interval during which the flip-flop FHH was at the L level. The focus state can be determined from the potential difference between the integral outputs Va and Vb, and the smaller the potential difference, the closer to focus. Moreover, the charging circuit 43 in this case
Charging at can also be considered discharging depending on the choice of sign.

Furthermore, the mode changes to CLEAR by the MODE pulse. In this mode, as in the IDLE mode, both the synchronous detection circuit 29 and the integration circuit 30 are initialized with no output, and no infrared light drive is performed. The magnitude relationship between the integral outputs Va and vb is latched until the mode transits to the HOLD mode again, and the motor 50 is driven via the motor drive circuit 48 to move the photographic lens closer to the focusing direction. Note that this focusing direction can be obtained by the positive or negative sign of the output of the comparator 44.

[Effects of the Invention] As explained above, the automatic focus detection device according to the present invention has the following effects:
The configuration of the synchronous detection circuit and integration circuit effectively removes external light components, and the offset compensation of the integration circuit, which conventionally required manual adjustment, is automatically performed.
This has the advantage of improving distance measurement accuracy.

[Brief explanation of drawings]

1 to 2 show an embodiment of an automatic focus detection device according to the present invention, in which FIG. 1 is a block circuit diagram thereof, FIG. 2 is a signal waveform diagram, and FIG. 3 is a synchronous detection circuit, integral circuit,
4 is a circuit diagram of an automatic offset adjustment circuit; FIG. 4 is a block circuit diagram of a conventional signal processing circuit; FIG.
) to (c) are diagrams explaining its operation, Figure 6 is a circuit diagram of its synchronous detection circuit and integrator, Figure 7 (a) is an input waveform diagram of the synchronous detection circuit, and (b) is an output waveform diagram. be. Reference numeral 21 is a photoelectric detector, 21a and 21b are light receiving elements, 2
2 is an infrared light emitting diode, 23.24 is a signal processing circuit,
25 is a sensor amplifier, 27 is a preamplifier, 29 is a synchronous detection circuit, 30 is an integration circuit, 31.33 is a capacitor, 3
2 is an automatic offset adjustment circuit, 40 is an adder, 41.4
2.44.46 is a comparator, 43 is a charging circuit, 45
47 is a logic circuit, 47 is an infrared light drive circuit, 48 is a motor drive circuit, 49 is a microcomputer, and 50 is a motor. Patent applicant Canon Corporation Figure 3 Figure 4 Figure 5 (G) (b) Figure 6 Figure 7 (G) (b)

Claims (1)

[Claims] 1. Light projecting means for projecting a spot light toward the subject;
A detection device comprising a pair of light receiving means for receiving reflected light of a spot light from a subject, and an integrating means for integrating output signals of the pair of light receiving means, and performing focus detection based on output signals of the pair of integrating means. In the device, the integrating means is a Miller integrating circuit consisting of a first operational amplifier, a resistor, and a capacitor, and the output of the first operational amplifier is applied to the input terminal of a second operational amplifier, and the second operational amplifier A reference power source is connected to the other input terminal, an output signal of the light receiving means and an output signal of the second operational amplifier are connected to the input terminal of the first operational amplifier, and the second operational amplifier An automatic focus detection device characterized by operating for a certain period of time immediately before the start of integration.