JPS6214855B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention provides a first-in method capable of correctly reading data even when writing to a plurality of arithmetic units is performed intermittently.
The present invention relates to a data processing device that can be selectively combined with a first-out storage device (hereinafter referred to as FiFO memory).

Here, the FiFO memory is defined as a storage device that can read information in order from the first written information, that is, the oldest information.

[Background of the invention]

Prior art related to high-speed data processing devices that operate multiple arithmetic units at the same time includes:
For example, as disclosed in US Pat. No. 4,128,880, there is a method of selectively coupling computing units using a vector register as an intermediary.

In this method, called chaining, a certain arithmetic unit outputs valid data continuously without interruption.
It is assumed that other arithmetic units also input valid data continuously without interruption. However, it does not operate correctly when data is transferred intermittently, such as when reading data from a storage device. That is, there is a risk that data that has not yet been written may be read by mistake.

[Purpose of the invention]

An object of the present invention is to selectively combine a plurality of arithmetic units and operate them simultaneously, so that even if data is intermittently output from the arithmetic units, correct data can be input to subsequent arithmetic units as valid data. The purpose of the present invention is to provide a processing device.

[Summary of the invention]

In order to achieve such an object, the present invention includes a plurality of storage means each holding a group of data and capable of performing read and write operations in parallel, and a plurality of storage means capable of performing operations on sequentially input data. a plurality of arithmetic means for performing respective calculations and outputting data corresponding to the arithmetic results in parallel with reception of new input data; the plurality of storage means and the plurality of calculation means so as to sequentially supply the data to the selected calculation means and sequentially supply the group of data output from the selected calculation means to the selected second storage means; a selection means selectively connected in response to a command; and a selection means configured to sequentially read out a group of data held in the selected first storage means according to a predetermined order of storage locations. means for controlling said second storage means to write a group of data outputted from said selected calculation means in said second storage means in accordance with a predetermined order of storage positions; Then, the first
control means having a detection/inhibition means for detecting whether data to be read next from the storage means already exists therein, and prohibiting reading of the data when the data does not exist; It is characterized by

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to Examples.
First, in order to clarify the configuration and functions of the FiFO memory used in the present invention, the configuration and operation of a data processing device when arithmetic units are fixedly coupled using the FiFO memory as an intermediary will be explained using Figure 1 and the following diagrams. The FiFO memory will be mainly explained, and finally, using FIG. 7, the configuration of a data processing device according to an embodiment of the present invention that can selectively combine the FiFO memory as an intermediary according to instructions from a program will be explained.

In recent years, FiFO memory has come to be applied to pipeline type arithmetic processing units, as shown in FIG. In the figure, a pipeline type arithmetic unit 1 surrounded by a dashed line consists of a pipeline arithmetic unit 2 and a pipeline control logic circuit 3 for controlling this arithmetic unit. Input data (1 bit or multiple bit data) via and 31
It receives the calculation result and sends the calculation result to another calculation unit 6 via the data line 32. FiFO memory 2
0, 21, and 22 are provided between the units as buffers for input data and calculation results. In other words, the input data from the calculation unit 4 (from the perspective of the unit 4, the calculation result of the unit 4) is input to the FiFO memory 20 from the data line 30, and then sent to the pipeline calculation in the unit 1 via the data line 10. is input to device 2. FiFO memory 21 and 2
2 is similar, and data lines 11 and 12 are used.

There are two advantages when using such a FiFO memory as a buffer.

(1) Measures against interruptions in input data from calculation units 4 and 5. In a multi-input pipeline arithmetic unit 2 as shown in FIG. 1, it is common that a large number of pairs of input data having the same number need to be input at the same time. Here, let us consider a case where input data with a certain number has arrived from the arithmetic unit 4, but the corresponding input data with the same number from another arithmetic unit 5 is delayed for some reason. FiFO memory 20 has data line 3
While accepting the data sent out in each cycle via the data line 10, the data sent out to the unit 1 via the data line 10 is sent to the other unit 5.
used to delay the arrival of input data from During this time, pipeline arithmetic unit 2
Invalid data is input to , and invalid corresponding operation results are output, but the pipeline control logic circuit 3 controls so that this invalid output is not sent to other units 6 .

(2) Countermeasures against refusal of acceptance of unit 6. Unit 6 may refuse to accept data from data line 32. FiFO memory 22 has data line 1
The calculation result from pipeline calculation unit 2 passing through unit 6 is temporarily buffered and sent to unit 6.
Used to make data wait until it can be accepted.

In this way, when the above-mentioned data discontinuity phenomenon occurs, it is effective to provide a FiFO memory between units having pipeline arithmetic units.
The functions required for this FiFO memory are as follows.

(A) It is possible to read and write simultaneously within the pipeline pitch time.

(B) Written data can be read in a short time.

Conventionally, storage elements for such high-speed FiFO memory include flip-flops (hereinafter referred to as FF) or latches that combine gates, and general memory elements (one readout or one readout per memory cycle). In many cases, one of the following was used: Although the former is sufficiently fast, it has the disadvantage of requiring an enormous number of gates to construct a large-capacity FiFO memory. On the other hand, in order to satisfy the above function (A) in a general memory element, it is necessary to execute two memory cycles within the pitch time of the pipeline. However, with the current pipeline technology and memory element speed-up technology, it is difficult to obtain a large-capacity memory element that can execute one memory cycle in half the pipeline pitch time.

The FiFO memory used in the present invention has a plurality of writable and readable data banks, a mode specifying means for repeatedly specifying the plurality of data banks to write mode, and a mode specifying means for specifying the write mode by repeatedly selecting the plurality of data banks, and The present invention is characterized in that it includes a write/read control means that writes data to a data bank, reads data from a data bank that is not specified in the write mode, and outputs the data in the order in which it is received.

Figure 2 is an overall block diagram of the FiFO memory used in the present invention.
It is applicable to any of the FiFO memories 20, 21, and 22 shown in FIG.

In FIG. 2, 47 and 48 are data banks (hereinafter simply referred to as banks), which can be written and read independently of each other.
Each data bank 47, 48 consists of one random access memory (hereinafter referred to as RAM).
Note that it is sufficient if there are two or more banks.

It goes without saying that each bank may be composed of a plurality of RAMs depending on the required capacity and word configuration.

Data sent from the outside is written to banks 47 and 48 in the order in which it was sent.
For example, the first sent data No. 0 is sent to bank 47, the next sent data No. 1 is sent to bank 48, the next sent data No. 2 is sent to bank 47, and so on. The data No. 3 sent next is written to bank 48, and so on, repeatedly to banks 47 and 48 in order. Therefore, bank 47 has 0, 2, 4,...
..., 2n (n is an integer) data, that is, even-numbered data are written in order, so they are called an even-numbered bank. Bank 48 has 1, 3, 5,
..., 2n+1 data, that is, odd-numbered data, are written in order, so it is called an odd-numbered bank.

Reference numeral 41 denotes a mode designation circuit for repeatedly designating which bank among the banks 47 and 48 is in a writable mode at a constant cycle. now,
The writable mode is called W mode, and the readable mode is called R mode. The mode specifying circuit 41 repeatedly outputs "0", "1", "0", "1", . . . at a constant cycle. When the output of the mode designation circuit 41 is “0”, even bank 4
7 is in W mode, and odd bank 48 is in R mode. When the output of the circuit 41 is “1”, “0”
Contrary to the case, the even bank 47 is in the R mode and the odd bank 48 is in the R mode. Therefore, the banks 47 and 48 repeat mode designations of R mode and W mode at a constant cycle so that the modes are different from each other at each time point, and the mode designation circuit 41
Due to this, it has been received.

Reference numeral 100 denotes a write/read control circuit for banks 47 and 48, which includes circuits 42 to 46 and 49. When even-numbered data is input, the circuit 100 immediately writes this data into the even-numbered bank 47 if the even-numbered bank 47 is in the W mode.
If the even bank 47 is not in the W mode, that is, if it is in the R mode, it waits until it becomes the W mode, and when it becomes the W mode, this data is written. The same applies to writing odd numbered data.

Further, when there is a read request and data to be read is written in the even bank 47, the circuit 100 immediately reads data from the even bank 47 if the even bank 47 is in the R mode. If the even bank 47 is in the W mode, it waits until it becomes the R mode and reads out when it becomes the R mode.

The configuration of the FiFO memory shown in FIG. 2 enables reading and writing at the same time. For example, data can be written to even banks 47 and data can be read from odd banks 48 at the same time. In FIG. 2, thick signal lines represent multiple signal lines.

Next, the operation of this FiFO memory will be explained.

In FIG. 2, when a write request is received (the write request arrives), the write request instruction signal WREQ on the signal line 33 is "1",
The value of data signal WDATA on data line 30 is write data. Signals WREQ and WDATA are
From a first external device, for example arithmetic unit 4,
Write control circuit 42 (hereinafter referred to as W control circuit)
is input. The W control circuit has means for detecting the arrival of a write request based on the signal WREQ, receiving write data from the signal WDATA, and detecting the arrival number of the arriving write request.
Suppose that it is detected that the arrival number of the write request is Nth. Depending on whether N is an even number or an odd number, it is determined whether the data bank to be written is an even number bank or an odd number bank. on the other hand,
Since the output signal SW of the mode designation circuit 41 described above designates the bank in W mode, when the data bank determined by the evenness of N matches the data bank designated by the signal SW in W mode, the W control circuit 4
2 is the address determined by the value of the upper bits excluding the lower bits in the binary representation of N.
3 is output to the signal WAH on the signal line 93, "1" is output to the write instruction signal WE on the signal line 93, and the write data to the even bank is output to the signal SDRE on the signal line 82.
The write data to the odd bank is output to the signal SDRO on the signal line 83. If there is a possibility that the bank match will not be established when a write request arrives, a means is required to store the existence of the write request and the write data until the bank match is established. A detailed embodiment of the means will be described later using FIG. 4. The W control circuit 42 is set to an initial state by an initial value setting signal START input via the signal line 39, as will be described later.

A circuit 44 surrounded by a one-dot chain line sends a write command signal WEE through signal lines 59 and 58 in response to a mode designation signal SW and a write permission signal WE.
This is a write signal generation circuit that outputs WEO to banks 47 and 48, respectively. The AND gate 441 of the circuit 44 operates when the signal SW is “0” and the signal WE
Write command signal WEE of "1" is output to the even bank 47 only when the condition that "WEE" is "1" is satisfied. In this way, when the even bank 47 is in the W mode (signal WE is "0") and there is data to be written now (signal WE is "1"), the write command signal WEE to the even bank 47 is set to " 1” is output. The AND gate 442 outputs "1" as the write command signal WEO to the odd bank 48 only when the conditions that the signal SW is 1 and the signal WE is "1" are satisfied. In this way, when the odd bank 48 is in the W mode (signal SW is "1") and data to be written now exists (signal WE is "1"), the write command signal WEO to the odd bank 48 is set to " 1” is output. and gate 4
A circle marked on one side of the input 41 indicates that the input signal is inverted.

The selection circuit 45 selects the write address WAH from bank 4 in response to the mode designation signal SW.
It operates to selectively output to either 7 or 48. The circuit 45 consists of selectors 451 and 452. When the mode designation signal SW is “0”, the selector 451 selects the write address signal WAH described above.
Of the read address signal RAH described later,
The signal WAH is selectively output to the signal line 57. Therefore, when the even bank 47 is in the write mode (when the signal SW is "0"), the write address WAH is output to the odd bank 47. signal
When SW is “1”, the selector 52 selects and outputs a read address RAH, which will be described later, to the even bank 47. The selector 452 selectively outputs a read address RAH, which will be described later, to the signal line 56 when the signal SW is "0", and selectively outputs a write address WAH to the signal line 56 when the signal SW is "1". Therefore, the write address WAH is output to the odd bank 48 when the odd bank 48 is in the write mode (when the signal SW is "1"). Selectors 451, 452 and 46 described later
1,491 selects the input from the upper left (the input from the address line 93 in the selector 451) when the signal SW applied from above is "0", and outputs the signal.
When SW is “1”, input from the lower left (selector 4
51 has a function of selecting the input from the address line 99) and outputting it to the right output line (signal line 57 in 451).

The selection circuit 46 selectively outputs the write data signal SDRE for even banks and the write data signal SDRO for odd banks in response to the signal SW, and is comprised of a selector 461. selector 4
61 selects the signal line 82 when the signal SW is "0" and outputs it to the data signal SDRE signal lines 54 and 55. When the signal SW is "1", the signal line 83 is selected and the data signal SDRO is output to the signal lines 54 and 55. Therefore, when even bank 47 is in W mode (signal SW is "0"), bank 4
Even bank write data signal SDRE is applied to 7 and 48.

Therefore, even numbered write requests are FiFO
When it reaches the memory, when the even bank is in W mode, the write terminal WET of the even bank 47 is
The signal "1" is input, the aforementioned write address signal WAH is input to the address terminal AT, this data signal SDRE is input to the data terminal DIT, and the even bank write data signal SDRE is written to the even bank 47. . However, as mentioned above, when the even bank 47 is in the W mode (when the signal SW is "0"), the odd bank 48 is in the R mode and the signal SW is "0", so the write output of the AND gate 442 is The command signal WEO becomes "0" and writing to the odd bank 48 is prohibited, so the even bank write data SDRE will not be written to the odd bank 48.

When the odd bank 48 is in the W mode (signal SW is "1"), the odd bank write data signal SDRO is applied to the banks 47 and 48.
However, for the same reason as mentioned above, this data signal SDRO is not written to the even bank 47.
This data signal SDRO is written into the odd bank 48.

Note that instead of the selector 461, the signal lines 82 and 55 are connected so that the signal SDRE is always applied to the even bank 47, and the signal lines 83 and 54 are connected.
The signal SDRO may be connected to the odd bank 48 so that the signal SDRO is always applied to the odd bank 48. However, selector 4
61, the signal lines 55 and 54 can be shared, and the banks 47, 48 and the W control circuit 4 can be used in common.
Wiring of signal lines between the two is simplified.

In this way, data number 0 is stored in even bank 4.
Data No. 7 is placed at address 0 of odd bank 48, Data No. 2 is placed at address 1 of even bank 47, Data No. 3 is placed at address 1 of even bank 48,
. . . The data is automatically and alternately written into the banks 47 and 48 in the order in which they are received, without any external designation of the address.

Note that the banks 47 and 48 have the following input/output terminals. WET is a write command signal input terminal, and the write command signal WEE to even bank 47 is
Alternatively, a write command signal WEO to the odd bank 48 is input to the terminal WET. AT is a memory address input terminal, which inputs memory address AE to even bank 47 or memory address to odd bank 48.
AO is input to terminal AT. DIT is the write data input terminal, and the data signal DIE or DIO is the terminal
Input to DIT.

DOT is a read data output terminal, and read data DOE is output from the terminal DOT of the even bank 47 to the data line 471, and the terminal DOT of the odd bank 48 is output to the data line 471.
Read data DOO is output from DOT to data line 481. When the input of terminal WET is “1”,
The banks 47 and 48 store the data on the data terminal DIT at the address indicated by the address signal input to the address input terminal AT. When the input to the terminal WET is "0", the banks 47 and 48 read the data stored at the address indicated by the address signal input to the address input terminal. Other input/output terminals of the banks 47 and 48 not shown in FIG. 2 include a power supply terminal, a chip select terminal, an output enable terminal, and the like.

Now that the writing operation has been explained, the reading operation will be explained next.

The read control circuit (hereinafter referred to as R control circuit) 43 receives an initial value setting signal START from the outside.
Initial settings are made as described below.
The R control circuit 43 stores addresses RA to be read from banks 47 and 48, as will be described later. Address RA is counted up by "1" in response to read request signal RREQ, which will be described later. Read address signal RAH is the lower one when address RA is expressed as binary bits.
This is a bit signal other than the R control circuit 4.
3 to the signal line 99. In addition, the circuit 43
stores the number M of data that has not yet been read out of the written data. Number M
is counted up by "1" each time the write permission signal WE becomes "1", that is, each time one piece of data is written, and the second external device receiving the read permission signal ROK, for example,
The read request signal RREQ input from the pipeline operation unit 1 via the signal line 15 is “1”
Each time, that is, each time one piece of data is read, the count is decremented by "1".
M is 1 or more (data that has not yet been read is written to banks 47 and 48), and this data is written to the bank for which the mode designation signal SW specifies the read mode. Only when the signal ROK is set, "1" is output to the signal ROK from the R control circuit 43 to the external device via the signal line 13. This data is bank 4
Whether it is written to either 7 or 48 is determined by 2.
It is detected whether the least significant bit of the hexadecimal read address RA is "0" or "1".

The read address signal RAH on the signal line 99 is
Depending on whether the mode designation signal SW applied to the aforementioned selectors 451 and 452 is "0" or "1",
It is applied from selectors 451 and 452 to address terminals AT of banks 47 and 48. i.e. the signal
When SW is "0", the odd bank 48 is in the read mode, and the read/write address signal PAH is output to the odd bank 48 via the selector 452. When the signal SW is "1", the even bank 47 is in the read mode, and the selector 4 is in the read mode.
A read address signal RAH is outputted to the even bank 47 via 51. In this way, the read address signal RAH is applied to the bank that is in the read mode.

Therefore, the data to be read from the address specified by the read address signal RAH in the bank that is in read mode is output from the output terminal.
Output to DOT.

A selection circuit 49 consisting of a selector 491 selectively outputs the output of a bank in read mode to the signal line 10. Mode designation signal SW
When is “0”, the odd bank 48 is in the read mode, and the selector 491 selectively outputs the data signal DOO read from the odd bank 48 to the signal line 10. This signal is the read data signal
Sent to external device as RDATA. When the mode designation signal SW is "1", the even bank 47 is in the read mode, and the selector 491 selects the data signal DOE read from the even bank 47 and sends it to the second external device via the signal line 10. ,Output. Of course, the output terminals of banks 47 and 48
If wiring logic is allowed for DOT, banks 47, 4
By controlling the inputs of the chip select terminal and the output enable terminal of 8, the function corresponding to the selection circuit 491 can be realized by simply connecting the data line 471 and the data line 481.

Note that the second external device, for example, the pipeline arithmetic unit, takes in the signal RDATA to indicate that it receives the read data when the signal ROK is "1" and it is readable.
The signal RREQ is set to "1" and output to the R control circuit 43. The R control circuit increases the read address RA by one in the next cycle when the signal RREQ is "1".

In this way, the data at address 0 of even bank 47, the data at address 0 of odd bank 48, the data at address 1 of even bank 47, the data at address 1 of odd bank 48,
Address data, such as bank 47,
The data written in banks 47 and 48 is read out in order from the oldest data written in bank 48. Therefore, FiFO in Figure 2
The memory has a so-called first-in first-out memory function. In addition, as explained above, since the mode is specified independently for each bank, when data is being written to the even bank 47, it is possible to simultaneously read the data written from the odd bank 48 and write the data to the even bank 47. It is possible to read the written data from the odd bank 481 and write the data to the odd bank 481 at the same time. That is, writing and reading can be performed simultaneously.

In the configuration shown in Figure 1, the FiFO in Figure 2
Since memory is used as 20 and 21,
The signal SW in the FiFO memories 20 and 21 must be synchronized. This is because in the pipeline arithmetic unit 2, the two input data numbers are generally always equal in the cycle in which the data is input correctly, and if the values of the signal SW at 20 and 21 are different, one side is always the same. It becomes impossible to read from the FiFO memory, and since both are not readable at the same time, no calculation can be started. In order to avoid this, a configuration may be adopted in which the signal SW in all FiFO memories in all devices always has the same value. For example, one FiFO memory 20
It is only necessary to share the SW signal with other FiFO memories 21. In FIG. 2, regarding the FiFO memory 22, the input to the arithmetic unit 6 is input to the FiFO memory 22.
There is no need for synchronization regarding the signal SW.

Next, the mode designation circuit 41, the W control circuit 42,
Regarding the R control circuit 43, more specifically, the third
This will be explained using FIG. A, FIG. 4, and FIG. 5.

The circuits 41, 42, and 43 operate with a one-phase clock signal T, and the period of this clock is the pitch of the pipeline arithmetic unit and the memory cycle time of the memory element. As shown in the lower part of FIG. 6, each cycle will be explained by numbering it. Each cycle is considered from the rising edge of T to the rising edge of the next T.

Unless otherwise specified, flip-flop (hereinafter referred to as
It is called FF. ) and the synchronous counter (hereinafter referred to as CNT) are edge trigger types that operate at the rising edge of the clock input signal T.

The single circles at the left and right signal line terminals in the diagram are
Shows the interface signals inside FiFO memory,
The double circle indicates an interface signal with the outside of the FiFO memory.

Here, the following explanation will be given as a FiFO memory that can store up to 8 pieces of input data. In this configuration, each of banks 47 and 48 only needs to have a memory capacity capable of storing four pieces of data. Furthermore, the signal line 93 for the signal WAH, the signal line 99 for the signal RAH, the signal line 57 for the signal AE, and the signal line for the signal AO may also be 2-bit address lines.

Circuits 41 and 4 shown in FIGS. 3A to 5
2 and 43 are all synchronous circuits synchronized with the clock signal T. In the following description, the following two points are assumed. (1) The gate delay time and the FF and CNT delay times are sufficiently small compared to the cycle time of the clock signal T. (2) FF and CNT operated by clock signal T
output from the next stage which operates with the same clock signal T.
No malfunction occurs even if input to FF or CNT.

The assumption in (2) above is that ``the previous FF in a certain cycle
The value of determines the value of the subsequent FF in the next cycle, and the value of the previous FF determines the value of the subsequent FF during the same cycle.
This means that it does not affect the FF value. If the assumption (1) above is not met, detailed calculation and study of the delay time including the bank used is required. If the assumption (2) above is not met, the two-phase clock signal Of course, if it is a synchronous circuit, countermeasures such as reduction are necessary.

FIG. 3A is a circuit diagram of the mode designation circuit 41. The output of the inverted output terminal of the FF50 is input to the input terminal D of the FF50. The clock terminal of the FF 50 is applied with a clock signal T which becomes "1" every memory cycle, that is, every pipeline pitch. The signal from the output terminal Q of the FF 50 becomes the aforementioned mode designation signal SW. Now, FF5
Assume that the internal state of 0 is “1”. The output "0" of the terminal at this time is input to the input terminal D. At the first rise of the clock signal T, the FF 50 receives the output "0" from the terminal Q, and the internal state of the FF 50 changes from "1" to "0". At this time,
The output of the terminal also changes from "0" to "1". Therefore, the input to input terminal D also becomes "1". At the second rising edge of clock signal T, FF50
receives the input "1" from the terminal D, and the internal state of the FF 50 returns to "1" again. In this way, at the rising edge of the clock signal T, the internal state of the FF 50 repeats inversion of "0" and "1". Therefore, the signal SW, which is the output of the output terminal Q of the FF50, also changes to "0" in response to the rising edge of the clock signal T.
Repeat inversion of “1”. This situation is shown at T and SW in the time chart of FIG. The role of the signal SW is to specify the operating mode of the bag, as described above.

FIG. 3B shows each mode of the even bank 47 and the odd bank 48 designated by the mode designation signal SW.

Note that the mode designation circuit is as follows: (1) In order to synchronize the plurality of FiFO memories described above, one mode designation circuit may be provided and used in common.

(2) When all 8 pieces of write data have arrived and there is no possibility of conflict between reading and writing on a bank, create a circuit that changes the signal SW so that the bank you want to read next can always be selected. It may be provided.

FIG. 4 is a circuit diagram of the W control circuit 42.

(3) Under conditions where there is no conflict between writing and reading, the signal SW is
A circuit for changing the value may be provided.

FIG. 4 is a circuit diagram of the W control circuit 42.

First, the roles of the CNT and FF in FIG. 4 and the functions of the main gates will be explained, and then an example of their operation will be explained according to the time chart in FIG. 6. CNT6
Reference numeral 2 denotes the edge trigger type synchronous counter described above, and the number of output bits is 1 bit.
CNT64 is an edge trigger type 3-bit synchronous counter. The terminal UP is a count up instruction input terminal, the terminal R is a reset terminal for clearing the contents to zero, the terminal CK is an input terminal of the clock terminal T, and the terminal Q is an output terminal for the counter contents. The count up operation is executed when the clock signal T applied to the terminal CK rises from "0" to "1" while the input signal at the terminal up is "1". When the input signal of the terminal up is "0", the value of CNT remains unchanged. The FF 63 is an edge trigger type FF, and like the counter described above, the value at the output terminal Q changes at the rise of the clock signal applied to the terminal CK.

The CNT 62 is reset by an external signal START, and is counted up at the end of the cycle in which the external write request signal WREQ arrives (the rising edge of the clock signal T), and its output WCNT is the write request (write request signal T) that arrives in that cycle. This indicates whether the request signal WREQ and write data WDATA are for the odd bank 48 or the even bank 47. That is, "0" of the output WCNT means a write request to the even bank 47, and "1" means a write request to the odd bank 48. Another output signal of CNT62
WCNT is a signal with the opposite polarity of the output signal WCNT.

The CNT 64 is reset by an external signal START, and counts up at the end of a cycle in which writing to any bank is executed (a cycle in which WE is "1"). The output of CNT64 is the above WA, and its upper 2 bits output WAH
indicates the write address of the bank, and its lower 1
The bit output WAL indicates whether the write bank is even or odd. That is, if the output of the CNT 64 is "000 ₂ " (the subscript 2 indicates a binary number; the same applies hereinafter), the W control circuit 42 instructs address 00 ₂ of the even bank 47 as the write destination. If the output of the CNT 64 is "001 ₂ ", it indicates address 00 ₂ of the odd bank 48, and if it is "010 ₂ ", it indicates address "01 ₂ " of the even bank 48. In order to actually write in a bank, a write enable signal WE, which will be described later, must be "1".

If the signal WREQ is “1” in a certain cycle, a write request is sent to the W control circuit 42 in that cycle.
has arrived. The data signal to be written is the signal WDATA in that cycle. That is, the corresponding signal WREQ and signal WDATA arrive at the W control 42 in the same cycle.

As shown in FIG. 3B, in a certain cycle, either the even bank 47 or the odd bank 48 is designated to the W mode depending on the value of the signal SW. On the other hand, a write request arriving at the W control circuit 42 from the outside arrives independently of the value of the signal SW. Therefore, the W control circuit 42 executes one of the following two write operation procedures in response to each arriving write request.

(a) In the same cycle as the one in which the request arrived,
Writing to the bank is executed. When a certain request arrives and the even-odd number of the arriving request (that is, the even-odd number of the write destination bank) matches the even-odd number of the bank in the W mode state in the cycle in which the request arrived, write (a). An operating procedure is executed. Hereinafter, this will be referred to as the direct write procedure.

(b) In the cycle following the cycle in which the request arrived,
Writing to the bank is executed. When a certain request arrives and the evenness of the number of the arrived request does not match the evenness of the bank in the W mode state in the cycle in which the request arrived, the write operation procedure (b) is executed. Hereinafter, this will be referred to as delayed writing.

The exclusive OR (hereinafter referred to as EOR) gate 69 in FIG. 4 recognizes the mismatch between the evenness and oddness of the arriving request number and the evenness and oddness of the W mode bank. In other words,
EOR gate 69 on signal line 88 in one cycle
If the output of is “0”, evenness and oddness match,
If a request arrives, a direct write procedure should be performed. Further, if the output of the EOR gate 69 is "1", the evenness does not match, and if a request arrives, the delayed write procedure should be executed. AND gates 69 and 68 authorize the execution of direct write procedures and delayed write procedures, respectively. The circle marked on one of the input terminals of the AND gate 69 indicates the inversion of the input signal, similar to the AND gate 441 in FIG. In other words, the necessary and sufficient condition for the output of the AND gate 69 to be "1" is that the signal WREQ on the signal line 33 is "1" and the signal on the signal line 88 is "0".

If the output of the AND gate 69 on the signal line 90 is "1", the write permission signal WE on the signal line 91 becomes "1" via the AOG gate 70,
Writing to the bank is executed in the cycle in which the write request arrives. This is the execution of a direct write operation.

If the output of the AND gate 68 on the signal line 89 is "1", "1" is input to the FF 63 from the terminal D, and in the next cycle, the FF on the signal line 86
The output signal WREQDL of 63 becomes "1", the signal WE becomes "1" via the OR gate 70,
Writing in the bank is executed in the next cycle after the write request arrives. This is the execution of the delayed write procedure. The FF 63 stores the arrival of a write request to be executed in the delayed write procedure, and instructs bank writing in the next cycle.

When the signal WE is "1", writing is executed in the even bank 47 or the odd bank 48. Whether the write destination bank is even or odd can be determined by both the signal SW and the signal WAL. As mentioned above, in the embodiment shown in FIG. 2, the signal SW is used as an even/odd selection signal for the write destination bank.

Regarding the write instruction signal WREQ, there are cases in which its value is transmitted as the signal WE during the cycle in which it reaches the W control circuit 42 in this way, and there are cases in which it is temporarily stored and transmitted as the signal WE in the next cycle. be able to. Regarding the write data signal WDTA, there are cases where its value is used directly and cases where it must be stored until the next cycle. Similarly to the signal WREQ, the signal WDATA also consists of two groups of AND gates (AND gate 6
8 and 69) FF group (equivalent to FF63) and OR
The operations in the above two cases can also be realized using a gate group (corresponding to OR gate 70). However, FIG. 4 shows an alternative scheme using two groups of latches.

The operation of latches 60 and 61 is different from the edge trigger type FF mentioned above. When the clock signal from input terminal CK is "1", the input contents from input terminal D are immediately output from output terminal Q. Therefore, when the clock signal falls from "1" to "0", the input contents from input terminal D are held (the holding operation is called a latch operation), and the held contents are retained when the clock signal falls from "0" to "0" again. ” to rise to “1” is output from the output terminal Q.

Latch 60 is used to temporarily hold even-numbered write data (write data to even-numbered bank 47), and latch 61 is used to temporarily hold odd-numbered write data (write data to odd-numbered bank 48). used for holding. Consider the cycle in which the even numbered write request arrives.
Since the signal is "1", the contents of the signal WDATA are output as they are to the output signal SDRE of the latch 60, and when the next cycle starts, the signal falls from "1" to "0" and the contents of the signal WDATA are retained. In the next cycle, the contents of the signal SDRE are the same as in the previous cycle. In other words, the even numbered write request arrives and the even numbered bank 47 in the cycle.
The signal is
The contents of SDRE are the correct even-numbered write data contents.

Latch 61 and its output signal SDRO also
They have the same configuration except that the clock signal to 1 is the signal WCNT, and the contents of the signal SDRO are the contents of the correct data to be written to the odd bank.

Next, the write operation of the FiFO memory 20 will be explained based on the operation example shown in the time chart of FIG. Arriving write requests are numbered from 0th to 7th, starting with address 0 of even bank 47, address 0 of odd bank 48, address 1 of even bank 48, and address 3 of odd bank 48.
It is written up to the address.

Although not shown in FIG. 6, CNT62 and CNT64 are reset to "0" by a "1" pulse of signal START prior to a series of write operations. FF63 also sends a signal to the reset terminal R.
Since the START pulse of "1" is input, it is similarly reset, indicating that the first write request is an even-numbered one.

In the operation example shown in FIG. 6, the direct write procedure is executed for the 0th to 2nd write requests, the delayed write procedure is executed for the 3rd and 4th requests, and the 5th to 7th A direct write procedure is performed for the second request.

First, the 0th write request arrives in the cycle. The signal WREQ on the signal line 33 and the signal WDATA on the data line 30 are input to the W control circuit 42. In other words, WREQ is “1” and the signal
The content of WDATA is the 0th write data.
In the cycle, the signal WCNT is still "0", and in the example of FIG. 6, the signal SW is "0", which indicates that the even bank is in W mode.
The output of the EOR gate 67 is "0", the output of the AND gate 68 is "0", the output of the AND gate 90 is "1", and the output signal WE of the OR gate 70 is "1". In a cycle in which the signal WE is "1", writing is executed in the bank designated as W mode by the signal SW, as shown in FIG. In other words, the AND gate 44 in FIG.
1, the signal WEE on the signal line 59 becomes "1" and a write operation in the even bank 47 is instructed.

Next, the write address will be explained. After CNT64 in Figure 4 is set by signal START
The output of CNT64 remains “000 ₂ ” during the cycle, and the signal which is the upper 2 bit output is
WAH is also output to the address line 93 as "00 ₂ ". In FIG. 2, selector 451 determines the content of memory address signal AE to even bank 47.
Since the signal SW is “0”, the write address signal WAH on the address line 93 is selected and the address line 5 is
The signal WAH is output to 7. As a result of the above, the correct address "00 ₂ " is input to the address terminal AT of the even bank 47 in the cycle. In the odd bank 48, the signal RAH is input to the address terminal AT by the action of the selector 452, but the signal WEO is set to "0" by the action of the AND gate 442.
Therefore, erroneous writing will not be executed.

Next, write data will be explained. In FIG. 4, since the signal is "1" in the cycle, latch 60 immediately transfers the signal WDATA corresponding to the 0th request on data line 30 to data line 82.
Output as signal SDRE on top. The selector 461 in FIG. 2 selects the data line 8 because the signal SW is "0".
The signal SDRE on the line 2 is output to the data line 55.
That is, in the cycle, the 0th write data signal WDATA is correctly input to the data input terminal DIT of the even bank 47. In the embodiment shown in FIG. 2, the 0th write data is also input to the data input terminal DIT of the odd bank 48, but the AND gate 44
2 ensures that the signal WEO is "0", so no erroneous writing will be performed.

The first write request also arrives in the cycle,
Also, writing to banks is executed during the cycle, but this cycle differs from the cycle in that the writing destination is odd-numbered bank 48. In other words, in Fig. 2, the signal
Since SW is “1”, signal WEE is “0”,
Signal WEO is "1". The value of signal WAH is selected by selector 452 and output as signal AO, and the value of signal SDRO is selected by selector 461 and output as signal DIO. Figure 4, 3
The value of bit CNT64 is set when the signal WE becomes “1” in the cycle when changing from cycle to cycle.
Therefore, it increases to “001 ₂ ”. The output signals WCNT and WCNT of CNT62 are also cycled by the signal WREQ.
Since they are "1", they are inverted to "1" and "0" respectively in the cycle. Even in the cycle, the output of AND gate 68 is “0”, so the output of FF63
WREQDL remains "0" throughout the cycle. The contents of the signal WDATA are held in the latch 60 during the cycle, and although they are output as the signal SDER during the cycle, they are not used.

A second request arrives in the cycle and is written to even bank 47 during the cycle. Since the signal WE is "1" in the cycle, the output of CNT64 is "010 ₂ " in the cycle, and the second write request data signal WDATA is in even bank 4.
It is written in the first position of 7.

The time chart in FIG. 6 shows an example of the operation when the third write request arrives at a cycle instead of a cycle. In the cycle, the arriving request is odd numbered and in odd bank 4.
8 is not in W mode, the third write request is executed in odd bank 48 in the next cycle. In FIG. 4, in the cycle, the signal
WCNT is "1" and signal SW is "0". Due to the action of EOR gate 67 and AND gates 68 and 69, the signal on signal line 89 becomes "1" and the signal on signal line 88 becomes "0". FF63 is
Since "1" is input to the input signal terminal D, "1" is outputted to the signal WREQDL for the first time in the next cycle. The bank write enable signal WE is "0" in the cycle, and becomes "1" to instruct the third write in the cycle. This operation is
This is the delayed write procedure described above.

Since WE is "0" in the cycle, the CNT 64 that creates the write address WA holds the same value "011 ₂ " from cycle to cycle, and is the correct value as a memory address in the odd bank memory 48 in the cycle. “01 ₂ ” is input.

Next, write data will be explained. A third write data signal WDATA arrives in the cycle. Signal that serves as the clock signal for latch 61
Since WCNT becomes "1" during the cycle and "0" during the cycle, the output signal SDRO of latch 61
The contents of the signal WDATA are the same from cycle to cycle as well as cycle to cycle.

Therefore, in the cycle odd bank 4
8, the write data of the third request can be input correctly.

In the W control circuit 42 of FIG.
It is assumed that the third write request cannot be executed in one cycle, but can be executed in the next cycle. In other words, if the signal SW is "0" in a cycle, it is predicted from the periodicity of SW that the signal SW will be "1" in the next cycle.

The fourth write request also arrives when the even bank 47 is not in the W mode (cycle), so it is written to the even bank 47 with a one cycle delay.

Since the 5th request arrives when the even bank 48 is in W mode (cycle), the 5th request is immediately sent to the even bank 4, just like the 0th, 1st, and 2nd requests.
8 is written. i.e. the corresponding signal WREQ
A direct write procedure is executed in which the signal WE and signal WE become "1" in the same cycle.

For every 8 write requests written to the bank, 3
The bit counter CNT64 is counted up and its output increases from "000 ₂ " to "111 ₂ ". Although it may return to "000 ₂ " in cycle 10, the contents of address 00 ₂ of the even bank 47 will not be destroyed because the 8th write request does not arrive from the outside.

FIG. 5 is a circuit diagram of the R control circuit 43. Edge-triggered counter (hereinafter referred to as CNT) 1
00 is a 4-bit counter that can count up and count down. The counter 100 is instructed to count up and down by inputting the count up terminal UP and the count down terminal DOWN. When the input signal WE of the terminal UP is "1" and the input signal RREQ of the terminal DOWN is "0", the counter 100 counts up by "1" at the rising edge of the clock signal T input to the clock terminal CK. do. Input signal WE of terminal UP is “0”
Then, when the input signal RREQ of the terminal DOWN is "1", it similarly counts down by "1". When both inputs are "0" or "1", the counter does not count up or count down. CNT10
The 4-bit output REQCNT of 0 is connected to the 4 data lines 1
01. The value of CNT100 indicates the number of pieces of data that have been written but not yet read. For CNT100, the number of input data is 0 to
It consists of a 4-bit counter so that nine types up to eight can be stored. The CNT 100 is reset by the initial value setting signal START inputted to the reset terminal R. The 4-bit output of the CNT 100 is input to an OVER gate 104, each bit is inverted, and the result is output to a signal line 105. When the output of the overgate 104 is not 0,
This indicates that there is data that has been written to banks 47 and 48 but has not been read yet. CNT109
is a binary 3-bit counter, which is reset by the initial value setting signal START input to the reset terminal R, and by the input signal to the count up terminal UP.
When RREQ is "1", it is counted up at the rising edge of the clock signal T input to the clock terminal CK.

The 3-bit binary value of CNT 109 indicates the read address. CNT109 reads the upper 2 bits of the counter value from the bank address RAH.
The lower one bit is outputted to the signal line 111 as a signal RAL indicating whether the bank to be read is even or odd.

Reference numeral 112 denotes an EOR gate for detecting whether the bank to be read now and the mode designation signal SW match the bank designated for reading. When the least significant bit signal RAL of the CNT 109 is "0", the even bank 47 is the bank to be read now, and when the signal SW is "1", the even bank 47 is in the R mode. Signal RAL
When is "1", the odd bank 48 is the bank to be read now, and when the signal SW is "0",
This odd bank 48 becomes the R mode. Therefore, the EOR gate 112 allows signals RAL and SW to
The condition that "1" is output when "0" and "1" or "1" and "0" are present, and "0" is output at other times is satisfied. The AND gate 106 performs a logical product of the signals on the signal lines 105 and 113. Therefore, and gate 1
When the read permission signal ROK, which is the output of 06, becomes "1", there is data written in banks 47 and 48 that has not been read yet, and the bank with data to be read is in the read mode. This is only when the following conditions are met. Otherwise, it is "0". signal
As mentioned above, ROK is a signal that indicates that data can be read from the FiFO memory.

The operation of the R control circuit will be explained based on the operation example of the time chart in FIG. An external circuit guarantees that the read request signal RREQ input from the signal line 15 becomes "1" only when the signal ROK is "1". For example, the pipeline control logic circuit 3 of FIG. 1 ensures this. In addition, the signal START prior to a series of read requests causes the CNT100,
This is the same as W control in that 109 is initially set to "0".

In the cycle in which the 0th write data is written to the even bank 47, the signal WE becomes "1".
CNT100 counts up at the next rising edge of clock signal T, and in the cycle, its output
REQCNT becomes “0001 ₂ ” and Owagate 104
outputs "1" to the signal line 105, indicating that unread data exists in the bank. On the other hand, in the cycle, the signal SW is "1" and the EOR gate 112 detects that even bank 47 is in the R mode, and outputs "1" to the signal line 113. AND gate 1 indicates that two conditions are met.
06 makes the determination and outputs "1" onto the signal line 13 as the signal ROK.

In the example in Figure 6, this response is an external signal.
The case where RREQ is "1" is shown. When the signal RREQ on the signal line 15 is “1”, CNT1
Count up 09. In the cycle, the signal WE indicating the first write becomes "1" at the same time, so the CNT 100 does not perform a counting operation. In the next cycle as well, the output signal REQCNT is held as "0001 ₂ ", indicating that there is one piece of unread data. In the cycle,
The output signal RAH of the upper two bits of the CNT 109 is "00" and is sent to the selection circuit 45 in FIG. 2 via the data line 99. In this cycle the signal
SW is "1", and the selector 451 in the selection circuit 45 selects the signal RAH and sends it to the address terminal AT of the bank 47. On the other hand, since the signal SW is "1", the AND gate 441 in FIG.
Set WEE to “0”. Since the signal WEE is “0”, the bank 47 executes the read operation to the “00” address indicated by the signal AE, and sends the contents of the 0th data written in the previous cycle to the data line as the signal DOE. 471. Since the signal SW is "1", the selector 491 in FIG.
Select DOE and use data line 10 as signal RDATA
Output to. With the above operation, the 0th data is output to the signal RDATA during the cycle.

The same operation is performed for reading the first and second data, except for the value of the signal SW and whether the bank used is even or odd.

Writing of the third data is executed three cycles after completion of writing the second data. Therefore, in the second data read cycle, the signal RREQ is "1" and the signal WE is "0", so CNT100 is counted down, and in the next cycle, the signal REQCNT becomes "0000 ₂ ", The signal ROK should be "0", the signal RREQ="1" should not be input, and 3
The read operation for the th data is not executed. In the cycle following the cycle in which the signal WE becomes "1" in response to the third write request signal WREQ, the signal REQCNT becomes "0001 ₂ " and the signal
ROK becomes “1”. However, the operation example in FIG. 6 shows a case where the signal RREQ remains at "0" due to another external factor. In the next cycle, the signal SW becomes 1 and the odd bank 48 in which the third data is stored is not in the R mode, so the signal ROK becomes "0". In this cycle, the value of CNT100 is "0010 ₂ " reflecting the fourth write in the previous cycle. In the next cycle, the signal SW is “0”, so the signal
In the example shown, ROK is "1" and "1" is input as the signal RREQ. In this cycle, the signal REQCNT has increased to "0011 ₂ ".

An example is shown below in which the fourth to seventh data are read out consecutively. The seventh and final data in the cycle is sent out as signal RDATA. from cycle to cycle
During 13 cycles, 8 write requests and 8 read requests are processed in this FiFO memory.
In particular, during the four cycles from cycle to cycle, four write requests and four read requests are processed in parallel, one each in each cycle.
The maximum processing power of FiFO memory is demonstrated.

FIG. 7 shows the above-mentioned system as an embodiment of the present invention.
This figure shows the configuration of a data processing device in which multiple arithmetic units are dynamically connected according to instructions from a program using FiFO memory as an intermediary. By using the FiFO memory described up to FIG. 6, the function of correctly transferring data from arithmetic unit to arithmetic unit even if write data occurs intermittently is realized.

Pipeline calculation units 901, 90
2,903 and FiFO memory 921,922,92
Distribution logic circuit 911 between 3,924,925
and 912 intervene. Distribution logic circuit 911, 91
2 has a function of allocating FiFO memory to the input source and output destination of each unit according to instructions from the outside. The distribution logic circuits 911 and 912 consist of a plurality of multi-input selector groups, and are well-known.
For example, at a certain point, the distribution logic circuit 912 selects the output of the FiFO buffer 921 as the input to the unit 903, and the output of the unit 903 is
The distribution logic circuit 911 can be selected to be an input to the FiFO memory 922, and at another time the FiFO memory 923 can be selected as an input to the unit 903.
Dynamic reconfiguration is possible by selecting FiFO memory 924 as the output. Distribution logic circuit 91
1,912 can be configured using a large number of selectors.

Note that each configuration of the FiFO memory 921, ..., 925 is configured by excluding the circuit 41 of the FiFO memory shown in FIG. It is provided and shared among each FiFO memory 921, . . . , 925.

The calculation unit shown in FIG. 7 may be not only an arithmetic operation unit that performs four arithmetic operations, but also a storage control unit that can store a large amount of data.

〔Effect of the invention〕

As explained above, according to the present invention, multiple arithmetic units and storage control devices that can operate simultaneously are dynamically coupled, and even if valid data is intermittently output, correct data is made available to subsequent arithmetic units. It is possible to provide a data processing device that inputs the data as data to a subsequent arithmetic unit.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional pipeline processing unit to which FiFO memory is applied;
The figure is a block diagram of the FiFO memory used in the present invention, FIG. 3A is a circuit diagram showing an example of a mode designation circuit that designates the operation mode of the bank, and FIG. A diagram showing the bank mode, FIG. 4 is a W which controls bank writing.
FIG. 5 is a circuit diagram showing an example of a control circuit, FIG. 5 is a circuit diagram showing an example of an R control circuit that controls bank reading, FIG. 6 is a time chart for explaining the operation of the FiFO memory, and FIG. 1 is a block diagram of a pipeline type data processing device which is an embodiment of the present invention. FIG. 41...mode designation circuit, 47...even bank, 48...odd bank, 100...write/read control circuit.

Claims (1)

[Scope of Claims] 1. A plurality of storage means each holding a group of data and capable of performing read and write operations in parallel, each of which performs arithmetic operations on sequentially input data and responds to the arithmetic results. a plurality of arithmetic means for outputting the data to be input in parallel with the reception of new input data; and a plurality of arithmetic means for outputting the data to be output in parallel with the reception of new input data; and selecting the plurality of storage means and the plurality of calculation means in response to a command so as to sequentially supply the group of data output from the selected calculation means to the selected second storage means. a selection means connected to the selected first storage means; controlling the first storage means to sequentially read out a group of data held in the selected first storage means according to a predetermined order of storage positions; means for controlling the second storage means to write a group of data output from the selected calculation means into the second storage means in accordance with a predetermined order of storage positions, the first
control means for detecting whether or not the next data to be read from the storage means already exists therein, and for prohibiting the reading of the data if the data does not exist; Processing equipment. 2. The control means is a read control means that is provided for each storage means and sequentially reads out a group of data from each storage means under the control of the detection/inhibition means, and the control means is a readout control means that sequentially reads out a group of data from each storage means under the control of the detection/inhibition means, and which controls the storage location within each storage means. and a write control means provided for each storage means for sequentially writing a group of data supplied to each storage means, the write control means being provided for each storage means and sequentially writing a group of data supplied to each storage means. 2. The data processing device according to claim 1, further comprising: a write counter that generates addresses for storage locations in a predetermined order; 3. The detection/inhibition means detects that the next data to be read already exists based on the difference between the number of data written in the selected first storage means and the number of data already read therefrom. 2. The data processing device according to claim 1 or 2, comprising means for detecting whether or not. 4. The detection/inhibition means detects whether one and the other of the pair of data to be read next already exist in one and the other of the pair of storage means selected for reading, and 2. The data processing device according to claim 1, further comprising means for prohibiting reading of the pair of data when it is detected that one of the data does not exist. 5. The detection/inhibition means is connected to the read control means and the write control means provided for each storage means, and detects for each storage means whether data to be continued next already exists or not. 2. The data processing device according to claim 2, having a plurality of detection means for detecting whether or not the data is detected. 6 The detection/prohibition means is one of the plurality of detection means,
Reading the data from the selected storage means in response to a detection result indicating that there is no data to be read next from a detection means provided for the storage means selected for reading. 6. The data processing device according to claim 5, having a prohibition means for prohibiting. 7. The prohibition means prohibits the absence of one or the other of the pair of data to be read next from either of the pair of detection means provided for the pair of storage means selected for reading. 7. The data processing device according to claim 6, further comprising means for inhibiting reading of the pair of data from the pair of storage means in response to a detection result indicating . 8. Clause 5, wherein each of said detection means is means for detecting the existence of data to be read next from the difference between the number of data already written in the corresponding storage means and the number of data read therefrom. data processing equipment.