JPS62147558A - Sequencer - Google Patents

Abstract

PURPOSE:To minimize the variance of answer time and to improve the accuracy of positioning control etc. by restarting a sequence arithmetic operation through a CPU at the first program address when an interruption is applied. CONSTITUTION:When the input signal of a sensor 7 connected to a synchronizing input circuit 6 is changed to an ON state from an OFF state, the circuit 6 detects the change of the external input signal and applies an interruption signal to the interruption input of a CPU 1. When receiving this interruption input, the CPU 1 cancels a cyclic sequence arithmetic operation even under process and resets the first address of a sequence program to start again the sequence arithmetic operation from the first. As a result, the answer time of a sequencer has an equal delay of a single scan regardless of the timing with respect to the change of the external input signal supplied to the circuit 6. This delay has no relation with the sampling cycle and therefore the variance of the answer time is minimized.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a sequencer 6 [Background Art 1 Conventionally, a sequencer using a cyclic calculation system receives an external input signal from an input circuit and uses a user program as shown in FIG. Sequence calculation is performed according to the following, and then output (number 3) is output to the output circuit.For example, even if the external input signal changes from off to on at point a, it changes from off to on at point b. Even if the sequencer's internal CPU inputs and detects this change, it will be difficult to input and detect this change. variations in period) occur.

In reality, variations in the response times of the input/output circuits are also added.

In other words, variation in response time to external input signals = (1
The calculation time for the scan is 100 m5 ec) + (the divisor of the variation in response time of the input/output circuit - 5 ec).

When positioning is performed by controlling a motor or solenoid pulp using a sequencer, variations in response time have a large effect on positioning accuracy. Therefore, in order to improve the positioning accuracy and the timing accuracy of the machine, it is necessary to reduce the variation in response time as much as possible.

[Object of the Invention 1] An object of the present invention is to provide a sequencer that always has a constant response time to a certain input signal and has improved control accuracy for positioning and the like.

[Disclosure of the Invention] As shown in FIG.
A CPU that controls the movement of the system itself, a memory 2 that stores sequence programs, and external input signals from sensors 7 and the like are input to the CPU via a data bus 3.
an input circuit 3 for sending the CPUI output signal through the data bus 5, and an output circuit 4 for driving the external 7 actuators (motor, solenoid pulp), etc.
The CPU detects changes in external input signals from sensor 7, etc.
It consists of a synchronous input circuit 6 that outputs an interrupt signal to the interrupt input of I. As shown in FIG. 2, the synchronous input circuit 6 includes a chattering removal circuit 6& that removes chattering components of the external input signal from the sensor 7, a rising detection circuit 6b that detects the rising edge of the external input signal, and a rising edge detecting circuit 6b that detects the falling edge of the external input signal. Fall detection circuit 6c and rain detection circuit 6
b, 6cl, which takes the OR of the outputs of c).

Normally, the CPU first takes in external input signals from the sensor 7 etc. from the input circuit 3 via the data bus 5, performs sequence calculations according to the sequence program stored in the memory 2, and sends the results to the output circuit 4 via the data bus 5. The output of 0 or more is one scan of the cyclic operation,
By repeatedly performing this scan, the sequencer
Performs sequence control. Therefore, if the input signal of the sensor 7 connected to the synchronous input circuit 6 changes from OFF to ON, the synchronous input circuit 6 detects the change in the external input signal and sends an interrupt signal to the interrupt input of the CPUI. give. Upon receiving the interrupt input, the CPU cancels the operation even if it is in the middle of a cyclic sequence operation, returns to the first address of the sequence program, and restarts the sequence operation from the beginning.

In other words, the process starts with taking in an external input signal from the input circuit 3. Therefore, the response time of the sequencer to a change in the external input signal input to the synchronization input circuit 6 is the same one scan delay regardless of the timing. In other words, in FIG. 3, the response time from the change point a or a until the output is generated is 1. Alternatively, since t2 requires only the time required for input, the time required for sequence calculation, and the time required for output, it is always equal to the calculation time of one scan from the input of the external input signal to the generation of the output. Therefore,
Since the sampling period, which had a large effect on conventional response time variations, is no longer involved, the variations become extremely small.

Incidentally, as shown in FIG. 4, the synchronization input circuit 6 may be configured to detect only the fall (or rise) of the external input signal.

Further, as shown in FIG. 5, the output signal of the synchronization input circuit 6 is
In addition to being used as an interrupt input to the PU 1, it may also be output to the instantaneous output circuit 8 as an instantaneous response output to an external actuator.

[Effect of the invention 1 The present invention is a cyclic calculation type sequencer,
It is equipped with a CPU that performs sequence operations in response to external input signals and generates response outputs, and means that detects changes in external input signals and provides CPU interrupts.When an interrupt occurs, the CPU executes a sequence from the first program address. Since the calculation is restarted, when a change in the external input signal is detected, the sequence calculation can be restarted from the beginning at that point.
Since a response output is produced after the scanning calculation time, the variation in response time becomes extremely small, and the accuracy of positioning control, etc. can be improved.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, FIG. 2 is a circuit configuration diagram of the same synchronous input circuit, FIG. 3 is an explanatory diagram of the operation of the same, and FIG. Example circuit diagram,
FIG. 5 is a circuit configuration diagram of the main part of another embodiment of the present invention, and FIG.
The figure is an explanatory diagram of the operation of a conventional example, in which 1 is a CPU and 6 is a synchronization input circuit. Figure 2 Figure 3 Figure 4 Figure 6

Claims (1)

[Claims] (1) A sequencer using a cyclic calculation method, which includes a CPU that performs sequence calculations in response to external input signals and generates a response output, and a means for detecting changes in the external input signals and providing an interrupt to the CPU. A sequencer characterized in that when an interrupt occurs, a sequence operation is restarted from the first program address in a CPU.