JPS62143432A - Manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE:To restrain any slip of silicon wafer with large diameter from occurring by a method wherein N atoms increasing the mechanical strength of silicon are contained only in the peripheral region of wafer under the maximum effect of thermal stress during heat-treatment process. CONSTITUTION:An element e.g. an oxide film 1 is formed using a wafer 2 wherein the distribution of nitrogen atoms is higher in the peripheral part than that in the central part. The peak value of concentration exceeding 4X10<14>cm<-3> is effective. Through these procedures, any slip of wafer during heat-treatment at high temperature can be restrained from occurring.

Description

[Detailed description of the invention] [Field of application of the invention] The present invention relates to a method for manufacturing a semiconductor device.

[Background of the invention]

Currently, in the manufacture of silicon semiconductor devices, diameters of 5 to 6
7-inch wafers are currently being used, and in the future
The situation is such that large-diameter 8-inch wafers are being introduced. The biggest problem when using large-diameter wafers is that the wafer slips from the periphery due to thermal stress caused by the temperature difference between the center and periphery of the wafer during heating and cooling during high-temperature heat treatment. occurs, and the wafer is easily deformed.

Slip from the wafer periphery, that is, the occurrence of dislocations, reduces the yield of semiconductor devices, so it is necessary to take measures to prevent the occurrence of slips in the heat treatment process. The occurrence of slip depends not only on the wafer diameter but also on the heat treatment temperature.

It also depends very strongly on the wafer insertion/extraction speed, the spacing between wafers on the wafer boat, and the interstitial oxygen concentration of the wafers.

For this reason, as a measure to prevent slipping when heat treating large-diameter wafers at high temperatures of 1000°C or higher, a heat removal/slow cooling method called ramping is adopted, and the spacing between the wafers lined up on the boat is widened, and the insertion and The current solution is to slow down the withdrawal speed.

However, as the diameter of wafers becomes larger, the time required for heat treatment increases, and the number of wafers processed per heat treatment decreases, resulting in a decrease in throughput. This results in the loss of benefits.

By the way, as a measure to prevent slippage, there is a method of increasing the mechanical strength of the silicon wafer itself, in addition to the above-mentioned method of devising heat treatment of the wafer. Journal of Applied Physics, an American academic journal published in 1983.
ed Physics) Volume 54, 5016-5020
According to a paper published on the page, N in silicon crystals
J7i particles have the function of fixing dislocations and increasing the strength of silicon crystals. Therefore, during silicon crystal growth, NJM
A possible method for preventing slippage is to dope the silicon wafer and use an N-doped silicon wafer.

However, at present, although the effect of increasing the mechanical strength of N atoms is clear, the electrical influence on semiconductor devices is 1. In addition, since the interaction with oxygen and carbon atoms that can cause crystal defects in silicon is not yet clear, doping NJJK elements into the region where semiconductor devices are formed may reduce the reliability of the device. I have a problem thinking about it.

[Purpose of the invention]

An object of the present invention is to provide a method for manufacturing a semiconductor device that can suppress the occurrence of slip in the large-diameter wafer and manufacture high-quality semiconductor elements.

[Summary of the invention]

To achieve the above object, the present invention suppresses slip in large-diameter silicon wafers by including NM elements that increase the mechanical strength of silicon only in the wafer peripheral region that is most susceptible to thermal stress during heat treatment. It is something.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail based on examples.

First, a CZ silicon wafer of P type (resistivity: 8 to 12 Ω), 5 inches in diameter, and 550 μm in thickness was heated at 1000°C.
After forming an oxide film with a thickness of approximately 300 nm through oxidation in an et○2n atmosphere, an oxide film pattern as shown in Fig. N ions are implanted only in the area (6 mm). A cross section of the wafer at this time is shown in FIG.

N ions are implanted at an acceleration voltage of 100 keV and a dose of 5.
The concentration peak value was set to be below the solid solubility limit of 4.5 x 10" cm.

After implantation, the oxide film was removed.

In this way, 15 wafers doped with N ions at the periphery of the wafer were combined with 15 wafers (hereinafter referred to as standard wafers) made from the same ingot.
A total of 30 sheets were arranged at 5 m intervals in a quartz boat, inserted into a 1000°C diffusion furnace at a speed of 9.0 m/min, and heated in a Nz atmosphere for 30 minutes.
After holding for 0 minutes, it was pulled out of the oven at the same speed as it was inserted. After withdrawal, the wafer positions on the quartz boat were interchanged quite arbitrarily. This series of treatments was defined as one cycle, and the same heat treatment was repeated four more times. That is, 1000℃.

After a total of five 30-minute heat treatments, the occurrence of slip around the wafer was examined using 5ecco etching solution. As a result, when summarized using the length 1- of the longest slip line that included the wafer periphery as a criterion, N
In the ion-implanted wafers, a slip line of 1 square or more was observed only in one of the 15 wafers, but in all 15 standard wafers, slips of 1 or more were observed.

As can be seen from the above examples, the occurrence of slip during high-temperature heat treatment is suppressed in the wafer in which the periphery of the wafer is doped with N ions. In addition, as a result of an experiment in which the amount of ion implantation was changed, the peak value of a degrees was 4 x 10 ''0
It is valid if it is 11-” or more.

〔Effect of the invention〕

As explained above, by using the present invention, it is possible to suppress the occurrence of slips in the periphery of the wafer.
Even when large-diameter wafers are subjected to high-temperature heat treatment, high-performance silicon semiconductor devices can be manufactured with high yield without reducing throughput.

[Brief explanation of drawings]

FIG. 1 and FIG. 2 are a plan view and a sectional view, respectively, showing an embodiment of the present invention.

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device, characterized in that elements are formed using a wafer in which nitrogen atoms are distributed more in the wafer's periphery than in its center.