JPS62143210A - Reproducing circuit for magnetic storage device - Google Patents

Abstract

PURPOSE:To remarkably improve the stability without any adjustment by employing a digital circuit at least for either a peak detection circuit or a demodulation circuit. CONSTITUTION:A read signal RS amplified properly by a read amplifier 20 is subjected to analog/digital conversion by an A/D converter 50 as required and the result is inputted sequentially to a digital detection circuit 60 as a digital read signal DRS. A digital filter of the digital peak detection circuit 60 is constituted of shift register while using a clock CK as a transfer clock by digital delay circuits 61a, 61b, and 61c. A zero cross detection circuit compares a code of a reception signal with that before one sample sequentially while a digital read signal DRS' outputted via said digital filter is received by a memory circuit 65 and a code comparator 66 at the same time to output a read data pulse RDP. A digital demodulation circuit 70 has a demodulation logic circuit 77 applying a required logic conversion to the quantized data and obtaining an MFM demodulation data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reproducing circuit for a magnetic storage device, which is used in a magnetic storage device such as a magnetic disk device and reads out and reproduces a stored signal.

[Conventional technology]

FIG. 5 shows the conventional general configuration of such a reproducing circuit, and FIG.
An example of the operation of the reproducing circuit assuming the UencyModulation method is shown below.

Hereinafter, the functions of this conventional reproducing circuit will be briefly explained with reference to FIGS. 5 and 6.

A minute level signal sequentially output from a magnetic disk (not shown) through the reproducing head 10 is suitably amplified by the read amplifier 20 and is applied to the peak detection circuit 30 as a read signal RS as shown in FIG. 6(a). The peak detection circuit 30 is a circuit that includes a differentiation circuit and a zero-cross detection circuit and detects the peak point of the received signal, that is, the Iζ point in response to changes in the magnetic flux of the signal, and is a circuit that detects the Iζ point shown in FIG. 6(a). Regarding the read signal R3, the magnetic flux changing point is detected and a pulse corresponding to the detected point as shown in FIG. 6(b), a so-called read data pulse RDP, is output. Note that in the MFM method or FM method assumed here, the timing pulse is also included in the read data pulse RDP due to the recording method, and the timing pulse is also included in the next stage demodulation circuit 4.
0, only the data pulses are separated and demodulated.

That is, as shown in FIG. 5, the demodulation circuit 40 forms and outputs a discrimination wind pulse WP (see FIG. 6(C)) which is synchronized with the 1q phase of the -1: data pulse IIDP based on the above-mentioned data pulse IIDP. The oscillator 41 and a comparator 42 for discriminating and separating the data pulse from the read data pulse RDP are used to compare the formed and outputted wind pulse WP. Only the pulses satisfying the condition (here, the AND condition ft of these pulses) are discriminated and output as data pulses DP (see FIG. 6(d)). The data pulse DP demodulated in this way is taken into a processing device such as an electronic sieve via an interface (not shown).

In addition, in such a reproducing circuit, when high-density recording is performed on a recording medium such as the above-mentioned magnetic disk and this is continuously read out, waveform interference occurs due to a decrease in the resolution of the read signal R8, and as a result, A peak shift may occur in the read signal @R8 and an error may occur in the demodulated signal. In such a case, a waveform equalization circuit (consisting of a well-known transversal filter, etc.) 2 as shown in FIG. 7 is installed between the readout amplifier 20 and the peak detection circuit 30.
1 is also provided to pre-correct the peak shifts 1 to 1 of the continuous output signal R8.

[Problem that the invention seeks to solve]

Since all of the above-mentioned playback circuits were constructed using analog circuits, many adjustments were required when manufacturing them, and in order for them to operate stably in practical use, it was necessary to Various considerations were required to ensure stability over time and temperature.

In addition, when the waveform equalization circuit 21 is provided as shown in FIG. 7, its operation is performed according to the track position in order to correct the change in the resolution of the read signal due to the change in the track position of the magnetic disk, etc. Although it is desirable to change the parameters, it is difficult to do so with this waveform equalization circuit 21 constituted by the ablation circuit as described above.

Furthermore, a demodulation circuit 4 using the phase synchronized oscillator 41
0 cannot tolerate the above-mentioned peak shift when it occurs, so the margin for demodulation is naturally reduced and demodulation errors often occur.

[Means and effects for solving the problem] In the present invention, both or one of the peak detection circuit and the demodulation circuit described above is converted into a digital circuit, and the reproduction circuit is made adjustable, highly stable, and highly functional. Specifically, the digital peak detection circuit uses a readout signal converted into a digital signal by an A/D converter installed in the preceding stage (however, the center level of the two magnetic flux change point levels is set to "0" level). (expressed as positive or negative equivalent levels), and then differentiate and differentiate this, including correction for factors related to the resolution of the read signal, such as the track position of the magnetic disk, head selection, etc. A digital filter that equalizes the waveform and the sign of this filter output are monitored to detect the change point (positive → negative or corner → positive), and the zero-crossing point of the read signal is detected to correspond to the detected river fish. The digital demodulation circuit includes a zero-cross detection means (7) to detect the read data pulse as a pulse, and the digital demodulation circuit includes, for example, a counter for measuring the pulse interval of input read data pulses at any time, and a counter for measuring the pulse interval of these pulse intervals. A hanging means for appropriately quantizing the measured data by converting the number of bits based on a predetermined threshold, and directly converting the quantized data into desired read data according to a predetermined logic. In addition, in the above-mentioned quantization, a storage means for temporarily storing the measurement data of the pulse interval for, for example, two consecutive pulse intervals, and a logic means for converting the measurement data of the same pulse interval are configured. For example, a threshold value correction means is provided for correcting the threshold value so as to absorb the aforementioned peak shift based on the data of interest and the measured data before and after it stored in the storage means, and the method is sequentially based on the corrected threshold value. If quantization is performed using the above logic means, the read data obtained from the logic means will also be high quality data with few errors.

Incidentally, since the peak shift occurs according to a certain law, the information set in the 1N value correction stage to absorb this can also be appropriately set according to this law.

[Effects of the Invention] As described above, in the reproducing circuit according to the present invention, by converting at least one of the peak detection circuit and the demodulation circuit into a digital circuit in the above-mentioned manner, ○ adjustment is unnecessary (at least 6), the stability is also greatly improved.

0 In particular, when the peak detection circuit is implemented as a digital circuit, variable setting of operating parameters related to waveform equalization becomes easy, and suitable waveform equalization can be realized according to the resolution of the read signal at any time.

0 In particular, when the demodulation circuit is made into a digital circuit, the allowable amount of peak shift caused by waveform interference becomes large, and reproduction errors are less likely to occur.

o It becomes easy to convert to LSI, which in turn makes it easy to downsize the device and produce it by hanging it from the ceiling.

You can obtain many excellent effects such as.

(Embodiment) Fig. 1 shows an embodiment of the reproduction circuit according to the present invention.Here, for example, the data transfer rate is 5 Hbit/Sec.
A case in which the reproducing circuit of the present invention is applied to an MFM type magnetic disk storage device will be described. The configuration and operation of this circuit will be described in detail below.

As mentioned above, in this embodiment circuit, the readout signal R8 appropriately amplified by the readout amplifier 20 is converted from analog to digital by the A/D converter 50 as required, and is sent to the digital peak detection circuit as a digital readout signal DR3. 60 is inputted sequentially. By the way, this analog/
The sampling frequency during digital conversion, that is, the frequency of the sampling clock CK shown in FIG.
Suppose that 0 M I-I Z. Further, it is assumed that the digital read signal DR8 obtained by analog/digital conversion is expressed as a digital value corresponding to each positive or negative equivalent level, with the center level of the two magnetic flux change point levels being the rOJ level.

Now, the digital peak detection circuit 60 to which such digital readout signal DR8 is input is broadly composed of digital delay circuits 61a and 61b.

It is composed of an acyclic digital filter made up of 61C9 n units 62a, 62b, 62c, and 62d and an adder 64, and a zero-cross detection circuit made up of a code memory 65 and a code comparator 66. Among these, the digital filter configures a shift register that transfers and locks the clock CK by the digital delay circuits 618, 61b and 61C, and extracts data at each transfer stage of the shift register as shown in the figure. In addition to one input of each of the multipliers 62a, 62b, 62c, and 62d, these multipliers multiply the same extracted data by the coefficient data added to the other input, so that the readout signal R8 is The well-known differentiation and waveform equalization operations are accomplished digitally. The outputs of these multipliers are added at any time by the adder f3 64.
), and is reproduced and output as a digital read signal DR8' corresponding to a signal with waveform interference and the like of the read signal R8 reduced. The operating parameters of the digital filter are the multipliers 62a, 62b, 62G.
The coefficient data added to each other input of 62d and 62d is
As mentioned above, the coefficient data is given as a value that differentiates and equalizes the waveform of the read signal R8 (more precisely, this digitized signal DR8), but here, the coefficient data is further calculated based on changes in the track position of the magnetic disk. It is assumed that the resolution is variably set through the filter control 211 circuit 63 in accordance with the resolution of the read signal R8, which changes depending on the relative positional relationship between the magnetic storage device and the magnetic head, such as switching of the head used. Information regarding the track position of the magnetic disk and information regarding the used head are supplied from the disk device to the filter control circuit 63 as filter control information FCC at any time.

On the other hand, the zero cross detection circuit receives the digital read signal DR8' outputted through this digital filter.
The code memory 65 and code comparator 66
5, the sign of the received signal is successively compared with the sign of the received signal (-) one sample cycle before, and the read data pulse RDP described above is output. In other words, the code memory 65 has the same I'l as the clock CK.
lL is a memory that stores the code data of the signal DR3' at any time while updating its storage contents every cycle of the signal.
I successively compare the output code data of the delayed code memory 65 and the occasional code data of the directly received signal DR8', and each time these codes differ, that is, each time the digital readout signal DR8' crosses zero. A pulse that becomes active at that point, that is, a read data pulse RDP is output.

The output data pulse RDP thus formed is then applied to a digital demodulation circuit 70 (not shown in FIG. 1).

The digital demodulation circuit 70 includes a start/stop control circuit 71 . A pulse interval measurement circuit for the read data pulse RDP consisting of counters 72a, 72b and data selector 73, and ledges 74a, 74b, I21iii
It has a m-digitization circuit for the pulse interval measurement data, which is composed of a memory 75J3 and a digital comparator 76, and a modulation logic circuit 77 for logically converting the quantized data as required to obtain MFM demodulated data. is composed of

Now, in this digital demodulation circuit 70, the two counters 72a and 72b sequentially perform the 81 count using the aforementioned clock GK as an input signal, and also have a start/stop control to which the read data pulse RDP is applied. Based on this read data pulse RDP, the output circuit 71 starts the number 31 of these J counters 72a and 72b through control signals SS1 and SS2, respectively, each time the pulse RDP becomes active.
Clear start) and Takazu stop can be switched alternately.
As a result, each time the counters 72a and 72b stop, measurement data (count data) regarding the pulse interval of the read data pulse RDP is stored in the counters 72a and 72b with the time resolution of the clock GK. They will be registered alternately. Incidentally, if these counters 72a and 72b are 5b1 counters, since the frequency of the clock CK is 50 MHz, it is possible to measure one pulse interval up to 52Q n5ec with a resolution of 2Q n5cc. The start/stop control circuit 71 also controls these two
The data selection operation of the data selector 73 is controlled through the control signal SL so that the measurement data (count data) of the two counters 72a and 72b on which the argument is stopped is selectively outputted via the data selector 73. Therefore, the data selector 73 sequentially outputs the measured data regarding the pulse interval of the read data pulse RDP in synchronization with the pulse RDP.

The pulse interval measurement data of these read data pulses RDP is then applied to the suspension circuit, and its latch timing is controlled by the control signal LH applied from the start/stop control circuit 71 so as to be synchronized with the read data pulses RDP. are sequentially latched into latches 74a and 74b.

That is, at a certain point in time, these latches 74a
In and 74b, measurement data regarding the pulse interval between adjacent pulses for each of the three consecutive pulses is latched. Therefore, as shown in FIG. 1, data between the first latch 74a and the second wrap 74b, that is, the first latch 74a
When the data NT is the current data, when the data selector 73 selects the data and the latches 74a and 74b complete the latching of the corresponding data, the data before and after the data become the data FT and NT, respectively. Second as data BC
latch 74b and data selector 73, respectively. Each of these data NT, FT, and BG is collectively added as address data to a threshold memory 75 consisting of, for example, a ROM, and data NT, which is data of particular interest, is separately added to a digital comparator 76. . Here, this digital comparison j! ! '＋
Reference numeral 76 is for fi-quantizing the data NT, which is a pulse interval of 5 bits plus the data on the il side, into 2-bit data based on a comparison of the threshold data BL read out from the threshold memory 75. can be,
Here, it is assumed that the correspondence between the 2-bit quantized data PD and the 5bth pulse interval measurement data is determined in the manner shown in the following table, for example.

Incidentally, if there is no peak shift in the read signal R3, the pulse interval J1 measurement data is also limited to several values as shown in the following table.

Further, the threshold value memory 75 stores the IN threshold value data that enables the digital comparator 76 to perform such quantization.
Each data NT, FT and B used as the above address data
This memory stores a plurality of data in a dimple shape corresponding to the contents of C, and operates to uniquely read out the corresponding threshold data B each time each of these data NT, FT, and BC is added. Incidentally, this threshold value is based on the data NT of interest regarding the pulse interval and the data F before and after it.
It is pre-registered as a value obtained by correcting the peak shift amount, which can be estimated from T and 8G based on a predetermined law regarding the peak shift of the read signal R8.

Therefore, by performing the above-mentioned quantization by the digital comparator 76, the comparator 76 outputs the signal that a peak shift has occurred in the read signal R8, even if no peak shift has occurred in the read signal R8. Even in the case where the modulation method is used, appropriate 2-bit suspension data corresponding to several pulse intervals that are preliminarily limited in the modulation method can be obtained. Incidentally, as in this embodiment, when the digital salt circuit 70 is used in conjunction with the digital peak detection circuit 6o described above, the threshold candy data B pre-recorded in the threshold value register 75 is However, the value is set in consideration of the waveform equalization by the digital peak detection circuit 60.

In this way, the 2-bit pulse interval data P
Finally, D is added to the demodulation logic circuit 77, where it is logically converted into a data string in a required format according to the modulation method (MFM method in this example). An example of the logic conversion operation by the demodulation logic circuit 77 is shown in FIG. 2 with a state transition diagram. In FIG. 2, it is assumed that the label attached to each path indicates "input/output". Also, input without a corresponding path (for example, input of '10' for status '0')
If so, it is judged as an error and the demodulation operation is stopped.

By performing such logical conversion (1), the quantized 2b;t pulse interval data PD can be properly reproduced as data RD in the required form in the MF and M systems.

If the reproducing circuit of this embodiment is used as described above, it is easy to variably set the operating parameters of the digital filter for waveform equalization of the readout signal in the digital peak detection circuit 60. In addition, the digital demodulation circuit 70 has a large tolerance for peak shifts caused by the waveform f interference of the readout signal (more than 50% compared to conventional reproduction circuits). It becomes possible to easily realize reliable data reproduction in which reproduction errors are unlikely to occur.

Also, since such a circuit requires no adjustment whatsoever,
This is particularly effective when producing m circuits with the same performance.

In the above embodiment, the digital filter used in the digital peak detection circuit 60 is of the acyclic type, but the digital filter may have any configuration as long as it has the above-mentioned waveform equalization characteristics and differential characteristics. It may be something.

Further, in the same embodiment, when the threshold value memory 75 used in the digital demodulation circuit 70 does not read out the threshold value data BL, the threshold value memory 75 stores the data NT of interest and the data FT before and after it.
and BC (that is, they are used as address data), but if there are at least two data, the data NT of interest and the data FT before it, the peak shift maximum for the data of interest NT is The information regarding the address is basically the same, and these two data may be used as reference data (address data).

Furthermore, in the same embodiment, the same clock CK is used as the clock for zumbling the read signal R8 and the clock used for measuring the pulse interval of the read data pulse RDP, but these clocks are different. Of course it's fine. In short, the clock used for zumbling the read signal R8 needs only to have a frequency that is at least twice the highest recording frequency of the same signal in the magnetic storage device, and the pulse interval of the read data pulse RDP. The clock used for measurement may be any clock that can measure this pulse interval four times with sufficient time resolution to correct the peak shift. Incidentally, this latter condition is also satisfied if the clock has a frequency that is twice or more than the maximum recording frequency.

Incidentally, in the same embodiment, the digital peak detection circuit 60 and the digital demodulation circuit 70 are arranged in parallel to constitute the reproduction circuit, but the digital peak detection circuit 60 and the digital demodulation circuit 70 are Even if it is used alone in the conventional circuit shown in FIG. 5 or FIG. 7, the corresponding effects described above can be obtained. For example, FIG. 3 shows a configuration in which only the peak detection circuit 30 of the conventional reproduction circuit shown in FIG. 5 is replaced with the digital peak detection circuit 60, and FIG. A configuration is shown in which only the demodulation circuit 40 of the conventional reproducing circuit shown in the figure is replaced with the digital demodulation circuit 70 described above. In these reproducing circuits, each of the digitizing circuits has the corresponding effects described above, and the reproducing circuit as a whole has a lower reproducing behavior when compared to the conventional circuit shown in FIG. 5 or 7. It is assumed that it is stable within -1 minute.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a reproduction circuit according to the present invention, and FIG. FIGS. 3 and 4 are block diagrams showing other embodiments of the reproducing circuit according to the present invention, FIG. 5 is a block diagram showing an example of a conventional reproducing circuit, and FIG. 6 is a block diagram showing an example of the conventional reproducing circuit. FIG. 5 is a timing chart showing an example of the operation of the circuit shown in FIG. 5, and FIG. 7 is a block diagram showing another example of the conventional reproducing circuit. 10... Reproduction head, 20... Read amplifier, 21
... Waveform equalization circuit, 30 ... Peak detection circuit, 40
... Demodulation circuit, 41 ... Phase synchronized oscillator, 42 ...
- Comparator, 50... A/D converter, 60... Digital peak detection circuit, 61a to 61G... Digital delay circuit 62a to 62d... Multiplier, 63... Filter control ti11 circuit , 64... β adder, 65... 7
No. 1 memory, 66...Sign comparison: 70...Digital demodulation circuit, 71...Start/stop system t
21] Circuit, 72a, 72b... force f kunta, 73.
...Data collector, 74 a, 7/l b-y tube,
75 value between t-1, J, 76...digital comparator,
77...11) ;! 'i logic circuit.

Claims (2)

[Claims] (1) Analog/digital conversion of a signal read from a magnetic storage device such as a magnetic disk through a magnetic head with a sampling period that is more than twice the maximum recording frequency of the same signal to the magnetic storage device. a converter, and by sequentially shifting the digitally converted data in synchronization with the sampling period, multiplying each data in the shifting process by a predetermined coefficient separately, and calculating the sum of these multiplication results at any time. , a digital filter that performs digital differentiation and waveform equalization on the read signal, and a digital filter that detects zero-crossing corresponding points of the waveform-equalized data and becomes active in response to the detected zero-crossing corresponding points. A reproducing circuit for a magnetic storage device, comprising: a zero-cross detector that outputs a read data pulse; and a demodulator that separates and extracts actual data according to the modulation method based on the read data pulse. (2) The predetermined coefficient to be multiplied is variably set according to the resolution of the signal read through the magnetic head, which changes depending on the relative positional relationship between the magnetic storage device and the magnetic head. A reproducing circuit for a magnetic storage device according to item (1).