JPS62140512A - Driving circuit for mosfet - Google Patents
Driving circuit for mosfetInfo
- Publication number
- JPS62140512A JPS62140512A JP28041885A JP28041885A JPS62140512A JP S62140512 A JPS62140512 A JP S62140512A JP 28041885 A JP28041885 A JP 28041885A JP 28041885 A JP28041885 A JP 28041885A JP S62140512 A JPS62140512 A JP S62140512A
- Authority
- JP
- Japan
- Prior art keywords
- mosfet
- transistor
- drive
- transformer
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004804 winding Methods 0.000 claims abstract description 24
- 238000010586 diagram Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/689—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit
- H03K17/691—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit using transformer coupling
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electronic Switches (AREA)
- Dc-Dc Converters (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、ＭＯＳＦＥＴの駆動回路に関し、更に詳しく
は、スイッチング電源に使用されるＭＯＳＦＥＴ に
おいて、オフ・ドライブ特性を改善することのできる駆
動回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a drive circuit for a MOSFET, and more particularly, to a drive circuit that can improve off-drive characteristics in a MOSFET used in a switching power supply. It is something.
（従来の技術）
第３図は、スイッチング電源におけるスイッチングトラ
ンジスタと、このトランジスタの駆動回路の接続概念図
である。この図において、■ｉは直流電圧源、では−次
巻線Ｉ’ｌｌ ＋二次巻線ｎ２を有したトランス、Ｑは
一次巻線０１に直流電圧Ｖｉｎをスイ。(Prior Art) FIG. 3 is a conceptual diagram of a connection between a switching transistor in a switching power supply and a drive circuit for this transistor. In this figure, ■i is a DC voltage source, a transformer having a -order winding I'll + a secondary winding n2, and Q is a transformer having a DC voltage Vin to the primary winding 01.
チングして（オン、オフして）与えるスイッチングトラ
ンジスタで、最近はこれＫ ＭＯＳＦＥＴ が使用さ
れつつある。ＤＲはこのスイッチングトランジスタＱ１
の駆動回路で、トランジスタＱ１をターンオン、ターン
オフするためのパルス１福信号を出力する。トランスＴ
の二次巻線ｎ２に生ずる交ａｔ圧の大きさは、トランジ
スタＱ１０オン、オフ時間に対応するので、パルス１福
信号のパルス幅を調整スることＫよって、二次巻線出力
を制御する。A switching transistor that provides power by switching on and off, and recently K MOSFET has been used. DR is this switching transistor Q1
The drive circuit outputs a pulse 1 signal for turning on and off the transistor Q1. transformer T
Since the magnitude of the AC pressure generated in the secondary winding n2 corresponds to the on/off time of the transistor Q10, the secondary winding output is controlled by adjusting the pulse width of the pulse 1 signal. .
第４図は、第３図において、スイッチングトランジスタ
Ｑ１としてＭＯＳＦＥＴ を用いた場合における従来の
駆動回路の接続図、第５図はその動作波形図である。FIG. 4 is a connection diagram of a conventional drive circuit when a MOSFET is used as the switching transistor Q1 in FIG. 3, and FIG. 5 is an operating waveform diagram thereof.
トランジスタＱ、のベースには、第５図（ａ）に示すよ
うなパルス幅信号が印加されており、トランジスタＱ２
＃−ｉ、これＫよって、オン、オフし、駆動トランスＴ
２の一次巻線Ｎ１に、オン状態において、（ｂ）に示す
ような電流ｉを流す。トランジスタＱ２と一次巻線Ｎに
は、並列に巻線Ｎ３とダイオードＤ１が接続されており
、オフ状！！ＩＩにおいて、巻Ｉ！ＩＮ３に（ｄｌに示
すような電流ｉ３が流れる。二次巻線Ｎ２に流れる電流
１２は、抵抗Ｒ１を介してＭＯＳＦＥＴ Ｑｌのゲート
に印加されており、（Ｃ）に示すように、はじめに振幅
ＩＧＩの電流１２を抵抗Ｒ１を介して流しＭＯＳＦＥＴ
Ｑｌをターンオンし１次に振＠ ＩＯ２の電流を逆方
向に流して、ターンオフさせている。この駆動回路にお
いては、オン時のドライブ特性は、抵抗Ｒ１で決定され
、また、オフ時のドライブ特性は、抵抗Ｒ１と、駆動ト
ランスＴ２の主インダクタンスで決定される。A pulse width signal as shown in FIG. 5(a) is applied to the base of the transistor Q2.
#-i, this K turns on and off, driving transformer T
In the on state, a current i as shown in (b) is passed through the primary winding N1 of No. 2. A winding N3 and a diode D1 are connected in parallel to the transistor Q2 and the primary winding N, and are in an OFF state! ! In II, Volume I! A current i3 as shown in (dl) flows through IN3. A current 12 flowing in the secondary winding N2 is applied to the gate of MOSFET Ql via a resistor R1, and as shown in (C), the amplitude IGI initially A current 12 is passed through the resistor R1 and the MOSFET
Ql is turned on and the primary current @ IO2 flows in the opposite direction to turn it off. In this drive circuit, the on-state drive characteristics are determined by the resistor R1, and the off-state drive characteristics are determined by the resistor R1 and the main inductance of the drive transformer T2.
（発明が解決しようとする問題点） 前記したような従来のＭＯＳＦＥＴの駆動回路は。(Problem to be solved by the invention) The conventional MOSFET drive circuit as described above is as follows.
オフ時のドライブ特性が駆動トランスＴ２の主インダク
タンスで決まるため１次のような問題点がある。Since the drive characteristic when off is determined by the main inductance of the drive transformer T2, there is a first-order problem.
（ａ） 高速スイッチングを実現するためには、主イ
ンダクタンスの値を小さくしなくてはならず、と、の場
合、無効電力が多くなり、１！力損失、ノイズ抑制上好
ましくない。(a) In order to achieve high-speed switching, the value of the main inductance must be reduced, and in the case of , the reactive power increases and 1! This is unfavorable in terms of power loss and noise suppression.
ら） オフドライブ特性がパルス幅信号のパルス幅に依
存して変化する。) The off-drive characteristics change depending on the pulse width of the pulse width signal.
（Ｃ） 主インダクタンスが設計要因に入り、バラツ
キ管理が難かしい。(C) The main inductance is a design factor, making it difficult to manage variations.
本発明は、これらの問題点に鑑みてなされたもので、そ
の目的社、オフ時のドライブ特性を改善し、簡単な構成
で低電力損失のＭＯＳＦＥＴ 駆動回路を実現しよう
とするものである。The present invention has been made in view of these problems, and its purpose is to improve the off-state drive characteristics and realize a MOSFET drive circuit with a simple configuration and low power loss.
（問題点を解決するための手段）
前記した問題点を解決する本発明は１Ｍ０８ＦＥＴのゲ
ートにゲート電流を与え当該ＭＯ８ＦＥＴ をオン。(Means for Solving the Problems) The present invention, which solves the above problems, applies a gate current to the gate of the 1M08FET to turn on the MO8FET.
オフさせる駆動回路において、前記ＭＯ８ＦＥＴのゲー
トと＝沖襄ミネーｉ間に抵抗を介して接続したトランジ
スタと、−次巻線にパルス幅信号が印加される駆動トラ
ンスと、この駆動トランスの二次巻線に得られる信号を
ダイオード及び前記抵抗を介して前記ＭＯ８ＦＥＴ
のゲートに与える回路と、前記駆動トランスの二次巻線
に得られる信号を前記トランジスタのベースに与える抵
抗とを設けたことを特徴とする。The drive circuit to be turned off includes a transistor connected via a resistor between the gate of the MO8FET and the Okisho Mine, a drive transformer to which a pulse width signal is applied to the negative winding, and a secondary winding of this drive transformer. The signal obtained on the line is passed through the diode and the resistor to the MO8FET.
and a resistor for applying a signal obtained to the secondary winding of the drive transformer to the base of the transistor.
（実施例） 第１図は１本発明駆動回路の一実施例の接続図である。(Example) FIG. 1 is a connection diagram of one embodiment of the driving circuit of the present invention.
この実施例では、スイッチング電源に用いられている場
合を示す。図において、Ｑｌは直流電圧Ｗｉｎをオン、
オフしてトランスＴの一次巻線ｎ１に与えるＭＯＳＦＥ
Ｔ 、 Ｔ２は駆動トランスでその一次巻線Ｎ１には、
パルス幅信号が与えられる。〜はダイオード、Ｒ１は抵
抗で、二次巻＋９ＪＮ２の一端とＭＯ８Ｆ’ＥＴ Ｑ
ｌのゲート間に直列に接続されている。This embodiment shows a case where the device is used in a switching power supply. In the figure, Ql turns on the DC voltage Win,
The MOSFE is turned off and applied to the primary winding n1 of the transformer T.
T and T2 are drive transformers, and their primary winding N1 is
A pulse width signal is provided. ~ is a diode, R1 is a resistor, and one end of the secondary winding +9JN2 and MO8F'ET Q
It is connected in series between the gates of l.
Ｑ２はトランジスタで、エミ、りは抵抗Ｒ１とダイオ続
されている。また、ベースは抵抗Ｒ２及び抵抗Ｒ３を介
してダイオードＤ２の両端にそれぞれ接続されている。Q2 is a transistor, and its emitter is diode-connected to resistor R1. Further, the base is connected to both ends of the diode D2 via a resistor R2 and a resistor R3, respectively.
このように構成した回路によれば、 ＭＯＳＦＥＴ Ｑ
ｌのオン時のドライブ特性は、抵抗Ｒ１締で決定されま
た。オフ時のドライブ特性は、抵抗Ｒ１と、トランジス
タＱのコレクタ・エミ、り間電圧ｖｃＰ、で決定される
。従って、 ＭＯ８ＦＥＴＱ１のターンオフ時は。According to the circuit configured in this way, MOSFET Q
The drive characteristic when R1 is on is determined by the tightening of resistor R1. The off-state drive characteristics are determined by the resistor R1 and the collector-to-emitter voltage vcP of the transistor Q. Therefore, when turning off MO8FETQ1.
抵抗Ｒ１を流れる逆ゲート電流が、トランジスタＱ２で
増幅されることとなり、駆動トランスＴ２からのエネル
ギ〒供給は僅かで、 ＭＯＳＦＥＴ Ｑｌは高速でター
ンオフする。The reverse gate current flowing through the resistor R1 is amplified by the transistor Q2, and the MOSFET Ql is turned off at a high speed with a small amount of energy supplied from the drive transformer T2.
第２図は、本発明駆動回路の他の例を示す接続図である
。この実施例では、トランジスタＱ２のベース・エミッ
タ間に抵抗Ｒ１３を接続するとともに。FIG. 2 is a connection diagram showing another example of the drive circuit of the present invention. In this embodiment, a resistor R13 is connected between the base and emitter of the transistor Q2.
エミ、りを抵抗Ｒ１□を介してＭＯＳＦＥＴ Ｑｌのゲ
ートに接続するようＫしたものである。The emitters and ri are connected to the gate of MOSFET Ql via a resistor R1□.
この実施例によれば１Ｍ０３ＦＥＴ Ｑｌのオン時の
ドなお、上記の各実施例ではＮチャンネルＭＯ８ＦＥＴ
を用いる場合を想定したものであるが、ＰチャンネルＭ
Ｏ８ＦｇＴ を用いてもよい。この場合、ダイオードＤ
２１ トランジスタＱ２の接続極性は逆となる。According to this embodiment, when 1M03FET Ql is turned on, in each of the above embodiments, N-channel MO8FET
This is based on the assumption that P channel M
O8FgT may also be used. In this case, diode D
21 The connection polarity of transistor Q2 is reversed.
（発明の効果）
以上説明したように１本発明、駆動回路は、ＭＯＳＦＥ
Ｔ のターンオフ時におけるドライブ特性が。(Effects of the Invention) As explained above, in the present invention, the drive circuit is a MOSFE
The drive characteristics at turn-off of T.
駆動トランスの主インダクタンスに大きく依存すること
がない。従って、本発明によれば、簡単な構成で、低電
力損失、かつ駆動信号のパルス幅にドライブ特性が影響
されないＭＯＳＦＥＴ の駆動回路が実現できる。There is no significant dependence on the main inductance of the drive transformer. Therefore, according to the present invention, it is possible to realize a MOSFET drive circuit with a simple configuration, low power loss, and whose drive characteristics are not affected by the pulse width of the drive signal.
第１図及び第２図は本発明駆動回路の一例を示す接続図
、第３図はスイッチング電源におけるスイッチングトラ
ンジスタの駆動回路の接続概念図、第４図は従来のＭＯ
ＳＦＥＴの駆動回路の接続図、第５図はその動作波形図
である。
Ｑｌ・・・ＭＯＳＦＥＴ 、 Ｑ２・・・トランジス
タ、Ｒ１，Ｒ２・・・抵抗、Ｄ２・・・ダイオード、Ｔ
２・・・駆動トランス。
代理人 弁理士 小 沢 信 助 ・・、（パ
、二、−・
第３図
第４図1 and 2 are connection diagrams showing an example of the drive circuit of the present invention, FIG. 3 is a conceptual connection diagram of a switching transistor drive circuit in a switching power supply, and FIG. 4 is a connection diagram of a conventional MO
The connection diagram of the SFET drive circuit, and FIG. 5 is its operating waveform diagram. Ql...MOSFET, Q2...transistor, R1, R2...resistance, D2...diode, T
2... Drive transformer. Agent Patent Attorney Shinsuke Ozawa... (Pa, 2, -) Figure 3 Figure 4
Claims (1)
ＥＴをオン、オフさせる駆動回路において、 前記ＭＯＳＦＥＴのゲートとソース間に抵抗を介して接
続したトランジスタと、一次巻線にパルス幅信号が印加
される駆動トランスと、この駆動トランスの二次巻線に
得られる信号をダイオード及び前記抵抗を介して前記Ｍ
ＯＳＦＥＴのゲートに与える回路と、前記駆動トランス
の二次巻線に得られる信号を前記トランジスタのベース
に与える抵抗とを設けたことを特徴とするＭＯＳＦＥＴ
の駆動回路。[Claims] Applying a gate current to the gate of a MOSFET
A drive circuit that turns on and off the ET includes a transistor connected between the gate and source of the MOSFET via a resistor, a drive transformer to which a pulse width signal is applied to the primary winding, and a secondary winding of this drive transformer. The signal obtained at M is passed through the diode and the resistor to the M
A MOSFET characterized in that it is provided with a circuit that supplies the gate of the OSFET, and a resistor that supplies the signal obtained from the secondary winding of the drive transformer to the base of the transistor.
drive circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28041885A JPS62140512A (en) | 1985-12-13 | 1985-12-13 | Driving circuit for mosfet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28041885A JPS62140512A (en) | 1985-12-13 | 1985-12-13 | Driving circuit for mosfet |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62140512A true JPS62140512A (en) | 1987-06-24 |
Family
ID=17624767
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28041885A Pending JPS62140512A (en) | 1985-12-13 | 1985-12-13 | Driving circuit for mosfet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62140512A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63139421A (en) * | 1986-12-01 | 1988-06-11 | Fuji Electric Co Ltd | Gate driving circuit for mosfet |
| JPH01147687U (en) * | 1988-03-30 | 1989-10-12 | ||
| JPH02118330U (en) * | 1989-03-11 | 1990-09-21 | ||
| US5264966A (en) * | 1990-12-18 | 1993-11-23 | Canon Kabushiki Kaisha | Lens barrel |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57206944A (en) * | 1981-06-15 | 1982-12-18 | Matsushita Electric Works Ltd | Driving circuit for switching element |
-
1985
- 1985-12-13 JP JP28041885A patent/JPS62140512A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57206944A (en) * | 1981-06-15 | 1982-12-18 | Matsushita Electric Works Ltd | Driving circuit for switching element |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63139421A (en) * | 1986-12-01 | 1988-06-11 | Fuji Electric Co Ltd | Gate driving circuit for mosfet |
| JPH01147687U (en) * | 1988-03-30 | 1989-10-12 | ||
| JPH02118330U (en) * | 1989-03-11 | 1990-09-21 | ||
| US5264966A (en) * | 1990-12-18 | 1993-11-23 | Canon Kabushiki Kaisha | Lens barrel |
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