JPS62139354A - Double heterojunction bipolar transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent gain reduction under low-bias conditions by a method wherein a collector layer is of a two-layer laminate built of a collector first layer of high carrier concentration and a collector second layer of low carrier concentration and the collector layer in contact with a base layer is higher in carrier concentration than the other collector layer in contact with the former. CONSTITUTION:Grown on an InP substrate (n-type Sn-doped) 1 by the liquid phase growth method are an Sn-doped InP layer (collector second layer with a carrier concentration of 1X10<16>cm<-3>) 2, Sn-doped n-type InP layer (collector first layer with a carrier concentration of 1X10<18>cm<-3>) 3, Zn-doped p-type GaAsP layer (base layer with a carrier concentration of 1X10<18>cm<-3>) 4, and Sn-doped n-type InP layer (emitter layer with a carrier concentration of 5X10<17>cm<-3>) 5. On the grown substrate, an SiO2 film is formed, a resist etching mask is formed, and etching is accomplished for the removal of the resist. Diffusion of Zn is accomplished for the construction of a graft base structure. Finally, an emitter elector and collector electrode are built.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a double heterojunction bipolar transistor that does not reduce gain at low bias during transistor operation, and a method for manufacturing the same.

[Conventional technology]

FIG. 7 shows a structural diagram of a heterojunction bipolar transistor. In the figure, ■ is a collector, 2 is a base, 3 is an emitter, 4 is an insulating dielectric material of each electrode, 5 is an emitter electrode, 6 is a base electrode, and 7 is a collector electrode. In Fig. 8, the emitter is InP (n type, N =
s x 1o17Cx') based on InGaAsP (
13, un composition, P type, p, = 3 x 1017
c'rrr5), collector is InPCn type, N=3X1
The figure shows an energy band structure diagram of a double heterojunction bipolar transistor when fabricated with An energy step is created that prevents the passage of electrons.For this reason, in the transistor characteristics, as shown in FIG. 9, the current gain decreases when the collector-emitter voltage is low and the bias is low.

As a way to prevent this decrease in current gain at low bias (
1) Method of inserting a thin multilayer film between the emitter and base and base and collector in the GaAs/AIGαAs system (Reference J, App1. Phys, 54C11>,
1983°S, L, Stb, et, al,) See Figure 10, (2JP-InGaAs (7) Emitter and n-
A method of inserting a thin InGaAsP layer between InP collector layers (Reference Appl, Phys.

Lgtt, 47(1), 1985. P2B, LoM
, StL, et, al, ), see Figure 11, etc. have been reported.

However, method 1) requires the use of the MBE method for growth and cannot be applied to the commonly used liquid phase growth method. (2)
This method had drawbacks such as effectively expanding the base region and reducing the current amplification factor.

[Purpose of the invention]

An object of the present invention is to provide a double heterojunction bipolar transistor based on the energy step that exists between the base and the collector in the double heterojunction bipolar transistor (without a decrease in gain at low bias) and a method for manufacturing the same.

The main feature of the present invention is that the collector layer in a double heterojunction bipolar transistor is composed of a first collector layer with a high carrier concentration of less than several hundred) and a second collector layer with a low carrier concentration, as shown in FIG. Features.

In the conventional structure, the collector layer has a semiconductor/layer structure with a low carrier concentration, but in the present invention, the collector layer has a semiconductor/layer structure with a high carrier concentration.
The difference is that it consists of a two-layer structure consisting of a layer and a second layer with a low carrier concentration.

The present invention further provides a structure in which the collector portion adjacent to the emitter of the double heterojunction bipolar transistor has a composition having a smaller energy gap than the collector composition following this portion. That is,
The difference is that the collector layer has a two-layer structure as described above, compared to the conventional single-layer structure. To put this specifically,
−1rLP substrate with LuInP or tylnGα
AsP (energy gap Eg2) 0) D L/
collector second layer, n, −1nGctAsh (energy gap Eg1. Eg+ <A;', !72), collector first layer of P-1nGcLAsP (energy gap E, q3. Egs < Eg2), n-I
In this method, nP emitter layers are sequentially grown.

In the present invention, the reason why the gain does not decrease at low bias can be qualitatively explained as follows.

In other words, as shown in Figure 8, at low bias, the energy spike in the conduction band between the base and collector becomes a large barrier to electrons passing through the base, preventing the electrons from reaching the collector, resulting in a decrease in gain. However, as the bias is increased, the influence of the energy spike becomes less noticeable due to the potential gradient between the base and the collector, and no decrease in gain occurs.

[Example 1] An example of the manufacturing procedure of the present invention is shown in FIGS. 1 to 4.

CVD or MBE methods may be used, or other CaAs/A
j! The same effect can be expected even if a crystal system such as GaAs is used.

InP substrate (n-type Sn doped N = 2 x 1018
cm-5) ; Sn-doped n-type InP layer on top (carrier concentration I x 1016 cm '5 μm thick collector second layer); 2. Sn-doped n-type rnP layer (carrier concentration I x 1018 cm-', 0.05 μm thick collector first layer); 3. Zn-doped P-type 1nGaAsP layer (1,3
μm composition, carrier concentration lx l Q18cm-' 0
．． 2 p m thickness, emitter); 4.5 n) - n-type In
P layer (carrier concentration 5XIO"Cm-' 10.5μm
Thickness, emitter layer); 5 is grown by liquid phase growth method. See Figure 1.

A SiO□ film is deposited on this growth substrate by a 1600A sputtering method, a resist etching mask is formed by ordinary photolithography, and the SiO2 is etched by a photolithographic active ion etching method (RTE method) to remove the resist.

Next, 230 mg of Zn3P and the substrate were placed in a quartz tube with a diameter of 10 mm (7), and the quartz tube was evacuated to a length of about 10 mm.
Prepare a 0 mm vacuum ampoule. Ampoule at 450℃
The sample was left in an electric furnace for about 1 hour to diffuse Zn. This forms a graft base structure, see Figure 2.

Note that instead of using the graft base structure by Zn diffusion, the base surface may be exposed by etching and the base electrode may be formed there.

After removing the 5in2 film with hydrofluoric acid, a S j 02 film was applied again by sputtering, a mask was formed using photolithography, and then S r 02 was etched by RIE, and after the resist was removed, 1% Br was added using SiO2 as a mask.
A SiN film is deposited on the entire surface using a methyl alcohol solution using the emitter plasma CVD method, a through-hole mask for forming an emitter electrode is formed using photolithography technology, and RI is performed.
After etching the SiN film using the E method, AuGaNi is deposited and an emitter electrode is formed using the lift-off method. In the same way as the emitter electrode was formed, a through hole was made for the base electrode using photolithography and RIE, and the AuZ
It is formed by a lift-off method after nNi vapor deposition. The collector electrode is formed by polishing the back surface with 10% Br methyl alcohol until the substrate thickness becomes about 100 μm, and then depositing 1 g of AuGaN. Finally, in a hydrogen atmosphere at 425℃20See
Heat treatment is performed to establish ohmic contact, see Figure 4.

As shown in Figure 4, the collector layer consists of a first collector layer with a high carrier concentration and a second collector layer with a low carrier concentration, and due to the presence of the first collector layer with a high carrier concentration, the energy step width of the conduction band increases as shown in Figure 8. Compared to the conventional -1 collector structure, the carrier concentration is higher as shown in Figure 5, that is, (1XIO/1'X10) = O
, becomes narrower by one time, and electrons from the base can pass through this due to the tunnel effect. This eliminates the decrease in current gain at low bias that was observed in transistors with conventional structures.

[Example 2] The manufacturing procedure is the same as that of the example except that during crystal growth, an Sn-doped n-type 1nGaAsP layer (1,5, crm composition, carrier concentration lXl0 cm, 0.058°C thickness) is grown as the collector first layer. Do the same as step 1. As shown in Figure 6, due to the existence of the first collector layer with a smaller energy gap than the second collector layer, the energy step of the conduction band cannot prevent the passage of electrons, and at the low bias observed in the conventional structure, The current amplification factor no longer decreases.

〔Effect of the invention〕

As explained above, in a double heterojunction bipolar transistor in which the collector layer is composed of a thin film collector first layer with a high carrier concentration and a collector second layer with a low carrier concentration, the presence of the collector first layer with a high carrier concentration allows the base collector to Based on the heterojunction between (because the energy step width of the conduction band becomes very narrow and the carriers from the base can pass through the energy step with the Teunel effect, it consists of a conventional low carrier concentration single-layer collector) This has the advantage that the reduction in current gain at low bias caused by the conduction band energy step that existed in the transistor characteristics of the double heterojunction bipolar transistor is eliminated.

Furthermore, as mentioned above, due to the presence of the collector first layer which has a smaller energy gap than the collector second layer, the carriers passing through the base lose energy at the boundary of the subsequent collector second layer due to the energy gradient in the first layer. to have enough energy to cross the step,
This has the advantage that the decrease in current gain at low bias is eliminated.

[Brief explanation of drawings]

1 to 4 show the manufacturing process of the present invention. FIG. 5 shows an energy band diagram between the base and collector in the structure of the present invention, and FIG. 6 shows an energy band diagram between the base and collector in another structure of the present invention. FIG. 7 shows a structural diagram of a heterojunction bipolar transistor. FIG. 8 shows an energy band diagram of a base-collector heterojunction. FIG. 9 shows the common emitter transistor characteristics of a double heterojunction bipolar transistor with a conventional structure. 1101m shows a structure in which a thin multilayer film is inserted between the emitter and base and between the base and collector to improve characteristics. FIG. 11 shows a structure in which a thin nlnGaAsP layer is inserted between the P-1nGaAs base layer and the n-InP collector layer to improve the characteristics. Patent Applicant Nippon Telegraph and Telephone Corporation Agent Patent Attorney Hisa Gobe Tamamushi (2 others) Figure 2 Figure 3 Figure 4 Figure 1n Figure 8 Figure 9

Claims (3)

[Claims] (1) Double heterojunction bipolar consisting of a first conductivity type emitter layer, a second conductivity type base layer having a composition with at least a smaller energy gap than the emitter, and a first conductivity type collector layer having at least a larger energy gap than the base layer. A double heterojunction bipolar transistor in which the carrier concentration in the collector layer adjacent to the base layer is higher than the carrier concentration in the collector region following this part. (2) A double heterojunction consisting of a first conductivity type emitter layer, a second conductivity type base layer having a composition with at least a smaller energy gap than the emitter layer, and a first conductivity type collector layer having at least a larger energy gap than the base layer. A double heterojunction bipolar transistor in which a first conductivity type semiconductor layer having a composition having a smaller energy gap than a collector region following this portion is attached to a collector portion adjacent to a base layer. (3) Sequentially grow an n-InP second collector layer, an n-InP or n-InGaAsP first collector layer, a P-InGaAsP base layer, and an n-InP emitter layer on the n^+-InP substrate, and A step of making the first layer have a higher carrier concentration than the second layer, A step of thermally diffusing Zn to the base layer using a silicon nitride film or a silicon oxide film mask to form a graft base structure, An emitter and a base layer Using the silicon oxide film as a mask, etching to the bottom of the base layer forms a mesa, and forming a plasma CVD silicon nitride film on the entire surface as an insulating film.The emitter electrode and base electrode are formed on the front surface, and the collector electrode is formed on the back surface. A method for manufacturing a double heterojunction bipolar transistor, comprising the steps of: forming and heat-treating to form an ohmic contact.