[go: up one dir, main page]

JPS62133828A - Signal quality detection method - Google Patents

Signal quality detection method

Info

Publication number
JPS62133828A
JPS62133828A JP27386385A JP27386385A JPS62133828A JP S62133828 A JPS62133828 A JP S62133828A JP 27386385 A JP27386385 A JP 27386385A JP 27386385 A JP27386385 A JP 27386385A JP S62133828 A JPS62133828 A JP S62133828A
Authority
JP
Japan
Prior art keywords
signal
circuit
error
deterioration rate
signal quality
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP27386385A
Other languages
Japanese (ja)
Other versions
JPH0441853B2 (en
Inventor
Takashi Kako
尚 加來
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP27386385A priority Critical patent/JPS62133828A/en
Publication of JPS62133828A publication Critical patent/JPS62133828A/en
Publication of JPH0441853B2 publication Critical patent/JPH0441853B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Dc Digital Transmission (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

PURPOSE:To quicken the pull-in speed of a signal quality evaluation circuit and to evaluate the signal quality of a line even top a short training signal by using an eye deterioration rate based on a reception signal so as to setting the initial value of an integration circuit. CONSTITUTION:A reception signal is inputted to an equalization circuit 1, an equalization signal of phase and amplitude is fed to a decision circuit 2 and a decided result signal is outputted. Further, the equalization signal and the decided result signal are inputted to an adder circuit 3, an error signal corresponding to an error of the both is generated and fed to a calculation circuit 4. The circuit 4 calculates the eye deterioration rate when the impulse response method to the equalization circuit 1 to generate a prescribed initializing signal corresponding to the eye deterioration rate. The initializing signal is used to set the initial value of the integration circuit constituting the signal quality evaluation circuit 5. Thus, the quality evaluation signal in a form corresponding to the error signal is generated quickly.

Description

【発明の詳細な説明】 〔概要〕 受信信号を等化した信号と、この等化した信号を判定し
た判定信号との誤差に基づいて、信号品質の検出を行う
信号品質検出方式において、信号品質評価回路と、アイ
劣化率算出回路とを備え、このアイ劣化率算出回路によ
って算出したアイ劣化率に対応して、前記信号品質評価
回路を構成する積分回路の初期値を設定し、前記信号品
質評価回路によって検出した品質評価信号を出力するよ
うにしている。
[Detailed Description of the Invention] [Summary] In a signal quality detection method that detects signal quality based on the error between a signal obtained by equalizing a received signal and a judgment signal that judges this equalized signal, the signal quality An evaluation circuit and an eye deterioration rate calculation circuit are provided, and an initial value of an integrating circuit constituting the signal quality evaluation circuit is set in accordance with the eye deterioration rate calculated by the eye deterioration rate calculation circuit, and the signal quality is A quality evaluation signal detected by the evaluation circuit is output.

〔産業上の利用分野〕[Industrial application field]

本発明は、信号品質を検出する際に、引き込みを迅速に
行わせる信号品質検出方式に関するものである。
The present invention relates to a signal quality detection method that quickly performs pull-in when detecting signal quality.

〔従来の技術と発明が解決しようとする問題点〕従来、
データ伝送系の回線を通してモデムにより位相変調デー
タを受信し、等花器を通して位相と振幅との等化が行わ
れている。この等花器を含むモデムの回線品質を評価す
る場合、受信信号を等化した等化信号の誤差分を積分処
理して行うものがある(例えば特公昭58−54686
号)。
[Problems to be solved by conventional technology and invention] Conventionally,
Phase modulated data is received by a modem through a data transmission line, and the phase and amplitude are equalized through an equalizer. When evaluating the line quality of a modem that includes this type of flower vase, there is a method that performs integral processing on the error of the equalized signal obtained by equalizing the received signal (for example,
issue).

このような評価信号を出力するために、積分回路を用い
て積分処理という統計的な処理を行っていたのでは、例
えばファースト・ポーリング・モデムの場合のように、
トレーニング信号の持続時間が短いもの例えば数msな
いし数+msのものに対しては、SQD回路(信号品質
検出回路)による引き込みが十分に行われず、信号品質
を検出して評価し得ないという問題点があった。
In order to output such evaluation signals, statistical processing called integration processing was performed using an integrating circuit, as in the case of fast polling modems, for example.
The problem is that when the duration of the training signal is short, for example, several ms to several + ms, the SQD circuit (signal quality detection circuit) does not sufficiently capture the signal, making it impossible to detect and evaluate the signal quality. was there.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、前記問題点を解決するために、受信信号を等
化した等化信号とこの等化した信号を判定した判定信号
との誤差に基づいて算出したアイ劣化率を用いて、信号
品質評価回路を構成する積分回路の初期値を設定する構
成を採用することにより、信号品質評価回路の引き込み
速度を速くしてトレーニング信号の短いものに対しても
回線の信号品質を評価し得るようにしている。
In order to solve the above-mentioned problems, the present invention uses an eye deterioration rate calculated based on the error between an equalized signal obtained by equalizing a received signal and a judgment signal obtained by judging this equalized signal to improve signal quality. By adopting a configuration in which the initial value of the integrating circuit that constitutes the evaluation circuit is set, the acquisition speed of the signal quality evaluation circuit is increased and the signal quality of the line can be evaluated even for short training signals. ing.

第1図は本発明の原理的構成図を示す。図中、1は受信
信号の位相および振幅を等化する等化回路、2は判定回
路、3は加算回路、4はアイ劣化率算出回路、5はSQ
D (信号品質検出)評価回路を表す。
FIG. 1 shows a basic configuration diagram of the present invention. In the figure, 1 is an equalization circuit that equalizes the phase and amplitude of the received signal, 2 is a determination circuit, 3 is an addition circuit, 4 is an eye deterioration rate calculation circuit, and 5 is SQ
D (signal quality detection) represents the evaluation circuit.

第1図において、アイ劣化率算出回路4は、等化回路1
によって位相および振幅が等化された等化信号(誤差を
含んでいる)と、判定回路2によって判定された判定結
果信号(誤差を含んでいない)との差からなる誤差信号
から、後述するようにして算出したアイ劣化率に対応し
た初期化信号を生成するものである。この初期化信号は
、SQD評価回路5を構成する積分回路に対して初期値
を設定するものである。
In FIG. 1, the eye deterioration rate calculation circuit 4 includes the equalization circuit 1
As will be described later, an error signal consisting of the difference between the equalized signal (contains an error) whose phase and amplitude have been equalized by This is to generate an initialization signal corresponding to the eye deterioration rate calculated as follows. This initialization signal sets an initial value for the integrating circuit that constitutes the SQD evaluation circuit 5.

SQD評価回路5は、後述するように、誤差信号を人力
として、回線品質を評価する品質評価信号を生成するも
のである。
As will be described later, the SQD evaluation circuit 5 generates a quality evaluation signal for evaluating line quality using the error signal manually.

〔作用〕[Effect]

第1図に示す構成を採用し、受信信号を等化回路1に入
力すると、等化回路lは位相および振幅の等化を行い、
等化信号を送出する。この送出された等化信号は、判定
回路2によって判定され、判定結果信号が送出される。
When the configuration shown in FIG. 1 is adopted and the received signal is input to the equalization circuit 1, the equalization circuit 1 equalizes the phase and amplitude.
Sends an equalized signal. This sent out equalized signal is judged by the judgment circuit 2, and a judgment result signal is sent out.

一方、等化信号と判定結果信号とを加算回路3に図示極
性で入力することにより、両者の誤差に対応する誤差信
号が生成される。この生成された誤差信号は、アイ劣化
率算出回路4に入力され、当該等化回路に、対してイン
パル応答法が適用された場合のアイ劣化率が算出される
。この算出されたアイ劣化率に対応した所定の初期化信
号を生成し、この生成した初期化信号を用いて、SQD
評価回路5を構成する積分回路の初期値を設定する。こ
のため、当該SQD評価回路5に人力された誤差信号に
対応した形での品質評価信号が迅速に生成され、短いト
レーニング信号に対しても十分引き込まれた態様の品質
評価信号が出力される。
On the other hand, by inputting the equalization signal and the determination result signal to the adder circuit 3 with the illustrated polarities, an error signal corresponding to the error between the two is generated. This generated error signal is input to the eye deterioration rate calculation circuit 4, and the eye deterioration rate when the impulse response method is applied to the equalization circuit is calculated. A predetermined initialization signal corresponding to this calculated eye deterioration rate is generated, and using this generated initialization signal, the SQD
The initial value of the integrating circuit constituting the evaluation circuit 5 is set. Therefore, a quality evaluation signal corresponding to the error signal manually input to the SQD evaluation circuit 5 is quickly generated, and a quality evaluation signal that is sufficiently drawn in even for a short training signal is output.

以上説明したように、平均化法(積分回路)を用いたS
QD評価回路に対して、インパルス応答法を用いて算出
したアイ劣化率に対応した初期化信号を当該SQD評価
回路を構成する積分回路に供給して強制的に初期値を設
定する構成を採用することにより、平均化法を用いたS
QD評価回路の引き込みを迅速に行わせ、以後はトレー
ニング信号の短いものに対しても安定に品質評価信号を
生成して出力することが可能となる。
As explained above, S
For the QD evaluation circuit, a configuration is adopted in which an initialization signal corresponding to the eye deterioration rate calculated using the impulse response method is supplied to the integrating circuit forming the SQD evaluation circuit to forcibly set an initial value. By using the averaging method, S
The QD evaluation circuit is quickly pulled in, and thereafter it becomes possible to stably generate and output quality evaluation signals even for short training signals.

〔実施例〕〔Example〕

第2図ないし第5図を用いて第1図図中アイ劣化率算出
回路4の構成および動作を詳細に説明する。
The configuration and operation of the eye deterioration rate calculation circuit 4 in FIG. 1 will be explained in detail using FIGS. 2 to 5.

第2図はインパルス応答法の動作概念説明図を示し、第
2図(イ)はEYE (アイ)劣化がない場合のインパ
ルス応答波形を示し、第2図(ロ)はアイ劣化がある場
合のインパルス応答波形を示す。この両者の図から判明
するように、インパルス応答の劣化量よ勾、SQD値(
信号品質評価値)を算出することができる。以下順次詳
細に説明する。
Figure 2 shows an illustration of the operational concept of the impulse response method, Figure 2 (a) shows the impulse response waveform when there is no EYE deterioration, and Figure 2 (b) shows the impulse response waveform when there is eye deterioration. The impulse response waveform is shown. As can be seen from both figures, the amount of deterioration of the impulse response is dependent on the slope and the SQD value (
signal quality evaluation value) can be calculated. A detailed explanation will be given below.

第1に、逆マトリツクス演算時の最終回でのエラー0な
いし+23次の絶対値の累積和を算出する。これは、第
3図図中のインパルス応答波形中に記入した0、■、■
・・・@、および1.3・・・23における誤差を夫々
算出し、絶対値の累積和を算出すればよい。
First, the cumulative sum of absolute values of errors 0 to +23rd order in the final round of inverse matrix calculation is calculated. This corresponds to 0, ■, ■ written in the impulse response waveform in Figure 3.
. . @ and 1.3 . . . 23 may be calculated, respectively, and the cumulative sum of absolute values may be calculated.

第2に、上記値よりアイ劣化率Ecを下式を用いて算出
する。
Second, the eye deterioration rate Ec is calculated from the above values using the following formula.

E C=(Σl St  l −l So  l)/l
 So  l xlOOχ当該Ecの値を正規化する処
理をほどこしてE c =22/(3(1+(2)””
))(ΣIE i  l)、X100χ・(11となる
。ここで、ΣIE、1は、第1のステップで算出した逆
マトリツクス演算時の最終回でのエラーの絶対値の累積
和(0ないし+23次)である。
E C=(Σl St l −l So l)/l
So l xlOOχ After normalizing the value of Ec, E c =22/(3(1+(2)")
))(ΣIE i l), Next).

第3に、アイ劣化率算出回路4の等化回路を求めると、
第4図(イ)に示すものが得られる。図中N3は正規化
係数である。更に、具体化すると第4図(ロ)に示す等
化回路が得られる。図中!SQDは、第5図に示すよう
に、伝送速度に依存した値を持つ。
Thirdly, when determining the equalization circuit of the eye deterioration rate calculation circuit 4,
What is shown in FIG. 4(a) is obtained. In the figure, N3 is a normalization coefficient. Furthermore, when this is implemented, an equalization circuit shown in FIG. 4(b) can be obtained. In the diagram! As shown in FIG. 5, SQD has a value that depends on the transmission speed.

以上説明したようにして生成した等化回路を用いて、誤
差信号からインパルス応答法の場合に対応するアイ劣化
率Ecを算出し、次いで、この算出したアイ劣化率E、
からSQD値を算出する。
Using the equalization circuit generated as described above, the eye deterioration rate Ec corresponding to the impulse response method is calculated from the error signal, and then the calculated eye deterioration rate E,
Calculate the SQD value from

そして、このSQD値に対応した初期化信号を生成し、
次に説明するSQD評価回路5を構成する積分回路に供
給して例えばタップを切り換えるようにする。
Then, generate an initialization signal corresponding to this SQD value,
The signal is supplied to an integrating circuit constituting an SQD evaluation circuit 5, which will be described next, to switch taps, for example.

第6図はSQD評価回路5であって、当該SQD評価回
路5を構成する積分回路(加算器15および帰還利得回
路16)中の帰還利得回路16に対して、前述したアイ
劣化率算出回路4から供給されたイニシャライズ信号(
初期化信号)によって、インパルス応答法によって算出
したSQD値が初期設定される。このため、第6図図示
SQD評価回路5は、迅速に回線品質を検出して図示品
質評価信号として送出することが可能となる。以下簡単
に構成および動作を説明する。
FIG. 6 shows the SQD evaluation circuit 5, in which the aforementioned eye deterioration rate calculation circuit 4 Initialization signal supplied from (
Initialization signal) initializes the SQD value calculated by the impulse response method. Therefore, the illustrated SQD evaluation circuit 5 in FIG. 6 can quickly detect the line quality and send it out as an illustrated quality evaluation signal. The configuration and operation will be briefly explained below.

第6図において、誤差信号IEを出力帰還点となる乗算
器11を介してスカラー値変換回路12に入れる。スカ
ラー値変換回路12は、誤差信号IE(ヘクトル量、信
号中の位相誤差成分および振幅誤差成分を含む)をパワ
ーに変換するため、その振幅値の2乗値または絶対値を
作成する。これにより誤差信号IEは虚数値を含まない
絶対量で表現されることとなり、実数部分、虚数部分の
両方で管理することなく、一つの実数値で管理できる。
In FIG. 6, the error signal IE is input to a scalar value conversion circuit 12 via a multiplier 11 which serves as an output feedback point. The scalar value conversion circuit 12 creates the square value or absolute value of the amplitude value in order to convert the error signal IE (including the hector quantity, the phase error component and the amplitude error component in the signal) into power. As a result, the error signal IE is expressed as an absolute quantity that does not include an imaginary value, and can be managed with a single real value without having to be managed with both a real part and an imaginary part.

このスカラー値を次の加算部13に入力し、等化出力に
対応する基準値B0から差し引く。基準値B0は、演算
限界幅の1/2程度に設定される。従って、この加算器
13の出力は、入力された誤差信号IEのスカラー値が
予め設定された演算限界幅の中央値、例えば平均的な回
線の誤差からどの程度相違する値であるかを示すものと
なる。
This scalar value is input to the next adder 13 and subtracted from the reference value B0 corresponding to the equalized output. The reference value B0 is set to about 1/2 of the calculation limit width. Therefore, the output of the adder 13 indicates how much the scalar value of the input error signal IE differs from the median value of the preset calculation limit width, for example, the average line error. becomes.

加算器13の出力は、乗算部14で制御定数T。The output of the adder 13 is converted into a control constant T by a multiplier 14.

が乗算される。乗算器14の出力は、加算器15声・描
遭刊湧■1蕗16声よめなる精分冊路乙こ入力される。
is multiplied. The output of the multiplier 14 is inputted into the adder 15, which is a 15-tone, 16-tone signal.

従って、この積分回路は、連続して入力される複数の誤
差信号に対する基準値B0との相違量が同一方向になる
まで(正または負の一方の極性となるので)正または負
の方向の何れか一方向に増加的になる。他方、回線の劣
化が大きければ大きい程、基準値B。に対する相違量は
、正負に出現することになり、その積分量は、零の方向
に向かって小さい値となる。この際、第2図ないし第5
図を用いて説明したインパルス応答法を用いて算出した
SQD値に対応した値が、初期化信号として積分回路を
構成する帰還利得回路16に入力されているため、極め
て迅速に当該積分回路が動作状態になり、有意な値を発
生させることができる。
Therefore, this integrator circuit operates in either the positive or negative direction until the amount of difference from the reference value B0 for a plurality of error signals that are continuously input becomes the same direction (because the polarity is either positive or negative). or increase in one direction. On the other hand, the greater the deterioration of the line, the greater the reference value B. The amount of difference with respect to will appear as positive or negative, and its integral amount will become a smaller value toward zero. At this time, Figures 2 to 5
Since the value corresponding to the SQD value calculated using the impulse response method explained using the diagram is inputted as an initialization signal to the feedback gain circuit 16 that constitutes the integrator circuit, the integrator circuit operates extremely quickly. state and can generate significant values.

積分回路からの積分出力を更に乗算部17で制御力定数
γ1を乗じ、加算部18で基準値C6との差をとる。こ
れにより、乗算部11へのフィードバック量を調整する
ことができる。そして、この値を加算部19に供給する
。この帰還ループの出力Cは、誤差信号が小さく回線劣
化が小さい場合にはCの値は大きくなり、誤差信号が大
きく回線劣化が大きい場合にしよCは急速に減少する値
がアナログ量として得られる。この回路の出力Cを2値
のデジタル量として出力するため、加算部19で誤差率
により定めた基準値D0との差をとり2値の品質評価信
号が出力され、回線の品質の評価に用いられる。
The integral output from the integrating circuit is further multiplied by a control force constant γ1 in a multiplier 17, and the difference from the reference value C6 is calculated in an adder 18. Thereby, the amount of feedback to the multiplier 11 can be adjusted. This value is then supplied to the adding section 19. The output C of this feedback loop is obtained as an analog quantity when the error signal is small and line deterioration is small, the value of C becomes large, and when the error signal is large and line deterioration is large, C rapidly decreases. . In order to output the output C of this circuit as a binary digital quantity, an adder 19 takes the difference from the reference value D0 determined by the error rate and outputs a binary quality evaluation signal, which is used to evaluate the quality of the line. It will be done.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、受信信号を等化
した等化信号とこの等化した信号を判定した判定信号と
の誤差に基づいて算出したアイ劣化率を用いて、信号品
質評価回路を構成する積分回路の初期値を設定する構成
を採用しているため、信号品質評価回路の引き込み速度
を速くすることができる。このため、受信した信号中に
含まれるトレーニング信号の持続時間が極めて短いもの
例えば数msないし数+msのものに対しても十分に安
定に引き込みを行って回線の品質を評価することができ
る。
As described above, according to the present invention, signal quality is evaluated using an eye deterioration rate calculated based on the error between an equalized signal obtained by equalizing a received signal and a judgment signal obtained by determining this equalized signal. Since the configuration is adopted in which the initial value of the integrating circuit constituting the circuit is set, the pull-in speed of the signal quality evaluation circuit can be increased. Therefore, even if the duration of the training signal included in the received signal is extremely short, for example, several ms to several + ms, the line quality can be evaluated with sufficient stability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の原理的構成図、第2図はインパルス応
答法の動作概念説明図、第3図はアイ劣化率算出説明図
、第4図はアイ劣化率算出回路例、第5図はアイ劣化率
算出回路のパラメータ例、第6図はSQD評価回路を示
す。 図中、■は受信信号の位相および振幅を等化する等化回
路、2は判定回路、3は加算回路、4はアイ劣化率算出
回路、5はSQD評価回路を表す。
Figure 1 is a diagram showing the basic configuration of the present invention, Figure 2 is a diagram explaining the operational concept of the impulse response method, Figure 3 is a diagram explaining eye deterioration rate calculation, Figure 4 is an example of an eye deterioration rate calculation circuit, and Figure 5. 6 shows an example of parameters for an eye deterioration rate calculation circuit, and FIG. 6 shows an SQD evaluation circuit. In the figure, ■ represents an equalization circuit that equalizes the phase and amplitude of the received signal, 2 represents a determination circuit, 3 represents an addition circuit, 4 represents an eye deterioration rate calculation circuit, and 5 represents an SQD evaluation circuit.

Claims (1)

【特許請求の範囲】 受信信号を等化した信号と、この等化した信号を判定し
た判定信号との誤差に基づいて、信号品質の検出を行う
信号品質検出方式において、前記誤差に対応する誤差信
号をスカラー値に変換し、この変換したスカラー値に応
じた積分値を生成する信号品質評価回路(5)と、 前記誤差に対応する誤差信号を用いて、アイ劣化率を算
出するアイ劣化率算出回路(4)とを備え、このアイ劣
化率算出回路(4)によって算出したアイ劣化率に対応
して、前記信号品質評価回路(5)を構成する積分回路
の初期値を設定し、当該信号品質評価回路(5)によっ
て検出した品質評価信号を出力するよう構成したことを
特徴とする信号品質検出方式。
[Claims] In a signal quality detection method that detects signal quality based on an error between a signal obtained by equalizing a received signal and a judgment signal obtained by determining this equalized signal, an error corresponding to the error is provided. a signal quality evaluation circuit (5) that converts a signal into a scalar value and generates an integral value according to the converted scalar value; and an eye deterioration rate that calculates an eye deterioration rate using an error signal corresponding to the error. a calculation circuit (4), and sets an initial value of an integrating circuit constituting the signal quality evaluation circuit (5) in accordance with the eye deterioration rate calculated by the eye deterioration rate calculation circuit (4), and A signal quality detection method characterized by being configured to output a quality evaluation signal detected by a signal quality evaluation circuit (5).
JP27386385A 1985-12-05 1985-12-05 Signal quality detection method Granted JPS62133828A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27386385A JPS62133828A (en) 1985-12-05 1985-12-05 Signal quality detection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27386385A JPS62133828A (en) 1985-12-05 1985-12-05 Signal quality detection method

Publications (2)

Publication Number Publication Date
JPS62133828A true JPS62133828A (en) 1987-06-17
JPH0441853B2 JPH0441853B2 (en) 1992-07-09

Family

ID=17533607

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27386385A Granted JPS62133828A (en) 1985-12-05 1985-12-05 Signal quality detection method

Country Status (1)

Country Link
JP (1) JPS62133828A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970008941A (en) * 1995-07-13 1997-02-24 가네꼬 히사시 Signal quality evaluation method for direct sequential frequency spreading receiver
JP2007028160A (en) * 2005-07-15 2007-02-01 Japan Radio Co Ltd Amplitude phase control device and receiving system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59171230A (en) * 1983-03-17 1984-09-27 Mitsubishi Electric Corp Pseudo error rate measuring circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59171230A (en) * 1983-03-17 1984-09-27 Mitsubishi Electric Corp Pseudo error rate measuring circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970008941A (en) * 1995-07-13 1997-02-24 가네꼬 히사시 Signal quality evaluation method for direct sequential frequency spreading receiver
JP2007028160A (en) * 2005-07-15 2007-02-01 Japan Radio Co Ltd Amplitude phase control device and receiving system
JP4708105B2 (en) * 2005-07-15 2011-06-22 日本無線株式会社 Amplitude phase control device and receiving system

Also Published As

Publication number Publication date
JPH0441853B2 (en) 1992-07-09

Similar Documents

Publication Publication Date Title
US7400675B2 (en) System and method for digital adaptive equalization with failure detection and recovery
US20020021767A1 (en) Digital base-band receiver
US5475632A (en) Method of and apparatus for identifying unknown system using adaptive filter
US6173019B1 (en) Control loop for data signal baseline correction
US6363111B1 (en) Control loop for adaptive multilevel detection of a data signal
US6744330B1 (en) Adaptive analog equalizer
US9020024B1 (en) Rate-adaptive equalizer that automatically initializes itself based on detected channel conditions, and a method
US6782043B1 (en) Method and apparatus for estimating the length of a transmission line
JPS62133828A (en) Signal quality detection method
JPH06188788A (en) Adaptive automatic equalizer
US4500999A (en) Line equalizer
JP2611557B2 (en) Decision feedback type automatic equalizer
JPH0468673A (en) Waveform distortion removing circuit
CN116232816B (en) Signal processing method, signal transmission device and interconnection interface
JPH0817375B2 (en) Sampling phase extraction circuit
US6463106B1 (en) Receiver with adaptive processing
JPS631781B2 (en)
WO1999014912A1 (en) Method and apparatus for modified baud rate sampling
JP3071811B2 (en) Modem control method
JPS5854686B2 (en) Signal quality detection method
KR19990066518A (en) Mode conversion control device of adaptive equalizer
US6018558A (en) Signal disconnection detection circuit that ensures positive detection of signal disconnection
JPH0435113A (en) Decision feedback type equalizer
KR100206810B1 (en) Equalizer and ghost position discriminating method
JPS593046B2 (en) Data transmission automatic equalization method

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees