JPS62131578A - Manufacturing method of thin film transistor - Google Patents
Manufacturing method of thin film transistorInfo
- Publication number
- JPS62131578A JPS62131578A JP60271987A JP27198785A JPS62131578A JP S62131578 A JPS62131578 A JP S62131578A JP 60271987 A JP60271987 A JP 60271987A JP 27198785 A JP27198785 A JP 27198785A JP S62131578 A JPS62131578 A JP S62131578A
- Authority
- JP
- Japan
- Prior art keywords
- film
- resistance semiconductor
- semiconductor film
- metal film
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、アクティブマトリクス液晶表示装置における
低コストで高歩留まりの薄膜トランジスタの製造方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing thin film transistors in active matrix liquid crystal display devices at low cost and with high yield.
絶縁基板上にゲート電極を形成し、ゲート電掘引出し部
の一部をマスクして、ゲート絶縁膜と、掻めて薄い高抵
抗半導体膜と極めて薄い低抵抗半導体膜と金属膜を連続
して堆積し、ゲート電極上とゲート電極引出し部の一部
に高抵抗半導体膜と低抵抗半導体膜と金属膜をほぼ同一
形状に選択的に形成し、スパッタエツチング後連続して
透明導電膜を堆積し、j3明導電膜をソース電極とドレ
イン電極とゲート電極の引出し部に選択的に形成し、金
属膜と低抵抗半導体膜を透明導電膜をマスクの一部とし
て選択的に除去する工程の薄膜トランジスタによって、
遮光不要で、製造工数が少なく(3枚マスク工程)、ソ
ース電極部とドレイン電極部の良好なコンタクト状態を
得、低コストのアクティブマトリクス液晶表示装置基板
である薄膜トランジスタが出来るようにしたものである
。A gate electrode is formed on an insulating substrate, a part of the gate electrically excavated lead-out part is masked, and a gate insulating film, an extremely thin high-resistance semiconductor film, an extremely thin low-resistance semiconductor film, and a metal film are successively formed. A high-resistance semiconductor film, a low-resistance semiconductor film, and a metal film are selectively formed in almost the same shape on the gate electrode and a part of the gate electrode extension part, and after sputter etching, a transparent conductive film is successively deposited. ,j3 By selectively forming a transparent conductive film on the lead-out portions of the source electrode, drain electrode, and gate electrode, and selectively removing the metal film and the low-resistance semiconductor film using the transparent conductive film as part of a mask, ,
It does not require light shielding, requires fewer manufacturing steps (3-mask process), and provides good contact between the source and drain electrodes, making it possible to produce thin film transistors that are low-cost active matrix liquid crystal display substrates. .
例えば、アモルファスシリコン(a−3L)を用いた従
来のアクティブマトリクス液晶表示装置における表示装
置用基板である薄膜トランジスタの製造方決の例を第6
図(81〜Telに示す。第6図ta)は、ガラス等の
絶縁基板1上にCr 、A1. Mo等のゲート電極2
をスパッタ装置等で堆積後、選択的に形成した断面図を
示す。ゲート電極2の引出し部2゛ も図示している。For example, the sixth example shows an example of the manufacturing method of a thin film transistor, which is a display device substrate in a conventional active matrix liquid crystal display device using amorphous silicon (a-3L).
The figure (shown in 81-Tel, FIG. 6 ta) shows that Cr, A1. Gate electrode 2 made of Mo etc.
A cross-sectional view showing selectively formed after deposition using a sputtering device or the like is shown. A lead-out portion 2′ of the gate electrode 2 is also shown.
第6開山)は、二酸化シリコン、チッ化シリコン等のゲ
ート絶縁膜3、アモルファスシリコン等の高抵抗半導体
膜4を連続して堆積し、高抵抗半導体膜4を選択エッチ
する。In the sixth step (6th opening), a gate insulating film 3 such as silicon dioxide or silicon nitride, and a high resistance semiconductor film 4 such as amorphous silicon are successively deposited, and the high resistance semiconductor film 4 is selectively etched.
次に二酸化シリコン等の眉間絶縁膜5、[TO等の透明
導電膜である画素電極6を堆積し、画素電極6を選択エ
ッチした断面図を示す第6図(C1では、層間絶縁膜5
を開孔した状態を示す。第6図(d+は、低抵抗半導体
膜7 (例えばN゛ア7モルフアスシリコン膜A/等の
金属膜を堆積し、選択エッチによってドレイン電極8.
ソース電極9.ゲート引出し′:4.iloを形成した
状態を示す。またソース電極9と画素電極6は接続され
ている。第6図(e)は、二酸化シリコン等の表面保護
膜11を堆積し、画素電極6とゲート引出し電極10の
一部の表面保護膜11をエッチして露出させた断面図を
示す。なお図示してないが、ドレイン電極引出し部の表
面保護膜11も工・ノチして、外部とのコンタクトが出
来るように形成している。また表面保護膜11は、遮光
も兼ねていたり、表面保護膜ll上に遮光膜を形成する
場合が多い。Next, a glabellar insulating film 5 such as silicon dioxide and a pixel electrode 6 which is a transparent conductive film such as [TO] are deposited, and the pixel electrode 6 is selectively etched.
This shows the state in which the hole has been drilled. FIG. 6 (d+ indicates a metal film such as a low resistance semiconductor film 7 (for example, a N7 amorphous silicon film A/) is deposited and selectively etched to form a drain electrode 8.
Source electrode 9. Gate drawer': 4. The state in which ilo is formed is shown. Further, the source electrode 9 and the pixel electrode 6 are connected. FIG. 6(e) shows a cross-sectional view in which a surface protective film 11 made of silicon dioxide or the like is deposited, and part of the surface protective film 11 of the pixel electrode 6 and the gate extraction electrode 10 is exposed by etching. Although not shown, the surface protective film 11 of the drain electrode extension portion is also etched and notched to form contact with the outside. In many cases, the surface protection film 11 also serves as a light shield, or a light shielding film is formed on the surface protection film 11.
従来のアクティブマトリクス表示装置用基板の薄膜トラ
ンジスタの製造方法においては、第6図の例に示したよ
うにマスク工程が多く (6回以上)低コストの表示装
置用の薄膜トランジスタが提供できない、また層間絶縁
膜5.ゲート絶縁膜3を開孔するために、遮光膜を形成
しなくてもよい極めて薄い高抵抗半導体膜4(例えばア
モルファスシリコン膜で500Å以下の膜厚)を形成し
たとき、ゲート電極引出し部2°上のゲー日色縁[3が
完全に開孔するまでエツチングすると、アモルファスシ
リコン膜4のピンホール等のためトランジスタ部のゲー
ト絶縁膜3がエツチングされて、耐圧低下あるいはショ
ート等が発生して、画素欠陥、ライン欠陥等が発生し歩
留まりが悪くなる。In the conventional method for manufacturing thin film transistors for active matrix display device substrates, as shown in the example in Figure 6, there are many masking steps (six or more), which makes it impossible to provide low-cost thin film transistors for display devices, and interlayer insulation. Membrane 5. When forming an extremely thin high-resistance semiconductor film 4 (for example, an amorphous silicon film with a thickness of 500 Å or less) that does not require the formation of a light-shielding film in order to open the gate insulating film 3, the gate electrode extension portion 2° If etching is performed until the upper gate edge [3] is completely opened, the gate insulating film 3 of the transistor section will be etched due to pinholes in the amorphous silicon film 4, resulting in a drop in breakdown voltage or a short circuit. Pixel defects, line defects, etc. occur, resulting in poor yield.
また、ゲート電極引出し部2゛のゲート絶縁膜3が完全
にエツチングされたかどうかの判断がむずかしく、完全
に開孔されずに次工程に進むと欠陥となる。またゲート
引き出し電極とゲート電極引出し部2′の良好なコンタ
クトを得るのも困難である。また、高抵抗半導体膜4を
堆積後、エソチング工程等を経てから低抵抗半導体膜7
(例えばN゛ア7モルフアスシリコン膜堆積すると、高
抵抗半導体膜40表面に自然酸化膜が生じて、低抵抗半
導体膜7との良好なコンタクトが得られず、トランジス
タ特性が悪くなる欠点があった。Furthermore, it is difficult to judge whether the gate insulating film 3 of the gate electrode lead-out portion 2' has been completely etched, and if the etching proceeds to the next step without being completely etched, a defect will result. Furthermore, it is difficult to obtain good contact between the gate lead electrode and the gate electrode lead part 2'. Further, after depositing the high resistance semiconductor film 4, the low resistance semiconductor film 7 is formed after going through an etching process or the like.
(For example, when a N7 amorphous silicon film is deposited, a natural oxide film is formed on the surface of the high-resistance semiconductor film 40, making it impossible to obtain good contact with the low-resistance semiconductor film 7, resulting in poor transistor characteristics. Ta.
上記問題点を解決するために本発明は、ゲート絶縁膜、
高抵抗半導体膜、低抵抗半導体膜、金属膜をゲート電極
引出し部の一部をメタルマスク等でマスキングして連続
堆積し、ゲート電極上とゲート電極引出し部の一部に高
抵抗半導体膜、低抵抗半導体膜、金属膜をほぼ同一形状
に選択形成し、スパッタエツチング後透明導電膜を形成
し、透明導電膜をソース電極とドレイン電極とゲート電
極引出し部に選択形成後、選択形成した透明導電膜をマ
スクの一部として、金属膜と低抵抗半導体膜を選択除去
することによって、上記問題点を解決するようにした。In order to solve the above problems, the present invention provides a gate insulating film,
A high-resistance semiconductor film, a low-resistance semiconductor film, and a metal film are sequentially deposited by masking a part of the gate electrode lead-out part with a metal mask, etc., and the high-resistance semiconductor film, the low-resistance semiconductor film, and the A resistive semiconductor film and a metal film are selectively formed in almost the same shape, a transparent conductive film is formed after sputter etching, a transparent conductive film is selectively formed on a source electrode, a drain electrode, and a gate electrode lead-out portion, and then a transparent conductive film is selectively formed. The above-mentioned problem was solved by selectively removing the metal film and the low-resistance semiconductor film using the mask as part of the mask.
上記のように構成されたアクティブマトリクス表示装置
用の薄膜トランジスタは、3回のマスク工程で出来るば
かりでなく、ソース電極、ドレイン電極、ゲート引出し
電極部のコンタクトが良好で、しかも遮光膜の必要ない
低コストアクティブマトリクス表示装置用の薄膜トラン
ジスタを提供できる。The thin film transistor for an active matrix display device configured as described above can not only be produced in three mask steps, but also has good contact between the source electrode, drain electrode, and gate lead electrode, and is a thin film transistor that does not require a light shielding film. A thin film transistor for a cost-active matrix display device can be provided.
以下に本発明の実施例を図面に基づいて詳細に説明する
。Embodiments of the present invention will be described in detail below based on the drawings.
第1図(al〜(flと第2図(al〜(「)は、本発
明の第一実施例であるアクティブマトリクス表示装置用
の薄膜トランジスタの単位画素部及びゲート電極引出し
部の平面図と断面図の例を示す、その製造方法は以下に
述べる通りである。第1図(a)(第2図(alは第1
図+IllのA−A’線に沿った断面図)は、ガラス等
の絶縁基板l上にCr 、 Ni 、 NiCr等でゲ
ート電極2と外部取出し用のゲート電極引出し部2°を
選択的に形成した状態を示す。第1図(bl(第2図中
)は第1図fb)のB−B’緑に沿った断面図)は、ゲ
ート電極引出し部2°を金属マスク等でマスクして、ゲ
ート絶縁膜3.高抵抗半導体膜4、低抵抗半導体膜7.
金属膜12を連続して堆積し、ゲート電極引出し部2゛
上に上記膜が堆積されない状態を示す。例えば、プラズ
マCVD装置において真空をやふることなく、SiH,
とNH。FIG. 1(al~(fl) and FIG. 2(al~()) are a plan view and a cross-sectional view of a unit pixel portion and a gate electrode lead-out portion of a thin film transistor for an active matrix display device according to a first embodiment of the present invention. The manufacturing method shown in the figure is as follows.
A cross-sectional view taken along the line A-A' in Figure +Ill) shows that a gate electrode 2 and a gate electrode extension portion 2° for external extraction are selectively formed using Cr, Ni, NiCr, etc. on an insulating substrate l such as glass. Indicates the state of FIG. 1 (bl (in FIG. 2) is a cross-sectional view along line B-B' green in FIG. .. High resistance semiconductor film 4, low resistance semiconductor film 7.
A state in which the metal film 12 is continuously deposited and the above film is not deposited on the gate electrode extension part 2' is shown. For example, SiH,
and N.H.
の混合ガスからゲート絶縁膜3として窒化膜(SiNX
)、 S+Haを用いて高抵抗半導体膜4としてアモ
ルファスシリコン膜(a−5t:H) 、 PHsとS
i Haの混合ガスから低抵抗半導体膜7としてN゛
ア7モルフアスシリコン膜’a−5i:H) ヲ連Vt
的に形成する。次に金属膜12は、スパッタまたは蒸着
機でCr 、 Ni 、 NiCr等を形成する。なお
、プラズマCVDとスパッタから成るインライン型の装
置を用いると上記ゲート絶縁膜3. a−5t;)(
膜4、 N″a −5i: H膜7.金属膜12が、大
気に出すことなく連続的に堆積できる。また金属膜12
は、後述するドレイン電極配線の一部となり配線抵抗を
小さくする上で有効である。またITOとN’a−5i
:H膜7は有効なコンタクト特性が得にくいが、金属膜
12 (Cr 、 Ni 、 NiCr )等を介して
ITOとコンタクトするので有効な特性が得られる。A nitride film (SiNX
), an amorphous silicon film (a-5t:H) as the high-resistance semiconductor film 4 using S+Ha, PHs and S
From the mixed gas of i Ha to the low-resistance semiconductor film 7, N゛a7morphous silicon film'a-5i:H) WorenVt
to form. Next, the metal film 12 is formed of Cr, Ni, NiCr, etc. by sputtering or vapor deposition. Note that if an in-line type device consisting of plasma CVD and sputtering is used, the gate insulating film 3. a-5t;)(
Film 4, N″a-5i: H film 7. The metal film 12 can be continuously deposited without exposing it to the atmosphere.
becomes a part of the drain electrode wiring, which will be described later, and is effective in reducing the wiring resistance. Also ITO and N'a-5i
Although it is difficult to obtain effective contact characteristics with the :H film 7, effective characteristics can be obtained since it is in contact with ITO via the metal film 12 (Cr, Ni, NiCr), etc.
第1図(C)(第2図fclは第1図(C)のc−c’
線に沿った断面図)は、レジスト13を塗布、露光。Figure 1 (C) (Figure 2 fcl is c-c' in Figure 1 (C)
In the cross-sectional view taken along the line), resist 13 is applied and exposed.
現像を行った後、レジスト13をマスクにして金属膜1
2.低抵抗半導体膜7.高抵抗半導体膜4を連続して選
択的にエツチングした状態を示す。After development, the metal film 1 is formed using the resist 13 as a mask.
2. Low resistance semiconductor film7. A state in which the high-resistance semiconductor film 4 is continuously and selectively etched is shown.
この時、ゲート電極引出し部2”上もレジスト13を残
し、金屈膜工2のエツチング時ゲート電極引出し部2゛
がエツチングされないようにすることが重要である。第
1図(d)(第2図fd)は第1図+diのD−D’線
に沿った断面図)は、金属膜12表面の酸化膜層を除去
(例えばスパッタエツチングまたはプラズマエツチング
等)後、連続してITO等の透明導1を膜14を堆積し
た状態を示す、金g!4膜12表面の酸化膜層を除去し
て大気にさらすことなく透明導電膜14を堆積している
ので、良好なコンタクトが得られる。第1図(e)(第
2図(elは、第1図telのE−E’線に沿った断面
図)は、レジスト15を塗布後、露光、現像を行った後
、透明導電膜14をエツチングして画素電極を兼ねるソ
ース電極9(14−2)、 ドレイン電極8(14−
1)を形成した状態を示す。この時、ゲート電極引出し
部2°上にも透明導?1ill14−3が形成されるよ
うにする。透明導電膜14−3を形成しないと透明導電
膜14−3エツチングの時(主に塩酸でエツチング)、
ゲート電極引出し部2“がエツチングされるのと、次の
工程で金属膜12をエツチングするとき、同様にゲート
電極引出し部2゛がエツチングされて、表示装置用の基
板が出来なくなる。第1図(f)(第2図fflは、第
1図(flのF−F’線に沿った断面図)は、透明導電
膜14−1.14−2.14−3を上記のように選択的
に形成した後、レジスト15を剥離しないで、透明導電
膜14−1.14−2.14−3をマスクの一部として
、金属膜12.低抵抗半導体膜7を選択的に形成し、レ
ジスト15を剥離した状態を示す。N″a−3i:H膜
7のエツチングは、一般にCF l系ガスによるプラズ
マエツチングや、フ・ノ酸と硝酸の混合液によるエツチ
ングがある。At this time, it is important to leave the resist 13 on the gate electrode extension part 2'' so that the gate electrode extension part 2'' is not etched during the etching of the metal film 2. Figure 2 (fd) is a cross-sectional view taken along the line DD' in Figure 1 + di), which shows that after the oxide film layer on the surface of the metal film 12 is removed (for example, by sputter etching or plasma etching), a layer of ITO or the like is continuously etched. The transparent conductive film 14 is deposited on the transparent conductive film 14 without removing the oxide film layer on the surface of the gold G!4 film 12 and depositing the transparent conductive film 14 without exposing it to the atmosphere, so good contact can be obtained. 1(e) (FIG. 2 (el is a sectional view taken along line EE' in FIG. 1) shows that after coating the resist 15, exposing and developing, the transparent conductive film is removed. 14 is etched to form a source electrode 9 (14-2) which also serves as a pixel electrode, and a drain electrode 8 (14-2).
1) is shown. At this time, is there also a transparent conductor 2° above the gate electrode extension part? 1ill14-3 is formed. If the transparent conductive film 14-3 is not formed, when etching the transparent conductive film 14-3 (mainly etching with hydrochloric acid),
When the gate electrode extension part 2'' is etched, when the metal film 12 is etched in the next step, the gate electrode extension part 2'' is also etched, making it impossible to form a substrate for a display device. (f) (FIG. 2ffl is a cross-sectional view along the line FF' of fl). After forming the metal film 12 and the low resistance semiconductor film 7 selectively using the transparent conductive film 14-1.14-2.14-3 as part of a mask without peeling off the resist 15, The N''a-3i:H film 7 is generally etched by plasma etching using a CF1-based gas or etching using a mixed solution of fluoric acid and nitric acid.
CF、系ガスやフン酸と硝酸の混合液による方法では、
a −5i : H$ 4とN a −Si: H膜7
のエツチンググレートが早く、かつエツチングレートが
ほとんど変わらなく、制?ITJがむずかしい。そこで
、光の影響を受けにくい極めて薄いa −5i: H膜
4の膜厚(例えば500Å以下)の時は、a −5i
: H膜4まで完全にエツチングされてトランジスタが
形成されない時がある。そこで、a−5i:H膜4の膜
厚500Å以下の時は、N ’ a −5i: H膜7
の膜厚は200Å以下で、酸素プラズマエッチまたはス
パッタエッチによって′isJ膜トランジスタを作成す
る。上記方法だと、a−5i:H膜4は、ダメージが少
なく極めて安定に薄膜トランジスタが作成できる。また
絶縁膜を開孔する工程がないので、ソース、ドレイン、
ゲート電極引出し部の良好なコンタクト特性が得られる
。また図示していないが、ドレイン電極8は、延在して
ドレイン電極配線とドレイン1を掻引出し部を形成して
いて、金属膜12と透明導電膜14の二層構造でライン
抵抗が小さくなり好ましい。以上の3回のマスク工程で
アクティブマトリクス表示装置用の薄膜トランジスタが
出来る。In the method using CF, system gas, or a mixture of hydrofluoric acid and nitric acid,
a-5i: H$4 and Na-Si: H film 7
The etching rate is fast, and the etching rate hardly changes. ITJ is difficult. Therefore, when the thickness of the a-5i:H film 4 is extremely thin (for example, 500 Å or less), which is not easily affected by light, a-5i
: There are times when the H film 4 is completely etched and no transistor is formed. Therefore, when the thickness of the a-5i:H film 4 is 500 Å or less, the N'a-5i:H film 7
The film thickness is 200 Å or less, and an 'isJ film transistor is formed by oxygen plasma etching or sputter etching. With the above method, the a-5i:H film 4 can be extremely stably fabricated into a thin film transistor with little damage. In addition, since there is no process of opening holes in the insulating film, the source, drain,
Good contact characteristics of the gate electrode lead-out portion can be obtained. Although not shown, the drain electrode 8 extends to form a part where the drain electrode wiring and the drain 1 are pulled out, and the line resistance is reduced due to the two-layer structure of the metal film 12 and the transparent conductive film 14. preferable. Through the above three mask steps, a thin film transistor for an active matrix display device can be produced.
第3図(al〜(f)は、本発明の第2実施例であるア
クティブマトリクス表示装置用の薄膜トランジスタの断
面図である。第3図(8)〜(flは、第2図(al〜
(rlに示した本発明の薄膜トランジスタを、より高歩
留まりに安定に作るための実施例を示す、第3図+al
は、第2図(′b)の製造工程と同じように、ゲート1
橿2形成後、ゲート電極引出し部2°を金属マスク等で
マスクして、ゲート絶縁193.高抵抗半導体膜4.低
抵抗半導体膜7.金属膜12を連続的に形成した状態を
示す。第3図(blは、レジスト13塗布後、ゲート電
極2上とゲート電極引出し部2°上にレジストパターン
が形成されるように露光、現像を行った後、金属膜12
(例えばCr膜)をエツチングした図を示す、第3図(
C1は、金属膜12をエツチング後、連続して、低抵抗
半導体膜7 (例えばN″a−5i:l(膜)、高抵抗
半導体膜4(例えばa −5i: H膜)を、フッ酸と
硝酸の混合液でエツチングした一例を示す。上記混合液
でエツチングすると、サイドエッチによって第3図te
lのように、N”a−5i:H膜7とa −3i :
H膜4は、金属膜12(例えばCr膜)よりも小さいパ
ターンに形成される。またCF、系ガスによるプラズマ
エッチでも同様のことが起こりやすい。第3図+d+は
、金8膜12(例えばCr膜)がN″a−3i:)I膜
7とa −3i: H膜4よりも小さいパターンになる
ように再度金属膜12をエツチングした状態を示す、第
3図telは、レジスト13を剥離した状態を示す。そ
の後の工程は、第2図(d1〜(flと同様に行い第3
図(flに示すような薄膜トランジスタが得られる。第
3図fflから分かるように、画素電極を兼ねるITO
のソース電極14−2が、トランジスタの端部で断線す
ることなく金属膜12と接続される。3(a-1f) are cross-sectional views of a thin film transistor for an active matrix display device according to a second embodiment of the present invention.
(Figure 3+al shows an example for stably manufacturing the thin film transistor of the present invention shown in rl at a higher yield.
is the same as the manufacturing process shown in Fig. 2('b).
After forming the rod 2, the gate electrode extension portion 2° is masked with a metal mask or the like, and the gate insulation 193. High resistance semiconductor film 4. Low resistance semiconductor film7. A state in which the metal film 12 is continuously formed is shown. FIG. 3 (bl shows that after applying the resist 13, exposing and developing the resist pattern so that a resist pattern is formed on the gate electrode 2 and 2 degrees above the gate electrode extension part, the metal film 12
Figure 3 (for example, a Cr film) showing an etched view
In C1, after etching the metal film 12, the low resistance semiconductor film 7 (e.g. N''a-5i:l (film)) and the high resistance semiconductor film 4 (e.g. a-5i:H film) are etched with hydrofluoric acid. An example of etching with a mixed solution of nitric acid and nitric acid is shown below.
As in l, N''a-5i:H film 7 and a-3i:
The H film 4 is formed in a smaller pattern than the metal film 12 (for example, a Cr film). A similar problem is also likely to occur in plasma etching using CF or other gases. Figure 3 +d+ shows the state in which the metal film 12 is etched again so that the gold 8 film 12 (for example, Cr film) has a smaller pattern than the N''a-3i:)I film 7 and the a-3i:H film 4. 3 shows the state in which the resist 13 has been peeled off.The subsequent steps are performed in the same manner as in FIG.
A thin film transistor as shown in Figure (fl) is obtained. As can be seen from Figure 3 ffl, the ITO
The source electrode 14-2 is connected to the metal film 12 without disconnection at the end of the transistor.
第4図Fa1〜(flは、本発明の第3実施例である薄
膜トランジスタの断面図である。第4図ta)と第4図
(b)は、第3図+al、 iblと全く同じであるか
ら説明を省略する。第4図(C))は、金属膜12をエ
ツチング後、レジスト13が変形して金属膜12よりも
大きいパターンになる温度(例えば150℃以上)で熱
処理した状態を示す。第4図+dlは、低抵抗半導体膜
7 (N″a−9i:)I膜)と高抵抗半導体膜4(a
−Si:)(膜)をエツチングした状態を示す。Fig. 4 Fa1-(fl is a cross-sectional view of a thin film transistor according to the third embodiment of the present invention. Fig. 4 ta) and Fig. 4 (b) are exactly the same as Fig. 3 + al and ibl. The explanation will be omitted from here. FIG. 4(C) shows a state in which, after etching the metal film 12, the resist 13 is deformed and heat-treated at a temperature (for example, 150° C. or higher) to form a pattern larger than the metal film 12. Figure 4 +dl shows the low resistance semiconductor film 7 (N″a-9i:)I film) and the high resistance semiconductor film 4 (a
-Si:) (film) is shown in an etched state.
N ” a −5i: H膜7とa−5i:HRQ4に
多少サイドエッチ(約2μm位)が起きてもよいぐらい
レジスト13を形成しておく。第4図(elは、レジス
ト13を剥離した状態を示す。その後の工程は、第2図
fdl〜(flと同様に行い第4図(flに示すような
薄膜トランジスタが得られ、第3図の実施例と同様の効
果が得られる。第5図ta+〜te+は、本発明の第4
実施例であるアクティブマトリクス表示装置用の薄膜ト
ランジスタの実施例を示す断面図である。N'' a-5i: H film 7 and a-5i: A resist 13 is formed to a degree that allows some side etching (approximately 2 μm) to occur on HRQ4. The subsequent steps are carried out in the same manner as shown in FIGS. 2 fdl to (fl) to obtain a thin film transistor as shown in FIG. Figures ta+ to te+ show the fourth aspect of the present invention.
1 is a cross-sectional view showing an example of a thin film transistor for an active matrix display device according to an example.
第5図(al〜(e)は、第2図(al〜(flに示し
た本発明のa膜トランジスフを、より裔歩留まりに作る
ための実施例を示す、第5図fatは、第2図(al〜
(C1までの工程と全く同じで、金属膜12(例えばC
「膜)。Figures 5(al to 5e) show examples for producing the A-film transistors of the present invention shown in Figures 2(al to (fl) with a higher production yield. Figure (al~
(It is exactly the same as the process up to C1, and the metal film 12 (for example, C
"film).
低抵抗半導体膜7 (N’a−Si:+1膜)、高抵抗
半導体[4<a−3r:H膜)を選択形成後、レジスト
を211離した状態を示す。第5図(blは、透明導電
膜14−1.14−2.14−3 (例えばITO膜)
を堆積後、レジスト15を塗布、露光、現像してITO
膜14〜1.11−2.14−3を塩酸を主成分とする
液でエツチングした状態を示す、ITo膜14−1.1
4−2.14−3は、サイドエッチが入りやすく図のよ
うに形成されることが多い、第5図telは、ITO膜
14−1.14−2゜14−3形成後、レジストI5が
変形してITO膜14−1.14−2.14−3を完全
に覆うようになる温度(例えば150℃以上)で熱処理
した状態を示す、第5図fd+は、金属膜12と低抵抗
半導体膜7をエツチングした状態を示す。第5図(el
は、レジスト15を剥離した状態を示す。第5図ft1
lから分かるように、ITOIIJ14−1.14−2
.14−3にサイドエッチが発生してパターンが小さく
なっても、画素電極を兼ねるソース電極17 (7,
12,14−2)、 ドレイン電極16 (7,12
,14−1)は、金属膜12で決まるので、トランジス
タがオフセットゲートになることもなく好ましい。また
、ドレイン電極8の配線抵抗の増大あるいはパターン細
りによる断線等もなく安定した薄膜トランジスタが得ら
れる。After selectively forming a low resistance semiconductor film 7 (N'a-Si:+1 film) and a high resistance semiconductor [4<a-3r:H film], the resist is separated by 211 points. Figure 5 (bl is transparent conductive film 14-1.14-2.14-3 (for example, ITO film)
After depositing ITO, apply resist 15, expose and develop it.
ITo film 14-1.1 showing a state where films 14 to 1.11-2.14-3 have been etched with a solution containing hydrochloric acid as a main component.
4-2.14-3 is often formed as shown in the figure because it is easy to side-etch.The tel in FIG. 5 shows that the resist I5 is formed after the ITO film 14-1. FIG. 5fd+ shows a state in which the metal film 12 and the low resistance semiconductor are heat-treated at a temperature (for example, 150° C. or higher) that deforms and completely covers the ITO film 14-1.14-2.14-3. A state in which the film 7 is etched is shown. Figure 5 (el
1 shows a state in which the resist 15 has been peeled off. Figure 5 ft1
As can be seen from l, ITOIIJ14-1.14-2
.. Even if side etching occurs in 14-3 and the pattern becomes smaller, the source electrode 17 (7,
12, 14-2), drain electrode 16 (7, 12
, 14-1) is determined by the metal film 12, so the transistor does not become an offset gate, which is preferable. Furthermore, a stable thin film transistor can be obtained without an increase in wiring resistance of the drain electrode 8 or disconnection due to thinning of the pattern.
なお、本発明は第3図と第5図の実施例の組み合わせや
、第4図と第5図の実施例の組み合わせだとより有効な
効果が得られる
〔発明の効果〕
以上のように、3回のマスク工程(n光5現像工程)で
、良好なコンタクト特性を持ち、低コスト歩留まりのア
クティブマトリクス表示装置用の薄膜トランジスタを提
供出来る。また、主にプラズマCVDで作成されるa−
5in膜トランジスタを例に実施例を記述したが、光C
VDやイオンビーム堆積法による半導体薄膜やp−Si
薄膜やS1以外の半導体薄膜でも適用でき有効である。It should be noted that the present invention can achieve more effective effects by combining the embodiments shown in FIGS. 3 and 5 or by combining the embodiments shown in FIGS. 4 and 5. [Effects of the Invention] As described above, With three mask steps (5 n-light development steps), it is possible to provide a thin film transistor for an active matrix display device with good contact characteristics and low cost yield. In addition, a-
Although the embodiment has been described using a 5-inch film transistor as an example, the optical C
Semiconductor thin films and p-Si by VD and ion beam deposition methods
It is also applicable and effective to thin films and semiconductor thin films other than S1.
第1図(al〜(flは、本発明の第1実施例である薄
膜トランジスタの製造工程に沿った平面図、第2図+8
)〜(「)は、それぞれ第1図+al〜iflに対応す
る断面図、第3図tal〜fflは、本発明の第2実施
例である薄膜トランジスタの製造工程に沿った断面図、
第4図(al〜(r)は、本発明の第3実施例である薄
膜トランジスタの製造工程に沿った断面図、第5図(a
+〜te+は、本発明の第4実施例である薄膜トランジ
スタの製造工程に沿った断面図、第6図(5)〜(cl
は、従来の7i膜トランジスタの製造工程に沿った断面
図である。
1 ・−・−絶縁基板
2・−・−ゲート電極
2° −一一−ゲート電極引出し部
3−・−ゲート絶縁膜
4 −高抵抗半導体膜
7・・−低抵抗半導体膜
8−・・・・−ドレイン電極
9−−一−・ソース電極
12−一一一一・金属膜
14−・透明導電膜
以上
出願人 セイコー電子工業株式会社
2′
(a)
第10
第1図
1基役
第3図
第3図
一ノ −ノ
ζノ−ノ
−ノ 、ノ弔5
図Figure 1 (al~(fl) is a plan view along the manufacturing process of the thin film transistor according to the first embodiment of the present invention, Figure 2 +8
) to () are cross-sectional views corresponding to FIG. 1+al to ifl, respectively, and FIG.
4(a) to 4(r) are cross-sectional views along the manufacturing process of a thin film transistor according to a third embodiment of the present invention, and FIG. 5(a)
+ to te+ are cross-sectional views along the manufacturing process of a thin film transistor according to the fourth embodiment of the present invention, and FIGS. 6(5) to (cl
These are cross-sectional views along the manufacturing process of a conventional 7i film transistor. 1 - Insulating substrate 2 - Gate electrode 2° - 11 - Gate electrode extension part 3 - Gate insulating film 4 - High resistance semiconductor film 7 - Low resistance semiconductor film 8 - -・-Drain electrode 9--1-・Source electrode 12-11-1・Metal film 14-・Transparent conductive film Applicant Seiko Electronics Co., Ltd. 2' (a) No. 10 Fig. 1 Base No. 3 Figure 3 - No.
ζ-no
-ノ 、ノ 張5
figure
Claims (5)
第1工程 b)少なくとも前記ゲート電極引出し部の一部をマスク
して、ゲート絶縁膜、高抵抗半導体膜、低抵抗半導体膜
、金属膜を連続して堆積する第2工程 c)少なくとも前記ゲート電極上とゲート電極引出し部
の一部に前記高抵抗半導体膜と低抵抗半導体膜と金属膜
をほぼ同一形状に残す第3工程d)前記金属膜表面の酸
化膜層を除去後、連続して透明導電膜を堆積する第4工
程 e)前記透明導電膜を画素電極を兼ねるソース電極とド
レイン電極配線とゲート電極引出し部に選択的に形成す
る第5工程 f)前記金属膜と低抵抗半導体膜を、前記透明導電膜を
少なくともマスクの一部として選択的に除去する第6工
程とから成る薄膜トランジスタの製造方法。(1) a) First step of selectively forming a gate electrode on an insulating substrate b) At least a part of the gate electrode extension part is masked to form a gate insulating film, a high-resistance semiconductor film, a low-resistance semiconductor film, a second step of continuously depositing metal films; c) a third step of leaving the high-resistance semiconductor film, low-resistance semiconductor film, and metal film in substantially the same shape on at least the gate electrode and a part of the gate electrode extension part; d) ) A fourth step of successively depositing a transparent conductive film after removing the oxide film layer on the surface of the metal film e) Selectively depositing the transparent conductive film on the source electrode, the drain electrode wiring, and the gate electrode extension part that also serves as the pixel electrode f) a sixth step of selectively removing the metal film and the low-resistance semiconductor film, using the transparent conductive film as at least a part of a mask.
ング後、低抵抗半導体膜と高抵抗半導体膜をエッチング
して、金属膜が高抵抗半導体膜と低抵抗半導体膜よりも
小さいパターンになるように再度金属膜をエッチングす
ることを特徴とする特許請求の範囲第1項記載の薄膜ト
ランジスタの製造方法。(2) In the third step, after etching the metal film using the same mask, the low-resistance semiconductor film and the high-resistance semiconductor film are etched so that the metal film has a smaller pattern than the high-resistance semiconductor film and the low-resistance semiconductor film. 2. The method of manufacturing a thin film transistor according to claim 1, further comprising etching the metal film again.
ング後、レジストが変形し、レジストの端部が上記金属
膜の端部よりも外側まで拡がる温度で熱処理して、低抵
抗半導体膜と高抵抗半導体膜をエッチングすることを特
徴とする特許請求の範囲第1項記載の薄膜トランジスタ
の製造方法。(3) In the third step, after etching the metal film using the same mask, heat treatment is performed at a temperature that deforms the resist and causes the edges of the resist to expand beyond the edges of the metal film, forming a low-resistance semiconductor film and a high-resistance semiconductor film. A method for manufacturing a thin film transistor according to claim 1, characterized in that a resistive semiconductor film is etched.
形する温度で熱処理後、金属膜と低抵抗半導体膜を選択
的に除去することを特徴とする特許請求の範囲第1項記
載の薄膜トランジスタの製造方法。(4) In the sixth step, the metal film and the low-resistance semiconductor film are selectively removed after heat treatment at a temperature at which the resist is deformed after the end of the fifth step. manufacturing method.
記低抵抗半導体膜の膜厚は200Å以下であることを特
徴とする特許請求の範囲第1項記載の薄膜トランジスタ
の製造方法。(5) The method for manufacturing a thin film transistor according to claim 1, wherein the high-resistance semiconductor film has a thickness of 500 Å or less, and the low-resistance semiconductor film has a thickness of 200 Å or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60271987A JPH0618215B2 (en) | 1985-12-03 | 1985-12-03 | Method of manufacturing thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60271987A JPH0618215B2 (en) | 1985-12-03 | 1985-12-03 | Method of manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62131578A true JPS62131578A (en) | 1987-06-13 |
| JPH0618215B2 JPH0618215B2 (en) | 1994-03-09 |
Family
ID=17507569
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60271987A Expired - Lifetime JPH0618215B2 (en) | 1985-12-03 | 1985-12-03 | Method of manufacturing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0618215B2 (en) |
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63316084A (en) * | 1987-06-19 | 1988-12-23 | 株式会社日立製作所 | Method for manufacturing thin film active device array |
| JPS63316470A (en) * | 1987-06-19 | 1988-12-23 | Alps Electric Co Ltd | Manufacture of thin film transistor |
| JPH01102433A (en) * | 1987-10-15 | 1989-04-20 | Sharp Corp | Electrode structure of liquid crystal panel |
| JPH01237622A (en) * | 1988-03-18 | 1989-09-22 | Seiko Epson Corp | Method for manufacturing thin film patterns |
| JPH01259565A (en) * | 1988-04-11 | 1989-10-17 | Hitachi Ltd | Thin film transistor and its manufacturing method |
| JPH04324831A (en) * | 1991-04-25 | 1992-11-13 | Sanyo Electric Co Ltd | Manufacture of liquid crystal display device |
| JPH09197433A (en) * | 1995-12-30 | 1997-07-31 | Samsung Electron Co Ltd | Manufacturing method of liquid crystal display device |
| US5686326A (en) * | 1985-08-05 | 1997-11-11 | Canon Kabushiki Kaisha | Method of making thin film transistor |
| JP2000101091A (en) * | 1998-09-28 | 2000-04-07 | Sharp Corp | Thin film transistor |
| JP2001142093A (en) * | 1999-11-11 | 2001-05-25 | Nec Corp | Active matrix substrate for liquid crystal display device and method for manufacturing the same |
| JP2001264804A (en) * | 2000-03-16 | 2001-09-26 | Semiconductor Energy Lab Co Ltd | Liquid crystal display device and manufacturing method thereof |
| US6667778B1 (en) | 1995-07-25 | 2003-12-23 | Hitachi, Ltd. | Liquid crystal display device having a transparent conductive film formed on an insulating film |
| US6839098B2 (en) | 1987-06-10 | 2005-01-04 | Hitachi, Ltd. | TFT active matrix liquid crystal display devices |
| WO2005047966A1 (en) * | 2003-11-14 | 2005-05-26 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and manufacturing method thereof |
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| US6992744B2 (en) | 1987-06-10 | 2006-01-31 | Hitachi, Ltd. | TFT active matrix liquid crystal display devices |
| US6839098B2 (en) | 1987-06-10 | 2005-01-04 | Hitachi, Ltd. | TFT active matrix liquid crystal display devices |
| US7450210B2 (en) | 1987-06-10 | 2008-11-11 | Hitachi, Ltd. | TFT active matrix liquid crystal display devices |
| US7196762B2 (en) | 1987-06-10 | 2007-03-27 | Hitachi, Ltd. | TFT active matrix liquid crystal display devices |
| JPS63316470A (en) * | 1987-06-19 | 1988-12-23 | Alps Electric Co Ltd | Manufacture of thin film transistor |
| JPS63316084A (en) * | 1987-06-19 | 1988-12-23 | 株式会社日立製作所 | Method for manufacturing thin film active device array |
| JPH01102433A (en) * | 1987-10-15 | 1989-04-20 | Sharp Corp | Electrode structure of liquid crystal panel |
| JPH01237622A (en) * | 1988-03-18 | 1989-09-22 | Seiko Epson Corp | Method for manufacturing thin film patterns |
| JPH01259565A (en) * | 1988-04-11 | 1989-10-17 | Hitachi Ltd | Thin film transistor and its manufacturing method |
| JPH04324831A (en) * | 1991-04-25 | 1992-11-13 | Sanyo Electric Co Ltd | Manufacture of liquid crystal display device |
| US6667778B1 (en) | 1995-07-25 | 2003-12-23 | Hitachi, Ltd. | Liquid crystal display device having a transparent conductive film formed on an insulating film |
| JPH09197433A (en) * | 1995-12-30 | 1997-07-31 | Samsung Electron Co Ltd | Manufacturing method of liquid crystal display device |
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| US8054430B2 (en) | 1998-05-19 | 2011-11-08 | Samsung Electronics Co., Ltd. | Liquid crystal display having wide viewing angle |
| US8711309B2 (en) | 1998-05-19 | 2014-04-29 | Samsung Display Co., Ltd. | Liquid crystal display having wide viewing angle |
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| US9368514B2 (en) | 2000-03-08 | 2016-06-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US9786687B2 (en) | 2000-03-08 | 2017-10-10 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| JP2001264804A (en) * | 2000-03-16 | 2001-09-26 | Semiconductor Energy Lab Co Ltd | Liquid crystal display device and manufacturing method thereof |
| US9298056B2 (en) | 2000-03-16 | 2016-03-29 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and method of manufacturing the same |
| US9048146B2 (en) | 2000-05-09 | 2015-06-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US9429807B2 (en) | 2000-05-09 | 2016-08-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| WO2005047966A1 (en) * | 2003-11-14 | 2005-05-26 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and manufacturing method thereof |
| US7499117B2 (en) | 2003-11-14 | 2009-03-03 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0618215B2 (en) | 1994-03-09 |
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