JPS62128544A - Gate array type semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of sedentary use] The unexploited BA relates to an ECL gate array type semicircular integrated circuit device.

[Conventional technology]

A conventional ECL gate array has an internal cell group 16. for forming the necessary logic circuit, as shown in the fourth column. Performs level conversion between external circuit and ECL gate array.
Irukaba 7a Group” 7. A power generation circuit 1 for supplying various kinds of power to the output buffer group 18 and the circular portion of the gate array.
The main issue in gate array design is how to efficiently allocate the power consumption of each part.
It is also There is a point in the process being used where the Evaspeed power supply becomes saturated, and even if the power consumption is increased more than necessary, the effect freezes and expectations are lost. . Especially ECL
Since the gate array of the system often has a steep external load of 50 to 70 Ω, it is necessary to design the output capacitor to have a very low resistance. It is common to use swords. - As an example, Fig. 6 shows simulation results of the magnetic current of the current switch shown in No. 5, and the rise and fall times of the output. In this example, the current of the current switch rises to about 4mA,
The effect of shortening the rise time can be expected to be considerable, but if it exceeds 4 mA, the effect will not be so great, and it will be disadvantageous in terms of power consumption. In the conventional design, the output buffers were all of the same shape and regularly arranged δn, so in the above example, the rise and fall times were 220 ps using a current switch current of 4FFIA from the results shown in Figure 6. Is it normal to design a specific output buffer? In particular, in response to the request for #I luck, there is also a gate array called the subcurrent switching method, which is designed so that the current switch current is 2 times the current switch current. However, if the circuit is made to have all the fusibility in this way, it is often uneconomical because elements that are rarely used usually require a lot of effort. In addition, with conventional current switching type, at most twice as much current flows, but if a particular pin requires particularly high speed, such as the clock of the entire system, the current can be increased further. I want to use Yuko to the limit of her performance. Conventional ECL type gauge type gauge arrays were not suitable for this type of use.

[Problems to be solved by the invention] Since the conventional ECL type gauge array output buffer mentioned above is not designed to allow the flow to flow in the "RL flow" up to the performance limit of the receiver, it is especially difficult to control the entire system. When such a high-speed clock is used inside the gate array and taken out to the outside, the insufficient speed of the output buffer sometimes becomes a problem [Means for solving the problem] ECL gate array of the present invention type semiconductor circuit device r1j
At t, the output of t￥f to output 1g to the outside (
The output power consumption of +tq is also large, and it is a characteristic that it is placed in the immediate vicinity of the 'wL source pad.

〔Example〕

Next, the present invention will be explained with reference to the drawings. 1st
Figure 1 shows an example of an ECL gate array according to an embodiment of the present invention, in which internal cells constituting an arbitrary logic circuit 1, relatively consuming (low power input or output buffer 2)
Each of the various oscilloscope generator circuits 3 and the large output power consumption circuit 7 in which the current is upstreamed until the element performance is fully brought out.
It consists of A4. When using this ECL gate array, you can control other high speed systems.

Use output buffers with high power consumption. This output buffer has a sufficiently low output impedance even for heavy loads, so there is no shortage of driving capability. 1 Usually, the number of signal pins that require special high-speed signal processing is 1 to 2.
Since it can be considered as a book, in this embodiment, two output buffers with large driving capacity are arranged at points symmetrical with respect to the center of the chip.

Next, a second embodiment of the present invention will be described with reference to FIG. In FIG. 2, various power generation circuits are omitted. In the figure, 5 is an internal cell, 6 is an output buffer 7 with relatively low power consumption, 7 is an output buffer with a large drive capacity and high voltage consumption, and 8 is a GND (OV) pad of the WCL circuit. In this embodiment, an output buffer with high power consumption is placed in the immediate vicinity of the GND pad.Furthermore,
The ECL gate eye shown in FIG. 842 is mounted in the next package shown in FIG. 3 and used. In the same figure,
The 9flECL gate array 10 is made of a dielectric material such as ceramic, 11 is a GND plane for the microstrip line, 12 is a signal line for the microstrip line, and the GND pad 8 shown in FIG. 2 is connected through a through hole 13. It is connected to GNDK of an external circuit via a conductor 14 connected to a GND plane 11. therefore.

The package shown in FIG. 3 has a microstrip line structure as a whole. but.

The GND plane tends to be incomplete as a GND plane because it is connected to the GND of the external circuit at the end of the package, as shown by lead 15 in Figure 3 (a) and (b). , 14 is connected to the GNυ plane by a through hole, so the GND plane near the conductor 14 is the most reinforced in the package.
ing. Therefore, the microstrip line closest to 14 is also the most ideal. 9% from the ECL gate array through a power-hungry output buffer.
The fastest signal is taken out to the outside via 12 conductors. Furthermore, as shown above, the conductor numbered 12 is the most ideal microstrip line in the package, so the highest speed signal can ideally be taken out to the outside.

〔Effect of the invention〕

As explained above, the present invention provides an ECL gate array in which the power consumption of a specific output buffer is made larger than that of other output buffers to increase the drive capability.
The pigeon speed No. 16 can be processed efficiently, and by self-molding in the vicinity of the above output buffer 'kGND pad, when mounted on a package with a microstrip line structure, the speed control No. 16 can be processed in a nearly ideal state. It has the effect of being able to be taken out.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the ECL gate array integrated circuit according to the first embodiment of the present invention, FIG. 2 is a diagram showing the entire ECL gate array integrated circuit according to the second embodiment of the present invention, and FIG. (a)
, (b) is the ECL game 1 of the second embodiment of the present invention.
Figure 4 is a cross-sectional view showing a package with a microstrip line structure for mounting an array integrated circuit, and Figure 4 is a diagram showing a conventional ECL gate array integrated circuit.
The figure shows an output buffer using a current switch.
The sixth figure is a diagram showing simulation results of the rise time V and fall time of the output buffer in FIG. 5. In the figure, 1...internal cell, 2...input or output buffer with relatively low power consumption, 3...power generation circuit. 4... Output buffer with large power consumption, 5...
...Internal cell, 6...Input or output buffer with relatively low power consumption, 7...Output buffer with large power consumption, 8...GND pad ,9
...ECL gate 71/I, 10...
Dielectric, 11...GND brain, 12...
...Microstrip line track, 13...
・Through hole, 14...Conductor, 15...
...Read, 16...Internal cell, 17...
...Input buffer, 18...Output buffer, 1
9...Power generation circuit. (bn(I) Figure 3 Figure 4!; Figure

Claims (2)

[Claims] (1) EC equipped with an output buffer that outputs signals to the outside
In an L gate array, the power consumption of a particular output buffer is larger than that of other output buffers.
CL gate array type semiconductor integrated circuit device. (2) The gate array type according to claim (1), wherein the output buffer whose power consumption is larger than that of other output buffers is arranged in the immediate vicinity of a power supply pad in an ECL gate. Semiconductor integrated circuit device.