JPS62126862A - Inner voltage converter circuit - Google Patents

Abstract

PURPOSE:To output a constant voltage lower than a power source voltage or a power source voltage by producing a conversion output in combination of a depletion type MISFET and an enhancement type MISFET. CONSTITUTION:A reference voltage generator 1 outputs a constant voltage VL lower than a power source voltage VCC. The voltage VL is applied to the gate of a depletion MISFETQ0, and a voltage V1 is applied to its drain. The source of the MISFETQ1 is connected with the gate of an enhancement type MISFETQ1, and a power source voltage VCC is applied to its drain. A conversion output V1 is produced from the source of the MISFETQ1. When the voltage VCC is high, it outputs a constant voltage lower than the VCC, and when the voltage VCC is low, it outputs the power source voltage VCC.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to voltage conversion circuits used within integrated circuits.

(Prior Art) Due to the miniaturization of transistors in semiconductor integrated circuits as the scale increases, if the operating voltage is kept constant at 5V, there will be a problem of characteristic deterioration due to hot carrier effects, drain breakdown, etc. For this reason, it is necessary to lower the operating voltage, but there is a strong demand to maintain the 5■ single power supply standard for power supply voltage in order to maintain compatibility with previous products. Therefore, as a compromise solution that satisfies both requirements, the external power supply voltage of the integrated circuit chip is maintained at 5V, and a voltage conversion circuit is provided inside the chip to reduce the operating voltage inside the chip to 5V.
A method is adopted in which the value is set to be less than or equal to v.

As a conventional example of such a voltage conversion circuit inside a chip, for example, the 1984 IEEE International Solid State Circuits Conference held in February 1984
RNATIONAL 5OLID-8TATE C
IRCUITS CONFERENCE) Digest of Technical Papers (ISSCCDIGE)
ST OF TECHNICAL PA-.

PER8) pages 282-283 (distributed at the same time at the February 1984 conference).
mental IMb DRAM with 0n-Ch
This method was introduced in a paper by Kiyoo Itoh et al. titled ip Voltage Limlter'') J.

The voltage conversion circuit introduced in the above paper is shown in FIG. 6, and the converted voltage characteristics are shown in FIG. 7. The conversion circuit consists only of enhancement type MO8FET, and the conversion output voltage VL
is determined by the conductance of MISFETQ6 and Q7. In FIG. 7 showing the converted voltage characteristics, the horizontal axis represents the chip power supply voltage VCC, and the vertical axis represents the output voltage VL. In this conventional example, even if the power supply voltage VCC changes around 5V, the output voltage VL is always fixed around 3.7V, but when vcc becomes 4V or less,
The constant voltage property of L collapses, and VL always becomes a voltage approximately IV lower than vcc.

(Problems to be Solved by the Invention) By the way, the voltage conversion characteristics required for an on-chip voltage conversion circuit that prevents deterioration of transistor characteristics are the power supply voltage VC.
When C is around 5V, the converted voltage VL is constant around 4V, whereas when VCC is 4V or less, it is desirable that the output voltage VI is as close to the constant voltage (4V) as possible. As in the conventional example, when VCC is 4v or less, vL
Reducing the voltage below ■cc will unnecessarily reduce the speed of the transistor and also lead to a reduction in the operating margin. In other words, when VCC is 4V or less, it is ideal to perform voltage conversion so that the voltage of vL matches Vcc, and problems related to deterioration of transistor characteristics do not occur.

An object of the present invention is to output a constant voltage from the power supply voltage VCC when the power supply voltage VCC is a high voltage.
The object of the present invention is to provide an internal voltage conversion circuit that outputs the power supply voltage VCC when C is a low voltage.

(Means for Solving the Problem) The internal voltage conversion circuit of the present invention includes a reference voltage generation circuit that outputs a constant voltage lower than the power supply voltage, and a first voltage conversion circuit that applies the output voltage of the reference voltage generation circuit to the gate. a first depletion type MISFET connecting a voltage source to its drain;
A first . This is an internal voltage conversion circuit characterized by comprising an enhancement type MISFET.

(Function) The internal voltage conversion circuit according to the present invention includes a reference voltage generation circuit that outputs a constant voltage between power supply voltage VCC and ground voltage, and a reference voltage generation circuit that outputs a constant voltage between power supply voltage VCC and ground voltage.
A depletion type MISFET has a drain connected to a first voltage source having a voltage level higher than the threshold voltage of the enhancement type MISFET, and a power supply voltage vcc is applied to the drain of the depletion type MISFET. It consists of an enhancement type MISFET whose source is connected to its gate and whose voltage conversion output terminal is connected to its source. Depletion type MISF
If the threshold voltage of ET is Vth (D), Vth (D) is a negative value in the case of n-channel, so this MISFE
When T operates in the triode region, its source output voltage is VL + 1Vth(D)l, but this MISF
When the ET operates in the diode region, its source output voltage is equal to the drain voltage. As a result, the enhancement type MISFE where these voltages are applied to the gate
The source output voltage of T has a threshold voltage of Vth(E), and when this MISFET operates in the triode region,
The source output voltage is VI, +1Vth(D)l-Vth(
E) On the other hand, when the cono MISFET operates in the triode region, its source output voltage is equal to the drain voltage, and the power supply voltage vcc tonal. Tatoeha, Vj=2
V, Vth(D)=-3V.

Vth (E) = IV c: If selected, when the power supply voltage vcc is 4 V or more, VL + 1 Vth (D) l - Vth (
The present invention provides an internal voltage conversion circuit that outputs E)=4V while outputting Vcc when Vcc is 4V or less.

The internal voltage conversion circuit of the present invention is particularly suitable for use in an integrated memory, using the source output of a depletion type MISFET as a word line drive voltage source, and converting the source output of a depletion type MISFET into a word line drive voltage source.
By using the source output of T as the bit line drive voltage source, it is possible to prevent the breakdown voltage from deteriorating due to miniaturization of transistors around the memory cell against high voltage vcc. or,
In general, reference voltage generation circuits have the disadvantage of consuming power because DC current always flows through them. By increasing the size and current capacity, an internal voltage conversion circuit with low power consumption and large current supply capability can be realized.

(Examples) Hereinafter, in order to better understand the present invention, the present invention will be explained using examples. FIG. 1 is an embodiment showing the basic circuit configuration of an internal voltage conversion circuit according to the present invention. The output voltage VL of the reference voltage generation circuit 1 is a constant voltage between the power supply voltage VCC and the ground voltage, and has a characteristic that, for example, when the power supply voltage VCC is 2V or more, a constant voltage of VL - 2V is output. has. Depletion type n-channel MISFET
QO is the output voltage vL of the reference voltage generation circuit at the gate.
is applied, the drain is connected to the first voltage source v1, and the source is connected to the internal terminal v2. In addition, the enhancement type n-channel MISFET QI has the power supply voltage VCC applied to its drain, and the internal terminal v2 applied to its gate.
However, the output terminal vI of the internal voltage conversion circuit is connected to the source. Here, depletion type MISFE
TQO-E value voltage Vth (D) is -3v, enhancement type MISFET (7) threshold voltage Vth (E) is I
VI: Add 1 and make the first voltage source voltage v1 1.5 of VCC
The output voltage VI and internal voltage 2 when doubled have characteristics that change as shown in FIG. 2 with respect to fluctuations in VCC. In FIG. 2, the horizontal axis shows the power supply voltage VCC, and the vertical axis shows the voltages of VL, VI, and V2°VCC. In the figure,
The solid line shows the converted output voltage vI, the one-dot chain line shows the reference voltage VL, the two-dot chain line shows the internal voltage v2, and the broken line shows the power supply voltage VCC. When voltage v1 is 5v or more, VL is 2
v, depletion type MISFET QO no Vth (
D) MISFET QO (7) because there is a 3V voltage
Only the V-X follower voltage is output.

In other words, the internal voltage v2 becomes a constant voltage of 2V - (-3V) = 5V. When vl is 5v or less, MISFE
The drain voltage v1 of TQO is equal to the source follower voltage (
5v) or less, so v2 becomes equal to vl. vl
If the voltage is set to 1.5 times VCC, the internal voltage v2
With respect to VCC, the voltage of vCc that changes from a constant voltage of 5V to vl is approximately 3.3V. As a result, when the voltage conversion output terminal is MISFETQI + 7) V - Sumi pressure vI, and vcc is 4V or more, MISFETQI operates in the triode region, so 5V - Vth (E) = 4
Vi: On the other hand, when VCC is 4v or less, M
Since ISFETQI operates in the triode region, it is equal to the drain voltage vcc. Therefore, this embodiment becomes an internal voltage conversion circuit that outputs a constant voltage lower than VCC for VCC of 4V or more, while outputting VCC itself for VCC of 4V or less.

In this example, the converted output voltage veva, 2V (7) when vcc is a high voltage, the reference voltage vLhuman-vnovth(D
) and 1v of Vth(E), but this combination may be freely changed.

FIG. 3 shows an embodiment of the reference voltage generation circuit.

The depletion type MISFET Q2 has its drain connected to the power supply voltage Vcc, and its gate and source connected to the output terminal VL. The depletion type MISFET Q3 has its drain connected to the output terminal VL, and its gate and source connected to the terminal 2. The enhancement type MISFET Q4 has its drain and gate connected to the terminal 21, and its source connected to the ground power supply GND.

The reference voltage generation circuit of this embodiment applies the IJ value voltage of MISFETQ4 to Vth(E).
2. Q3. By appropriately changing the conductance ratio of Q4, the output voltage VL can be set to any voltage between VCC and Vth(E). Moreover, since the gate and source of MISFETQ2 are connected, MISFETQ2 functions as a constant current source, so that the output voltage VL can be kept constant regardless of fluctuations in the power supply voltage VCC. For example, MISFETQ2. Q3. By setting the conductance ratio of Q4, when Vcc is 2v or more, an output voltage VL of approximately 2v can be obtained regardless of Vcc. When VCC is 2v or less, vL decreases with VCC.

By using the reference voltage generation circuit of this embodiment in the internal voltage conversion circuit shown in FIG. 1, an internal voltage conversion circuit having voltage conversion characteristics as shown in FIG. 2 can be realized. In other words, when the TL source voltage VCC is 4v or more, the conversion output is obtained by converting the output voltage VL of 2v of the reference voltage generation circuit shown in FIG. The voltage is 2V-(-3V)-1V=4V, whereas when VCC is 4V or less, the internal voltage conversion circuit outputs VCC itself. In addition, the reference voltage generation circuit is configured only with MISFETs with small current capacity, and the enhancement type MISFET QI is replaced by MIS with large current capacity.
By using FETs, it is possible to realize an internal voltage conversion circuit that has a large current supply capability despite having low DC power consumption. It goes without saying that any constant voltage generating circuit other than the embodiment shown in FIG. 3 can be used as the reference voltage generating circuit.

FIG. 4 shows an example of a generating circuit for the first voltage source V1.

The enhancement type MISFET Q5 has its drain connected to the power supply voltage ■cc, its gate connected to the first clock signal line Φ1,
The sources are respectively connected to the output terminal v1.

The second clock signal line φ2 is coupled to the output terminal v1 via the boot capacitor tcB. FIG. 5 shows the drive clock signal waveform and output voltage waveform of this circuit. Tarock signal line φ1
The voltage of VCC+2Vth(E
) and falls to VCC at time t2. During this time, the voltage at the output terminal v1 is charged to VCC. Next, when the voltage of the clock signal Φ2 increases from Ov to VCC at time t3 and decreases to Ov at time 4, the voltage at the output terminal v1 becomes a constant voltage equal to or higher than VCC between times t3 and t4. By appropriately setting the size of the put volume flcB, v
It is easy to set the high level voltage of l to 1.5 times the value of vcc.

By using the voltage generation circuit of this embodiment as the first voltage source of the internal voltage conversion circuit shown in FIG.
An internal voltage conversion circuit having voltage conversion characteristics as shown in FIG. 2 can be realized only between and -.

A conversion circuit having such dynamic voltage conversion characteristics is particularly useful for integrated memories, etc., by converting the internal terminal v2 into a word line driving voltage source and making the output terminal vl a bit line driving voltage source. This method performs voltage conversion only when the memory is in operation, and can prevent deterioration of the withstand voltage of fine transistors around the memory cell, making it very useful in practice.

It goes without saying that any circuit other than the embodiment shown in FIG. 4 can be used as the voltage generating circuit for vl. Furthermore, by using the reference voltage generation circuit of FIG. 3 and the v1 voltage generation circuit of FIG. 4 in the internal voltage conversion circuit shown in FIG. 1, a more practical internal voltage conversion circuit can be realized.

Although the above description has been made using an n-channel MIS transistor, a p-channel MIS transistor may also be used.

(Effects of the Invention) As explained above, according to the present invention, compared to the conventional example, when the power supply voltage An internal voltage conversion circuit that outputs voltage can be realized, and while the deterioration of withstand voltage caused by miniaturization of transistors is prevented for high voltage VCC, the converted output voltage is VCC for low voltage VCC. Therefore, the conversion circuit has the advantage of not impairing the speed of the transistor. Also, the constant voltage level output when VCC is high is the output voltage VL of the reference voltage generation circuit and V of the depletion type MISFET QO.
th(D) and enhancement type MISFETQ1nov
Since it is determined by th(E) no 3-horn haramometer, there is an advantage that the degree of freedom in circuit design increases and it is easy to design.

[Brief explanation of drawings]

FIG. 1 is an embodiment showing the basic circuit configuration of the internal voltage conversion circuit of the present invention, FIG. 2 is a diagram showing the converted voltage characteristics of the embodiment of FIG. 1, and FIG. 3 is a diagram showing the internal voltage conversion circuit of the present invention. This is one embodiment of a reference voltage generation circuit used in a voltage conversion circuit. Fourth
5 and 5 are waveform diagrams for explaining an embodiment of the first voltage source generating circuit and its operation, respectively. FIGS. 6 and 7 are diagrams for explaining a conventional internal voltage conversion circuit and its voltage conversion characteristics, respectively. The symbols in the diagram are QO, Q2. Q3 is a depletion type MISFET, Ql, Q4. Q5. Q6. Q7 is an enhancement type MISFET, 1 is a reference voltage generation circuit, 2 is a terminal, vcc is a power supply terminal or power supply voltage, VL is a reference voltage output terminal or output voltage, vl is a conversion output terminal or output voltage, GND is the ground power supply, vl is the first voltage source or its voltage, v2 is the internal terminal or its voltage, Φ1. Φ2 represents a clock signal or a clock signal line, cB represents a boot capacitance, and t represents time. 'A-1 Figure 1 Two reference voltage generation low ■2: Internal terminal or its voltage low 2 Figure power supply voltage ■. c(■) 73 Figure GND: Ground power supply 2: Terminal Q2. Q3: Depletion type MISFETQ4
: Enhancement type MISFET7I-4 Figure CB: Boot capacity O 5 mouth tl ↑2 ↑3 ↑4t+, tz
, ↑-14: Time 76 Figure ND O 7 Figure power supply voltage vCc■)

Claims (1)

[Claims] a reference voltage generation circuit that outputs a constant voltage lower than the power supply voltage; and applying the output voltage of the reference voltage generation circuit to the gate;
a first depletion type MISFET connecting the first voltage source to the drain; and applying a power supply voltage to the drain;
An internal voltage conversion circuit comprising: a first enhancement type MISFET whose gate is connected to the source of the first depletion type MISFET; and a first enhancement type MISFET whose voltage conversion output terminal is connected to its source.