JPS62125738A - Communication control unit - Google Patents

Abstract

PURPOSE:To improve largely the data transfer capability by transferring a data while using transmission/reception control independently and operating the scan processor in parallel. CONSTITUTION:A transmission control processor 12 and a reception control processor 13 apply processing respectively and a signal representing the processing state of both the processors is sent to a ready signal generating circuit 18 during the processing. Further, the initial setting to a line for the transmission control processor 12 or the reception control processor 13 can be applied prior to the scanning of the scan processor 10 or at a proper scanning section of the scan processor 10. Since the transmission control processor 12 and the reception control processor 13 are operated in parallel during the operation of the scan processor 10 in this way, the processing capability of the entire processors is improved largely.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a line processing device that is one element of a communication processing device that connects an information processing device and a communication line.

〔overview〕

In a line processing device that is equipped with a data serial/parallel conversion circuit and a control processor between the communication line side and the device side, this processor is used as a scan processor that scans parallel data processing requests and a transmission control that controls transmission. The data transfer capability is improved by dividing the system into a processor and a reception control processor that performs reception control.

[Conventional technology]

FIG. 2 is a diagram showing an example of the configuration of a communication processing device. Connected to a host device via a host interface unit 1,
The plurality of communication lines 6 are connected to the line control device 4. The host device (not shown) is, for example, a large information processing device, and the communication line is, for example, a dedicated line for communicating serial data with a terminal device (not shown). This communication processing device is constructed by connecting the upper interface section 1, the processor section 2, the buffer memory section 3, and the line control device 4 through an internal buffer 5.

The line control device 4 is further provided with a processor means therein in addition to the processor section 2, and this internal processor means controls the interface between the communication line 6 and the internal bus 5, and also performs processing request scanning for the communication line 6. are doing.

In the conventional device, this internal processor means is constituted by one processor, which accepts commands from the processor section 2, sends the responses to the processor section 2, processes the communication line 6, and performs data transfer or processing according to the results. It reported non-identical yI to the processor unit 2.

[Problem that the invention seeks to solve]

In such a conventional device, since the line control device 4 has only one processor means, the load may be concentrated on that processor means, and the number of lines that can be accommodated or the number of lines that can be accommodated is limited by its processing capacity. was to be done.

The present invention solves this problem, and aims to provide a line processing device that can improve data transfer ability regardless of the processing ability of the processor means.

[Means for solving problems]

The present invention includes a parallel-to-serial conversion circuit that is connected to a plurality of communication lines and mutually converts serial data on the communication lines and parallel data on the device side, and connects an internal bus of a communication processing device to the communication lines. In a line control device including a processor means for controlling an interface and scanning the parallel data processing request, the processor means includes a scan processor for scanning the parallel data processing request, and a transmission interface of the interface. a transmission control processor for controlling a transmission control processor; and a reception control processor for controlling a reception interface of the interfaces, the means for supplying scan information from the scan processor to the transmission control processor and the reception control processor; and means for providing the operating status of the control processor and the reception control processor to the scan processor.

[For production]

A scan processor scans parallel data on each communication line, updates scan addresses, transfers data, and processes address counts, etc., and a transmission control processor and a reception control processor control the transmission interface and reception interface, respectively. Scan information is given to the control processor and the reception control processor, and the scan processor is notified of the operating status of each control processor, so that the plurality of processors can work together and operate independently. Therefore, the data transfer ability is dramatically improved, and the number of lines and communication speed are no longer limited by the ability of the processor means.

〔Example〕

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention. This device is a diagram showing in detail the configuration of the line control device 4 shown in FIG. 2. That is, the internal bus 5 of the communication processing device,
This is a device inserted between a large number of communication lines 6.

This line control device 4 includes a scan processor 10, a scan address generation circuit 11 that provides scan addresses to the scan processor 10, a transmission control processor 12 that controls a transmission interface, and a reception control processor 13 that controls a reception interface. Be prepared. Each of the processors 10, 12 and 13 is connected to an internal bus 5, which connects to a higher-level device, and an internal bus 15, which connects to a lower-level device.

Each communication line 6 is connected to a serial/parallel conversion circuit 14 that converts serial data on the communication line to parallel data on the device side, and converts parallel data on the device side to serial data on the communication line.

Furthermore, the address information generated by the scan address generation circuit 11 and the scan results are transmitted to the transmission control processor 12.
and the reception control processor 13. Also, the operating state of the transmission control processor 12 and the reception control processor 13, that is, the operation status of the two processors 12 and 13.
A ready signal generating circuit 18 is provided for supplying a ready signal to the scan processor 10 when the control is completed and the next control becomes possible.

Next, the operation of this device will be explained. First, the operation of the entire communication processing device shown in FIG. 2 will be explained. When transmitting to the communication line 6, the upper interface unit 1 receives a transmission request from a higher-level device (not shown) and writes all of the transmitted data into the buffer memory 3 via the internal bus 5. Next, the upper interface section 1 reports to the processor section 2 via the internal hub 5 that the transmission data has been written to the buffer memory section 3. The processor section 2 is
A state in which communication is possible is confirmed from the line control device 4 with a communication processing device on the other side (not shown) connected to the communication line 6. Thereafter, a command to instruct the line control device 4 to transmit is sent via the internal lotus 5.

Thereby, the line control device 4 sequentially reads out the transmission data from the buffer memory unit 3, converts it into serial data, and sends it out on the line. When the data transfer termination condition occurs, the line control device 4 transfers the data to the processor section 2 via the internal bus 5.
Report this as a response.

When performing reception, the processor unit 2 sends a command to the line control device 4 via the internal bus 5 to instruct the receive (i-enabled state).Then, the line control device 4 receives the received data from the line, Convert to parallel data and store in buffer memory section 3
Write the received data to.

When the data transfer termination condition occurs, the line control device 4 reports the result to the processor unit 2 via the internal bus 5 as a response. When all the data is stored in the buffer memory section 3, the processor section 2 instructs the higher-level interface section 1 via the internal bus 5 to write the data on the buffer memory section 3 to a higher-level device (not shown). .

As a result, the higher-level interface section 1 transfers the received 1g data to the higher-level device via the internal bus 5 and the interface bus 6, and reports the same to the processor section 2 after the transfer is completed.

During the above operations, the processor unit 2 performs processing such as error checking as determined by the protocol when the transmitted and received data passes through the buffer memory unit 3.

Next, the operation of the line control device 4 of this embodiment shown in FIG. 1 will be explained. First, the scan processor 10 starts with the processor section 2.
The receiver receives a command from the internal bus 5 indicating the line address to be scanned. The scan address generation circuit 11 is initialized. When the scan processor 10 receives a command to instruct transmission for each line, it causes the transmission control processor 12 to perform initial setting operations including setting the valid flag of the line, setting the start address of the transmission data in the buffer memory section 3, etc. . Further, when the scan processor 10 receives an instruction to enable reception for each line, the reception control processor 13 sets the valid flag of the line, sets the reception data storage start address of the buffer memory section 3,
Performs initial setting operations, including initialization.

The scan processor 10 reads and holds the transmission/reception processing request from the parallel/serial conversion circuit 14 designated by the scan address generation circuit 11, and activates the transmission control processor 12 and the reception control processor 13. As a result, the transmission control processor 12 executes the corresponding process when the valid flag of the line specified by the scan address generation circuit 11 is set and the transmission processing request content read by the scan processor 10 is significant. do. If the processing request is a request to transfer transmission data, the transmission control processor 12 transmits data to the buffer memory held in the transmission control processor 12 via the internal bus 5, the parallel-to-serial conversion circuit 14, and the internal bus 15. Part 3
The data indicated by the address is transferred to the parallel-to-serial conversion circuit 14. Thereafter, the transmission control processor 12 performs post-processing such as updating the transmission data address in the buffer memory section 3. Next, the transmission control processor 12 stores the results of processing the transmission processing request in the transmission control processor 12 .

When the reception control processor 13 is activated by the scan processor 10, the valid flag of the line specified by the scan address generation circuit 11 is set, and the scan processor 13 operates similarly to the operation of the transmission control processor 12. If the content of the reception processing request read from 10 is significant, the corresponding processing is executed. After the processing is completed, the reception control processor section 3 retains the results of processing the reception processing request.

As described above, the transmission control processor 12 and the reception control processor 13 each perform processing, but during this processing, both processors send a signal indicating that processing is in progress to the ready signal generation circuit 18, and when the processing is completed, Then, the signal indicating that the processing is in progress is inverted to set it to the ready state.

When neither signal from both processors is being processed, the ready signal generation circuit 18 sets the ready signal to a ready state and sends it to the scan processor 10.

When scan processor 10 detects this ready state, it reads out the processing results held in transmission control processor 12 and reception control processor 13, respectively. If this processing result indicates the normal completion of the transmission/reception data transfer or the occurrence of an error, the scan processor 10 creates a response and reports it to the higher-level processor section 2 via the internal bus 5.

Next, the scan processor 10 instructs the scan address generation circuit 11 to update the scan address and repeats the above operation. Initial settings for a certain line of the transmission control processor 12 or the reception control processor 13 may be performed prior to the scan operation of the scan processor 10, and this processing setting operation is performed when the scan processor 10 sets appropriate scan boundaries. You can go there.

In this way, the transmission control processor 12 and the reception control processor 13 can operate in parallel while the scan processor 10 is operating, so the processing capacity of the entire processor is greatly improved.

〔Effect of the invention〕

As explained above, according to the present invention, line control processing is distributed to the scan processor and the transmission control and reception control processors that mainly perform data transfer, and the transmission control and reception control independently transfer data. You can also
Since it can operate in parallel with the scan processor, data transfer capability is greatly improved. Furthermore, since each processor requires a small load, the device can be constructed using inexpensive integrated circuits.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a line control device according to an embodiment of the present invention. FIG. 2 is a block configuration diagram showing an example of the configuration of a communication processing device including a line control device according to the present invention. DESCRIPTION OF SYMBOLS 1... Upper interface part, 2... Processor part, 3... Buffer memory part, 4... Line control device, 5... Internal bus, 6... Communication line, 10... Scan Processor, 11... Scan address generation circuit, 12... Transmission control processor, 13... Reception control processor, 14... Parallel-serial conversion circuit, 15...
- Internal bus, 18... Ready signal generation circuit. Patent applicant: NEC Corporation, agent: Naotaka Ide, -゛.

Claims (1)

[Claims] (1) A parallel-to-serial conversion circuit that is connected to multiple communication lines and mutually converts serial data on the communication lines and parallel data on the device side, and provides an interface between the internal bus of the communication processing device and the above-mentioned communication lines. In the line control device, the processor means controls a scan processor that scans the parallel data processing requests, and a transmission interface among the interfaces. and a reception control processor that controls a reception interface of the interfaces, the means for providing scan information from the scan processor to the transmission control processor and the reception control processor; A line control device comprising: a processor; and means for providing the operating state of the reception control processor to the scan processor.