JPS62125659A - input protection circuit - Google Patents

Abstract

PURPOSE:To prevent a potential from varying at load voltage applying time by forming a second conductivity type sixth semiconductor layer formed to surround the periphery of a fourth semiconductor layer and applied with a reference voltage. CONSTITUTION:A transistor 11 is set at an N-type insular region 25 to a negative polarity potential when a negative polarity voltage is supplied to an input terminal 10. At this time, a parasitic current tends to flow in a passage of other N-type insular region, a P-type substrate and an N-type insular region 26, but since an N<+> type semiconductor layer 30 including an N-type impurity is formed in high density around the region 25, most parasitic current generated in the transistor 11 flows in a passage of the layer 30, an N-type semiconductor device 22, a P<+> type semiconductor layer 23 and the region 25. Accordingly, this transistor 11 does not almost affect other circuit. Thus, even if a negative polarity voltage is applied to the terminal 10, a potential variation does not substantially occur in other circuit.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an input protection circuit provided at the input stage of a semiconductor integrated circuit such as an integrated circuit for an A/D converter, an integrated circuit for a rotation detection circuit, or an integrated circuit for an automobile. In particular, there is a possibility that the input voltage becomes negative polarity, and the negative influence of this negative polarity voltage on other circuits is suppressed.

[Technical background of the invention and its problems] Fig. 5 is composed of bipolar transistors, and for example, three analog input voltages Vin, f! i.

Select either V inB or V inC and press A/
FIG. 2 is a circuit diagram showing the configuration of a multiplexer circuit section provided at the input stage of an A/D conversion circuit that performs D conversion. In this multiplexer circuit section, when selecting the input voltage VinA, only the selection signal 5ELA is set to the "OI+ level" and the remaining selection signal S.sub.ELB.

5ELC is set to "1" level. Signal 5ELB.

When 5ELC is set to 1111+ level, npnt- transistors 51B and 51C are turned on, so pn
The emitter potential of each of p-transistors 52B and 52G is set to approximately ground potential. On the other hand, signal 5ELA is i
Since it is at the r O++ level, the npnt-transistor 51A is turned off, and the emitter potential of the pnp transistor 53A, whose base is supplied with the input voltage VinA, is higher than Vin8 by the base-emitter voltage VBE53 of this transistor 53A (V inA + VBE53). ) and whose base is connected to the emitters of the transistors 53A and 53A.
52 higher potential (V+nA+VB E 53+ VB
E 52).

On the other hand, a current mirror circuit consisting of pn pI transistors 54 and 55, npn transistors 56 to 59 whose emitters are connected, and a constant current source 60 constitute a differential circuit, and the base and collector of transistor 59 are short-circuited. Therefore, a potential equal to the potential supplied to the base of any one of the transistors 56 to 58 is outputted from the output terminal 61 provided at the connection point between the bases and collectors of the transistors 59 to 59. Therefore, the above belief @
When only SFL△ is set to the "0" level, the emitter potential of the transistor 52A (
V! A potential equal to nA+VBi53+VBE52) is output.

Further, when the signal SEI B is set to the "0" level,
npnt-transistor 51B is turned off, and the pnp transistor 53 whose base is supplied with the input voltage Vin13
This transistor 5 has an emitter potential of B higher than VinB.
A pnp whose potential is set to a higher potential (VinB+VBE 53) by the base-emitter voltage VBE53 of transistor 3B, and whose base is connected to the emitter of this transistor 53B.
The emitter potential of the transistor 52B is the above potential (Vin
The potential (Vin
B+VnE53+VBE52), and this potential is output from the output terminal 61. Furthermore, when the signal 5FLC is set to the "O" level, the npn transistor 51
G is off and the emitter potential of the pnpt transistor 53C whose base is supplied with the input voltage VinC is Vi
The potential (VinC+Vp E
53), and the base is this transistor 53C.
pnp transistor 52C connected to the emitter of
The emitter potential of is the above potential (VinC + Vo E 53
) is higher than the base-emitter voltage VBE52 of this transistor 52C (VinC+Vs E 5
30V s E 52), and this potential is applied to the output terminal 6.
Output from 1. The voltage selected here is then A/D converted in an A/D conversion circuit section (not shown). In addition, in FIG. 5, 62 to 67 are constant current sources, respectively.

FIG. 6 is a sectional view showing the element structure of the transistors 53A, 538, and 530 when the circuit as described above is integrated. An N-type semiconductor layer 72 is formed on a P-type semiconductor substrate 71 by, for example, an epitaxial method. This N-type semiconductor layer 72 has N-type island regions 74,75,16 separated by a P1-type half layer 73, and each island region 74,75,76 has a P-type semiconductor layer. 77, 78, and 79 are formed respectively. That is, each of the above transistors 53A, 53B
, 53C is configured such that the P-type semiconductors 1iI77, 78, and 79 are emitters, the island regions 74, 75, and 76 are bases, and the P-type semiconductor substrate 71 is a common collector, and this semiconductor substrate 71 is grounded. ing.

In such a cross-sectional structure, for example, the input voltage VinA
When a negative voltage is applied, the N-type island region 74 is set to a negative potential. Therefore, as shown in FIG. 6, this island region 7 is
A current of 11 flows toward 4. On the other hand, this current 1
1, the island area 75 adjacent to the island area 74
An unnatural current 12 as shown flows from the circuit. For this reason, the first to transistors 53 based on this island region 75
The input voltage V inB of B is affected and decreases, which causes a conversion error.

Conventionally, in order to prevent potential fluctuations in other circuits when the negative polarity window IJ is applied, as shown in FIG. A protection circuit consisting of diodes 81, 82 and a resistor 83 is externally connected to the input terminal. In this protection circuit, when a negative voltage is applied to the input terminal 84 of the voltage Vin, the diode 81 becomes conductive, and the current due to this negative voltage is released to the ground potential. Further, the current due to the negative polarity voltage generated inside the integrated circuit 80 is transferred to the resistor 8
Since it is sufficiently attenuated by 3, it is possible to sufficiently suppress potential fluctuations applied to the above-mentioned circuit. Note that the other diode 82 is for protection against high voltage of positive polarity.

However, providing such a protection circuit outside the integrated circuit increases the number of elements, which is undesirable from a cost perspective. Therefore, such a protection circuit is integrated into the integrated circuit 80.
It is easy to imagine that it could be formed inside the . However, by simply incorporating this protection circuit as is, it is not possible to prevent the above-mentioned potential fluctuation due to the influence of the stray current of the diode 81.

[Object of the invention] This invention has been made in consideration of the above circumstances, and the object of the invention is to be able to be built into an integrated circuit,
An object of the present invention is to provide an input protection circuit that can prevent potential fluctuations that occur when a negative electrode f1 voltage is applied.

[Summary of the Invention] In order to achieve the above object, the present invention includes a semiconductor substrate of an eleventh voltage type to which a reference potential is applied, and a second semiconductor substrate formed on the substrate and to which an M quasi-potential is applied. A first conductivity type semiconductor layer is a collector, a first conductivity type second semiconductor layer formed within this first semiconductor layer and to which a reference potential is applied is a base, and a second conductivity type semiconductor layer formed within this second semiconductor layer is a base. A first transistor having a conductivity type third semiconductor layer as an emitter and an input voltage applied to the third semiconductor layer; the base as a collector; and the first semiconductor layer on the base, which are formed separately. The fourth semiconductor layer of the second conductivity type formed in the fourth semiconductor layer is used as the base, the fifth semiconductor layer of the first conductivity type formed in the fourth semiconductor layer is used as the emitter, and the input voltage is applied to the fifth semiconductor layer through the resistance element. a second transistor for input to which is applied;
An input protection circuit is provided, which includes a sixth semiconductor layer of a second conductivity type, which is formed so as to surround the semiconductor layer of the sixth semiconductor layer, and to which a reference potential is applied. In other words, by using a 1-transistor with a switching function as a means for clamping the negative polarity voltage, it is possible to prevent current from flowing into the substrate, and also to prevent the current from flowing into the substrate through the resistive element to the base of the second transistor for input. Attenuating the value of the negative current flowing into the base by applying a voltage, and surrounding the second transistor with a sixth semiconductor layer having a different voltage type from the substrate, and setting this semiconductor layer to a reference potential. By doing so, the negative polarity current flowing out from this second 1H transistor is attenuated.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a circuit diagram when the input circuit according to the present invention is implemented in the multiplexer circuit section of an A/D converter circuit in the same manner as in FIG. 5, and only the input circuit section for one analog input voltage Vin is shown. has been done.

In the figure, two resistors 12 and 13 are inserted in series between an input terminal 10 to which the input voltage Vin is supplied and the base of an input PNP transistor 11 corresponding to transistors 1 to 53 in FIG. has been done. The emitter of an npn transistor 14 is connected to the connection point between the resistors 12 and 13. The collectors and bases of transistors 1 to 14 are both grounded. Furthermore, the collector of the input transistor 11 is grounded, and a constant current source 15 is inserted between the emitter and the power supply potential Vcc. Further, the emitter of the transistor 11 is connected to the base of a pnp transistor 16, which corresponds to the transistor 52 in FIG. The collector of this transistor 16 is grounded, and a constant current [17 is inserted between the emitter and the power supply potential Vcc. Further, the emitter of this transistor 17 is connected to the transistor 5 shown in FIG.
The collector of a selection npnt-transistor 18 corresponding to No. 1 is connected, the emitter of this transistor 18 is grounded, and the base is supplied with the selection signal SEL. Although not shown, the emitter potential of the transistor 16 is supplied to a differential circuit having a configuration similar to that shown in FIG. 5.

Further, a guard ring indicated by a broken line is formed around the input transistor 11, and this guard ring is grounded.

FIG. 1 is a cross-sectional view showing the cross-sectional structure of transistors 11 and 14 when the circuit having the structure shown in FIG. 2 is integrated.

An N-type semiconductor layer 22 is formed on the P-type semiconductor base 21 by, for example, an epitaxial method.

In this N-type semiconductor layer 22, N-type island regions 24 and 25 separated by a P+ type semiconductor layer 23 are formed. An N++ conductor layer 26 is formed at the bottom of one of the island regions 24, and a portion thereof is formed to be exposed from the surface of the island region 24. Further, a P-type soil conductor layer 27 is formed within this island region 24, and this P-type soil conductor layer 27
An N-type semiconductor layer 28 is formed inside. The n p n l-transistor 14 in FIG.
J3 is composed of a type island region 24 as a collector, a P-type earth conductor layer 27 as a base, and an N-type semiconductor layer 28 as an emitter.
, the P+ type semiconductor layer 2 formed around the N1 semiconductor layer 26, the P type soil conductor layer 27, and the N type island region l1124.
3 are each grounded, and the N-type semiconductor layer 28 is connected to the input terminal 10 via the resistor 12.

In the other island region 25, a 1] type half layer 29 is formed. Furthermore, P for separating this island region 25
An N+ type half layer 30 forming the guard ring is formed around the + type semiconductor layer 23.

That is, the pnp transistor 11 in FIG.
It is configured with the P-type substrate 21 as the collector, the N-type semiconductor layer 25 as the base, and the P-type earth conductor layer 29 as the emitter.
The N+ type semiconductor layer 23 and the N+ type half layer 30 are each grounded, and the N type semiconductor layer 25 is connected to the N type semiconductor layer 28 of the transistor 14 via the resistor 13. Further, the P-type earth conductor layer 29 of this transistor 11 is connected to the base of the pnp transistor 16 and one end of the constant current 115 in FIG.

In such a configuration, when a negative voltage is applied to the input terminal 10, the N-type semiconductor layer 28 is set to a negative potential in FIG. Since the P-type soil conductor layer 27 on which the N-type semiconductor layer 28 is formed is grounded, by applying such a negative polarity voltage, the N-type semiconductor layer 28 and the P-type soil conductor layer 27 are grounded. A current flows from the P-type soil conductor layer 27 toward the N-type semiconductor H28 at the pn junction consisting of the transistor 14, and most of the negative polarity voltage applied to the input terminal 10 is absorbed by the transistor 14. Also P
The type substrate 21 and the N type island region [24] are both grounded and have the same potential, so even if a negative voltage is supplied to the input terminal 10, there will be no interference from the substrate 21 and the island region 24. Almost no current flows through the pn junction. Therefore, since no current flows through the substrate 21, the island region 25 provided adjacent to the island region 24, the substrate 21, and the N-type semiconductor layer 2
No parasitic current is generated in the path consisting of 4, and other circuits are not affected.

Regarding the transistor 11, when a negative voltage is supplied to the input terminal 10, the N-type island region 25 is set to a negative potential. At this time, as in the case of FIG.
A strange current tries to flow along the path of , but this island region 25
Since an N++ semiconductor Fm30 containing N-type impurities at a high I of 11 degrees is provided around the N1-type semiconductor layer 30, N-type semiconductor device 22, P'-type half layer 23 and N
Most of the parasitic current generated in this transistor 11 flows through the path of the mold island region 25. Therefore, this transistor 11 has almost no influence on the circuit.

As a result, in this embodiment circuit, even if a negative voltage is applied to the input terminal 10, almost no potential fluctuation occurs in other circuits.

Note that, in general, when an npn transistor is connected like the transistor 14, it exhibits Zener characteristics when a predetermined voltage of positive polarity is applied to its emitter. For this reason,
By adjusting the Zener voltage by controlling the impurity concentration of the N-type semiconductor layer 28, etc., which becomes the emitter of the transistor 14, protection against a positive high voltage applied to the input terminal 10 can be achieved.

FIG. 3 is a characteristic diagram that does not show fluctuations in the potential V of other circuits when a negative voltage is applied to the input terminal 10 and a negative current -I flows. In the figure, curve a is for a conventional circuit, and as current -I increases, potential V drops significantly.

On the other hand, the curves are those of the above example circuit,
Even if the current -1 increases, the potential V hardly decreases.

FIG. 4 is a sectional view of a modification of the invention, showing another structure of the transistor 14. In this example, the N+ type half body layer 6 is continuously formed not only at the bottom but also around the N type island region 24, and is grounded. Having decided to have such a configuration, the substrate 21
The parasitic current flowing through can be significantly reduced.

FIG. 8 is a sectional view showing a specific structure of the resistors 12 and 13 used in the circuit of the above embodiment. These resistances are P
An N type semiconductor layer 22 formed on a type semiconductor substrate 21 is separated by a P+ type semiconductor layer 23 to form an N type island region 81, and a P type semiconductor layer 82 is formed within this island region 81. It is made up of. That is, the resistor 12.
13, this P-type semiconductor layer 82 is used. The N-type island region 81 is connected to Vcc or ground.

[Effects of the Invention] As explained above, according to the present invention, it is possible to provide an input protection circuit that can be easily incorporated into an integrated circuit and can prevent potential fluctuations when applying a negative polarity voltage. can.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the configuration of an embodiment of the present invention, and FIG.
The figure is a circuit diagram of the above-mentioned embodiment, FIG. 3 is a characteristic diagram for explaining the above-mentioned embodiment, and FIG. 4 is a sectional view of a modification of the present invention.
Fig. 5 is a circuit diagram showing the configuration of a multiplexer circuit provided at the input stage of the A/D conversion circuit, Fig. 6 is a cross-sectional view showing the element structure of a part of the circuit shown in Fig. 5, and Fig. 7 is a conventional circuit. FIG. 8 is a cross-sectional view showing the structure of the resistor used in the circuit of the above embodiment. 11... PNP transistor for input, 12.13.
...Resistor, 14...npnt-transistor, 16...
- pnpt-transistor, 21... P-type semiconductor substrate, 22... N-type semiconductor layer, 23... P4'' type semiconductor layer, 24.25... N-type island region, 26... N++
Conductor layer, 27... P type semiconductor layer, 28... N type semiconductor layer, 29... P type semiconductor layer, 30... P+ type semiconductor layer. Applicant's agent Patent attorney Takehiko Suzue 171

Claims (3)

[Claims] (1) A semiconductor substrate of a first conductivity type to which a reference potential is applied; and a first semiconductor layer of a second conductivity type formed on the substrate and to which a reference potential is applied; A second semiconductor layer of the first conductivity type formed and applied with a reference potential is used as a base, a third semiconductor layer of the second conductivity type formed in this second semiconductor layer is used as an emitter, and input to the third semiconductor layer. a first transistor to which a voltage is applied; the base is a collector; a fourth semiconductor layer of a second conductivity type formed on the base separately from the first semiconductor layer is a base; a second input transistor having a fifth semiconductor layer of a first conductivity type formed in the layer as an emitter and to which the input voltage is applied via a resistive element; and a fourth semiconductor layer. An input protection circuit comprising: a sixth semiconductor layer of a second conductivity type formed to surround the layer and to which a reference potential is applied. (2) The seventh semiconductor layer of the second conductivity type, which contains impurities at a high concentration and is applied with a reference potential, is formed at the bottom of the first semiconductor layer. input protection circuit. (3) Claim 2, wherein an eighth semiconductor layer of a second conductivity type that contains a high concentration of impurities and is applied with a reference potential is formed so as to surround the first semiconductor layer. Input protection circuit as described in .