JPS62124748A - Package for mounting semiconductor element - Google Patents
Package for mounting semiconductor elementInfo
- Publication number
- JPS62124748A JPS62124748A JP60263996A JP26399685A JPS62124748A JP S62124748 A JPS62124748 A JP S62124748A JP 60263996 A JP60263996 A JP 60263996A JP 26399685 A JP26399685 A JP 26399685A JP S62124748 A JPS62124748 A JP S62124748A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- package substrate
- bumps
- onto
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 〔技術分野〕 本発明は、半導体素子の実装技術に関する。[Detailed description of the invention] 〔Technical field〕 The present invention relates to a mounting technique for semiconductor elements.
従来、半導体素子（１）をパッケージ基板（２）に実装
する方法としては大別して次の４つの方式が公知である
。すなわち、第３図の如き金線（３）で両者間をつなく
ワイヤーボンディング方式第４図の如き半導体素子（１
）の裏面に形成したバンプ（４）を利用するフリップチ
ップ方式第５図の如く両者間をビームリード（５）で接
合するビームリード方式がある。第３図の例は、多くの
入出力端子を有する半導体素子に対しては、入出力数に
比例したボンディング時間を要し、不向きである。Conventionally, the following four methods are known as methods for mounting a semiconductor element (1) on a package substrate (2). In other words, the semiconductor element (1) as shown in FIG.
) There is a flip-chip method that utilizes bumps (4) formed on the back surface of the two. As shown in FIG. 5, there is a beam lead method that connects the two with a beam lead (5). The example shown in FIG. 3 is not suitable for a semiconductor device having many input/output terminals because it requires bonding time proportional to the number of input/output terminals.
これに対して、フェースダウンボンディングをおこなう
第４図及び第５図の例は一度にバンプ（４）等の入出力
端子をパフケージ基板（２）にボンディングする為、高
速でボンディングすることができ、工程の合理化が図れ
る。しかし、これらの方式は、半導体素子形成時に、バ
ンプを設けなければならず、半導体素子単価の上昇をま
ねくとともに現在のところまだまだ、多数を占めるワイ
ヤーボンディング用のチップとは互換性がなく、普及に
時間がかかっている。On the other hand, in the examples shown in FIGS. 4 and 5, which perform face-down bonding, input/output terminals such as bumps (4) are bonded to the puff cage substrate (2) at one time, so bonding can be performed at high speed. The process can be streamlined. However, these methods require bumps to be provided when forming the semiconductor element, which increases the unit cost of the semiconductor element.Currently, these methods are still incompatible with the majority of wire bonding chips, and are not widely used. It's taking time.
このため、特に多くの入出力端子を有するゲートアレイ
や、画像処理用ＩＣのパッケージは、ワイヤーボンドに
時間がかかるにもかかわらずピングリッドアレイ （Ｐ
ＧＡ）バンケージャ、リードレスチップキャリア（ＬＣ
Ｃ）等のパッケージ基板に、ワイヤーボンド方式を採用
して実装している。For this reason, gate arrays and image processing IC packages, which have a particularly large number of input/output terminals, are manufactured using pin grid arrays (P
GA) Bunker, leadless chip carrier (LC)
It is mounted on a package substrate such as C) using the wire bonding method.
本発明は、多数の入出力端子を有する半導体素子の実装
を短時間に、安価に行なうことができる半導体素子実装
用パッケージを提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a package for mounting a semiconductor element, which allows mounting of a semiconductor element having a large number of input/output terminals in a short time and at low cost.
本発明の要旨とするところはセラミックやガラスエポキ
シ樹脂等を材料とするパッケージ基板及び、このパッケ
ージ基板の表面から裏面へ形成した複数本のリード及び
、このリード上に、半導体素子と電気的接続をとる為の
バンプを設けたことを特徴とする半導体素子実装用パッ
ケージである。即ち、本発明は半導体素子を実装するパ
ッケージ基板の半導体素子の人出力パッドに相対する位
置に、バンプを設は半導体素子は従来のワイヤーボンデ
ィング用アルミニウム等のパッドを有する半導体素子を
用いることができるような、ビングリッドアレイパッケ
ージや、リードレスチップキャリア等の半導体素子実装
用パッケージを提案するものである。The gist of the present invention is to provide a package substrate made of ceramic, glass epoxy resin, etc., a plurality of leads formed from the front surface to the back surface of the package substrate, and electrical connections to semiconductor elements on the leads. This is a package for mounting a semiconductor element, which is characterized by being provided with bumps for removal. That is, in the present invention, a bump is provided at a position opposite to the human output pad of the semiconductor element on a package substrate on which the semiconductor element is mounted, and the semiconductor element can be a semiconductor element having a pad made of conventional aluminum for wire bonding. The present invention proposes semiconductor element mounting packages such as bin grid array packages and leadless chip carriers.
ブ
具体的に実施例を用いて説明する。第≠図に示したもの
は、ビングリッドアレイパッケージ（６）に半導体素子
（１）を実装する図で、ピングリッドアレイ （６）の
パッケージ基板（２）上の搭載する半導体素子（１）の
入出力端子に相対したパッド（７）にバンプ（４）が形
成されている。This will be specifically explained using examples. The figure shown in Figure ≠ is a diagram of mounting a semiconductor element (1) on a pin grid array package (6). A bump (4) is formed on a pad (7) facing the input/output terminal.
（８）はリーバである。(8) is a lever.
バンプ（４）の拡大図を第４図に示したが、このバンプ
（４）はパッケージ基板（２）上のパッド（７）を形成
している導体（１１）上にこの導体（１１）へ密着力を
増す為にニッケル、クロム、チタン等のメブキ（９）を
施し、その上にバンプ金属の拡散を防ぐための拡散防止
用の金属層（１０）を形成し、その上においていわゆる
バンプ金属といわれる例えば金や、はんだで形成されて
いる。An enlarged view of the bump (4) is shown in Figure 4, and this bump (4) is connected to the conductor (11) forming the pad (7) on the package substrate (2). A coating (9) of nickel, chromium, titanium, etc. is applied to increase adhesion, and a diffusion prevention metal layer (10) is formed on top of this to prevent the diffusion of the bump metal. For example, it is made of gold or solder.
なお密着用金属層や拡散防止用金属層は選択する金属に
より省略することも可能である。例えば導体材料が銅の
場合、両層は不要で直接バンプを形成することも可能で
ある。Note that the adhesion metal layer and the diffusion prevention metal layer may be omitted depending on the metal selected. For example, when the conductor material is copper, both layers are unnecessary and bumps can be formed directly.
而して、このピングリッドアレイ （６）は、半導体素
子（１）の搭載部（８）に、半導体素子（１）の裏面を
パッド（４）に直接接合して実装できるのである。Thus, this pin grid array (6) can be mounted on the mounting portion (8) of the semiconductor element (1) by directly bonding the back surface of the semiconductor element (1) to the pad (4).
以上のように、この発明の半導体素子実装用のパッケー
ジを用いると、従来のグイボンド方式の半導体素子をも
ちいてフェースダウン方式を用いてパッド上に直接接合
することができるので、■ボンディングを迅速に行なえ
る。As described above, by using the semiconductor element mounting package of the present invention, it is possible to bond directly onto pads using the face-down method using the conventional Guibond method semiconductor element. I can do it.
■半導体素子の入出力端子を加工しなくてもよい為、半
風体素子製造プロセスが従来通りでよく、その製造も簡
単である。■Since there is no need to process the input/output terminals of the semiconductor element, the manufacturing process for the semicircular element can be the same as before, and its manufacture is simple.
■従来ワイヤーポンディングに用いている半導体素子を
そのまま転用して使用できる。■Semiconductor elements conventionally used for wire bonding can be used as is.
■多くの入出力端子をもつ半導体素子の実装も容易であ
るという利点がある。■An advantage is that it is easy to mount semiconductor elements with many input/output terminals.
第１傘図及び第２図は本発明の一実施例を示す図で、第
１図は断面図、第２図は概略断面図、第３図乃至第５図
は各々従来例を示す断面図である（１）・・・半導体素
子、（２）・・・パッケージ基板、（３）・・・ワイヤ
、（４）・・・バンプ、（６）・・・半導体素子実装用
ンケージ、（７）・・・導体、（８）・・・搭載部。The first umbrella diagram and FIG. 2 are diagrams showing one embodiment of the present invention, in which FIG. 1 is a sectional view, FIG. 2 is a schematic sectional view, and FIGS. 3 to 5 are sectional views each showing a conventional example. (1) Semiconductor element, (2) Package substrate, (3) Wire, (4) Bump, (6) Semiconductor element mounting cage, (7 )...Conductor, (8)...Mounting part.
Claims (2)
パッケージ基板及び、このパッケージ基板の表面から裏
面へ形成した複数本のリード及び、このリード上に、半
導体素子と電気的接続をとる為のバンプを設けたことを
特徴とする半導体素子実装用パッケージ。(1) A package substrate made of ceramic, glass epoxy resin, etc., multiple leads formed from the front surface to the back surface of this package substrate, and bumps on the leads for electrical connection with the semiconductor element. A package for mounting a semiconductor element, characterized by the following:
てられた請求範囲第１項の半導体素子実装用パッケージ
。(2) The semiconductor element mounting package according to claim 1, wherein the plurality of leads are erected perpendicularly to the surface of the package substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60263996A JPS62124748A (en) | 1985-11-25 | 1985-11-25 | Package for mounting semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60263996A JPS62124748A (en) | 1985-11-25 | 1985-11-25 | Package for mounting semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62124748A true JPS62124748A (en) | 1987-06-06 |
Family
ID=17397095
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60263996A Pending JPS62124748A (en) | 1985-11-25 | 1985-11-25 | Package for mounting semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62124748A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3817600A1 (en) * | 1987-05-26 | 1988-12-08 | Matsushita Electric Works Ltd | Semiconductor device |
-
1985
- 1985-11-25 JP JP60263996A patent/JPS62124748A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3817600A1 (en) * | 1987-05-26 | 1988-12-08 | Matsushita Electric Works Ltd | Semiconductor device |
| US5126818A (en) * | 1987-05-26 | 1992-06-30 | Matsushita Electric Works, Ltd. | Semiconductor device |
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