JPS62123365A - Peak hold circuit - Google Patents

Abstract

PURPOSE:To make a circuit integratable onto a single semiconductor substrate together with other circuit elements, by adopting a gate circuit in plate of a diode. CONSTITUTION:A gate circuit M1, when an analog voltage is applied on the input terminal and a high-level signal on a control terminal, outputs the analog voltage from the output terminal, and when a low-level signal is applied to the control terminal, interrupts the analog voltage. A capacitor C1 has an electrode on one side connected to the output terminal of the gate circuit M1 and the other electrode connected to a grounding voltage. Further, in a voltage comparing circuit COM1, an electrode on one side of the capacitor C1 is connected to the No.1 input terminal and an analog voltage is applied to the No.2 input terminal. And, when the voltage applied to the No.1 input terminal is higher than the analog voltage, then a low-level signal is outputted and when the voltage applied to the No.1 input terminal is lower than the analog voltage, a high-level signal is outputted. By this arrangement, an integratable circuit without requiring the diode becomes available.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a peak hold circuit, and particularly to a peak hold circuit that can be integrated on a semiconductor substrate.

[Conventional technology]

Conventionally, this type of peak hold circuit, as shown in Fig. 2, uses the positive phase input of operational amplifier CPII as the signal input terminal, connects the anode side of diode D1 to its output, and connects the cathode side to one electrode of capacitor C1l. operational amplifier 0P12
is connected to the positive phase input of Further, the other electrode of the capacitor C1l is grounded. Furthermore, the negative phase input of the operational amplifier 0P12 is connected to the output to form a so-called voltage follower, and its output is the output terminal.
11 negative phase inputs.

The analog signal input to the peak hold circuit shown in FIG. 2 enters the operational amplifier 0P11, which is basically connected as a voltage follower and has a single input signal, so that an output of positive phase can be obtained.

However, in this case, diode D1 and capacitor C1 are included in the feedback loop.
It includes a half-wave rectifier circuit made up of 1 and a voltage follower made up of an operational amplifier 0P12. At this time, looking at the voltage at each part, it is V, rl = Vp = V.

Then, v, l becomes vP+ (1@direction drop voltage of diode D1). In this circuit, Via is v,, ut
When attempting to change in the child direction beyond t remains the same, and - remains the same. In this way, when the signal changes from the child direction to one direction, v
The voltage of P is maintained at the capacitance C1l and the output is V. , get t. Also, the voltage higher than vP maintained by capacitor C1l is Vl!
Unless it enters I, the value is held in DVp and Vut is output.

[Problem to be solved by the invention]

In the conventional peak hold circuit described above, a diode D1 must be provided to hold the positive-sequence input voltage of the operational amplifier 0P12 at the peak value of the analog signal, but the diode in the integrated circuit usually maintains it at a predetermined voltage. Since the semiconductor substrate formed on the semiconductor substrate and the substrate formed on the substrate are composed of impurity regions of opposite conductivity type, when the anode voltage and cathode voltage change as in the diode D1 in the conventional peak hold circuit, However, there was a problem in that it could not be integrated on a single semiconductor substrate together with other circuit elements.

Means for Solving Problem c] The present invention employs a gate circuit in place of the conventional diode DIK, compares the input analog voltage with the voltage stored in the capacitor, and compares the input analog voltage with the output voltage of the capacitor. The gist is to include a voltage comparator circuit that opens the gate circuit only when the voltage becomes higher.

〔Example〕

FIG. 1 is a diagram showing an embodiment of the present invention, in which the input terminal is connected to the positive phase input of the comparator COMI and one terminal of the analog multiplexer M1, and the other terminal of the analog multiplexer M1 is connected to the positive phase input of the comparator COMI. A capacitor C1 is connected to the negative phase input, and a capacitor C1 is connected between this connection point and the ground potential, and the output of the comparator is an analog multiplexer. It is input to the gate of M1.

Here, consider the case where a voltage that changes from the ground potential in the child direction is applied to Min. If Vout is initially set to 0 [v], then M
When in becomes even slightly more positive than 0 [v], the output of comparator C0M1 becomes high level, turns on the analog multiplexer M1, and charges the capacitor C1 with the voltage level of Via. In this state, Vln > ■0111. During the period L, Vln<Vtm@ (when D, the controller Av-100M1 outputs the full low level and the analog multiplexer M1 is turned off), VL-t retains its previous value. Here ■o
Since ll is a high impedance, it is normally received by a voltage follower, but any intensifier may be used as long as the signal strength is low.

Although the present invention has been described as a positive peak hold circuit, a negative peak hold circuit can be easily created by reversing the polarity of the comparator.

〔effect〕

As explained above, according to the present invention, the voltage comparator compares the input analog voltage and the output voltage of the capacitor, turns on the gate circuit only when the input analog voltage is high voltage, and reduces the input analog voltage. Since the capacitor is charged, there is no need for a diode as in the past, and the gate circuit can be integrated on a single substrate with other circuits, which has the effect of making it possible to integrate the peak hold circuit. can get.

[Brief explanation of drawings]

FIG. 1 is an electric circuit diagram showing one embodiment of the present invention, and FIG. 2 is an electric circuit diagram of a conventional example. Ml...Gate circuit bcl...Capacitor, C0M1...Voltage comparison circuit.

Claims (1)

[Claims] A gate circuit that outputs the analog voltage from the output terminal when an analog voltage is applied to the input terminal and a high-level signal is applied to the control terminal, and cuts off the analog voltage when a low-level signal is applied to the control terminal. and a capacitor having one electrode connected to the output terminal of the gate circuit and the other electrode connected to the ground voltage, one electrode of the capacitor being connected to the first input terminal, and the analog voltage being connected to the second input terminal. When the voltage applied to the first input terminal is higher than the analog voltage, the low level signal is output, and when the voltage applied to the first input terminal is lower than the analog voltage, the high level signal is output. A peak hold circuit equipped with a voltage comparison circuit.