JPS62121567A - Data processor - Google Patents

Abstract

PURPOSE:To easily recognize the time relation of an address by storing a function which issues an instruction to an address buffer part and an address, and simultaneously providing an address trace part having the function to store the number of a report signal. CONSTITUTION:An address trace part 5 is connected to one external address bus 59, and also, is connected to address buffer parts 3 and 4 which perform operational controls that output addresses and clock signals on internal address buses 51 and 52 to the external address bus. The report signal is inputted to plural data processing parts 1 and 2 which output report signals 55 and 56 to an outside, and to plural instruction signals 57 and 58 which instruct the start and the completion of an operation outputting addresses independently to each address buffer part, and an instruction is given to an optical one performing an output out of the address buffer parts. And the function which stores an inputted address and simultaneously stores the number of the report signal is provided. Thereby, it is enough to provide one address trace part 5, and also, the time relation between the addresses at each data processing part can be easily recognized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device (
Open up.

[Conventional technology]

Conventionally, as shown in FIG. 2, for example, in this type of data processing device, if the internal address buses 71, 72, and 73 of the three data processing units 20, 21, and 22 are unique, each internal address The configuration was such that the address trace portion was 23.24.25% for buses 7+, 72.73. Here, the address trace section 23.
24 and 25 are internal address buses 71, 72, and 7, respectively.
The address on 3 is taken in by the synchronization signal 74, 75, 76.

[Problem that the invention seeks to solve]

In the conventional data processing device described above, when the address bus is unique to the data processing unit, each address bus is not synchronized with each other, so the address trace function is added to each address bus. Although they have the same functions, they have the disadvantage of requiring multiple units.
Furthermore, since the address trace units are separate, there is a drawback that the temporal relationship of addresses on each address bus cannot be easily known.

(Means for Solving the Problems) A data processing device of the present invention has one external address bus, a unique internal address bus connected to the address bus, and a data processor on the internal address bus. It has an address buffer section that controls the operation of outputting an address and a clock signal synchronized with changes in the address to the external address bus, and further includes an address buffer section that controls the operation of outputting an address and a clock signal synchronized with changes in the address to the external address bus. Start and end operations for individually outputting addresses on the internal address bus to the external address bus for a plurality of data processing units that output report signals and for each address buffer unit in the plurality of data processing units; an address buffer unit of any one data processing unit that has a plurality of instruction signals for issuing instructions, inputs all report signals output from the plurality of data processing units, and outputs the report signals; In contrast, it has an address trace section having a function of issuing the instruction using the instruction signal, and a function of storing the address inputted from the external address bus and simultaneously storing the number of the report signal being outputted.

Therefore, only one address tracing unit is required, and it is also possible to easily know the H quantity relationship of the addresses of each data processing unit.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the data processing apparatus of the present invention, in which there are two data processing units.

The data processing section 1 has an internal address bus 51 and an address buffer section 3, and outputs a report signal 55 when the address on the internal address bus 51 becomes an address to be traced. The data processing section 2 has an internal address bus 52 and an address buffer section 4.
When the address becomes the address to be traced, a report signal 56 is output. The address buffer section 3 controls the operation of outputting the address of the internal address bus 51 to the external address bus 59 according to the start or end instruction of the instruction signal 57. The address buffer section 4 controls the start or end instruction of the instruction signal 58. The address trace unit 5 controls the operation of outputting the address of the internal address bus 52 to the external address bus 59.The address trace unit 5 inputs the report signals 55 and 561Fr output from the data processing unit 1.2, respectively, and outputs the report signals. In response to an instruction signal 57 or 58 to the address buffer section 3 or 4 of either data processing section 1 or 2 that is (2) Instructs the start and end of the operation to be output to the external address bus 59, and also stores and simultaneously outputs the address being output to the external address bus 59 using the synchronous clock 53 or 54 which is also output to the external address bus 59. The number of the report signal 55 or 56 being sent is memorized.

Next, the operation of this embodiment will be explained. The data processing unit 1 outputs a report signal 55 when the address on the internal address bus 51 becomes an address (address to be traced) that meets a preset condition. When the address trace section 5 receives this report signal 55, the instruction signal 57 sends the address of the internal address bus 51 and the synchronization clock 53 to the external address bus 59 to the address buffer section 3.
Instructs the device to start outputting. Then, the address trace section 5 stores the address outputted to the external address bus 59 using the synchronization clock 53 also outputted to the external address bus 59, and also stores the address outputted to the external address bus 59 using the report signal 5.
Also memorize the number 5. Thereafter, when the report signal 55 is no longer output, the address trace section 5 instructs the address buffer section 3 to terminate the above operation by the instruction signal 57, and the address trace section 5 itself also uses the address and report signal 55 numbers. interrupt the memory of. Next, when the address on the internal address bus 52 of the data processing section 2 becomes an address that matches a preset condition (address to be traced) and a report signal 56 is output, the address tracing section 5 uses the instruction signal 58 to address the address. Buffer part 4
to start the operation of outputting the address of the internal address bus 52 and the synchronization clock 54 to the external address bus 59,
! resume. When the report signal 56 is no longer output, the address trace section 5 instructs the address buffer section 4 to end the above operation by means of an instruction signal 58, and stops storing the address and the number of the report signal 56. In this way, the address trace section 5 receives the report signal 5.
5 is output, the address of the internal address bus 51 and the number of the report signal 55 are stored, and when the report signal 56 is output, the address of the internal address bus 52 and the number of the report signal 56 are stored using the respective synchronous clocks 53 and 54. repeat. When the report signals 55 and 56 are output at the same time, the address trace unit 5 instructs the address buffer unit 3 or 4 of one of the data processing units 1 or 2 to start and end using the instruction signal 57 or 58. , the address output to the external address bus 59 is stored, and both the report signal numbers are stored. This makes it easy to understand that an event to be traced has occurred in both data processing units 1.2.

Although this embodiment deals with a case where there are two data processing units, the same applies to a case where there are three or more data processing units.

〔Effect of the invention〕

As explained above, the present invention enables each data processing unit to output a report signal when the address of the internal address bus of each data processing unit becomes an address to be traced, and also to output the report signal. By tracing the address by instructing the start and end of the operation that outputs the address and synchronization clock of the internal address bus of the data processing unit connected to the external address bus connected to the address trace unit, it is possible to trace the address, which previously required multiple units. This has the advantage that the number of address trace units that have been previously used can be reduced to one unit, and that the temporal relationship between events that occur in each data processing unit can be easily understood.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing one embodiment of a data processing device of the present invention, and FIG. 2 is a block diagram showing a conventional example. 1.2...Data processing unit, 3.4...Address buffer unit, 5...Address trace unit, 51, 52...Internal address bus, 53, 54...Synchronization clock, 55, 56 ... report signal, 57, 58 ... instruction signal, 59 ... external address bus. Figure 1

Claims (1)

[Claims] One external address bus, a unique internal address bus connected to the address bus, and an address on the internal address bus and a clock signal synchronized with changes in the address. and a plurality of data processing units that have an address buffer unit that controls the operation of outputting to the external address bus, and further output a report signal to the outside when an address on the internal address bus becomes an address to be traced. , having a plurality of instruction signals for individually instructing each address buffer section in the plurality of data processing sections to start and end an operation of outputting an address on the internal address bus to the external address bus; a function of inputting all report signals outputted from a plurality of data processing units and instructing an address buffer unit of any one data processing unit outputting the report signal using the instruction signal; A data processing device comprising an address trace section having a function of storing an address input from an external address bus and simultaneously storing a number of the report signal being output.