JPS62120720A - phase locked loop circuit - Google Patents

Abstract

PURPOSE:To form a continuous wave of a prescribed period oscillated in an optional frequency by inputting a ripple carrier RC signal and a synchronizing signal of a prescribed period to a load LD terminal of a counter frequency- dividing an output of a voltage controlled oscillator VCO in a PLL circuit in an oscillation circuit using a phase locked loop PLL circuit. CONSTITUTION:A signal extracted from a specific timing of a synchronizing signal is used as a control signal deciding the period of a counter 2 frequency- dividing an output of the voltage controlled oscillator VCO 3 in the phase locked loop PLL circuit. For example, in a video signal of the standard television system, a horizontal synchronizing signal and a clock of 14.13818MHz are synchronized and 910 clocks exist in one period of the horizontal synchronizing signal. Thus, in obtaining a continuous wave of nearly 2.5MHz synchronized with said horizontal synchronizing signal at each specific phase, when a count number of a counter 1 is selected as 910 and a count number of the counter 2 as 159, the continuous clocks having a prescribed frequency of 2.502MHz synchronized with the horizontal synchronizing signal at a specific phase are obtained.

Description

[Detailed Description of the Invention] [Summary] In an oscillation circuit using a phase-locked loop (PLL) circuit, a counter load ( Lg
) The ripple-Galley (RC) signal output at a period determined by a preset value is ANDed with one clock of the input clock input to the phase-locked loop (PLL) circuit. By inputting a synchronization signal with a constant period, a continuous wave with a constant period that is synchronized with the synchronization signal at a specific phase and oscillates at an arbitrary frequency is obtained.

[Industrial application field]

The present invention relates to a phase-locked loop (PLL) circuit, and more particularly to a control method for a phase-locked loop (PLL) circuit that can obtain a constant-cycle continuous wave signal that is synchronized with a specific phase to a constant-cycle synchronization signal.

In recent ultrasonic diagnostic apparatuses, an economical rusk scan type display device is often used to display ultrasonic reflection signals from a subject.

In this case, since the ultrasonic reflected image is displayed according to the standard television system, it is required to economically generate continuous waves synchronized with the period of the horizontal synchronization signal of the television.

On the other hand, there is a known method of economically generating arbitrary continuous wave pulse signals using a phase-locked loop (PLL) circuit, but it is difficult to synchronize with a synchronizing signal of a constant period at a specific phase each time. If possible, it is possible to obtain an arbitrary continuous wave synchronized with the period of a horizontal synchronization signal of a television, for example, while maintaining the economy of a phase-locked loop (PLL) circuit.

[Prior art and problems to be solved by the invention] FIG. 3 is a diagram showing an example of the configuration of a conventional phase-locked loop (PLL) circuit.

When a sufficiently high reference frequency is input from the outside, it is divided by a counter 1 and input to a phase comparator 2.

Counter 2 is a so-called n-ary counter, and by setting a constant value m in advance, ripple carry (RC
) terminal outputs an m-n-adic pulse signal, and by resetting the load (LD) terminal with a negation signal of this signal, the 8-n-adic counter can function as an m-n-adic counter, The continuous wave pulse output from the voltage controlled oscillator (VCO) 3 can be divided into frequencies as desired.

Then, the phase of the ripple carry (RC) signal and the phase of the counter 1 are compared by the phase comparator 4 to determine the phase difference, and the phase difference signal is transmitted to the voltage controlled oscillator (
By feeding back to VCO) 3, a continuous wave signal with a frequency corresponding to the phase difference can be obtained.

Therefore, in a conventional phase-locked loop (PLL) circuit, an arbitrary continuous wave with a fixed frequency division ratio can be obtained for an external input signal, but a specific phase is generated each time for a synchronized signal of a fixed period. Because it is not possible to obtain synchronized continuous waves,
There has been a problem in that it is not very adaptable to ultrasonic diagnostic equipment and the like equipped with a Rusk scan type display device.

In view of the above-mentioned conventional drawbacks, the present invention provides a phase-locked loop (PL).
L) Ripple carry (RC
) terminal and a load (LD) terminal, by controlling the load (LD) terminal of an n-ary counter with a constant period synchronization signal, a constant period synchronization signal synchronized with the synchronization signal at a specific phase. The purpose of this invention is to provide a method for obtaining continuous waves of arbitrary frequencies.

[Means for solving problems]

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the present invention, when there is a periodic synchronization signal and a reference frequency input that is synchronized with the synchronization signal and has a sufficiently higher frequency than the synchronization signal, a phase-locked loop (PLL) mechanism is used, and the above-mentioned In a circuit that obtains an output frequency that is an integral multiple of the synchronization signal, the synchronization signal is added to the control signal that determines the period of the circuit 2 that divides the output of the voltage controlled oscillator (VCO) 3 in the phase-locked loop (PLL) circuit. It is configured to apply a signal extracted at a specific timing.

[Effect]

That is, according to the present invention, in an oscillation circuit using a phase-locked loop (PLL) circuit, the phase-locked loop (PLL)
) Ripple carry (RC) output at a period determined by a preset value to the load (LD) terminal of a counter that divides the output of the voltage controlled oscillator (VCO) in the circuit.
) signal and one clock of the input clock input to the phase-locked loop (PLL) circuit. Since it is designed to obtain a continuous wave with a constant period that oscillates at an arbitrary frequency, for example, it has the effect of economically obtaining a continuous wave of an arbitrary frequency synchronized with a horizontal synchronizing signal of a standard television system.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

The above-mentioned FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a diagram showing a phase locked loop (PL) according to the present invention.
L) It is a diagram showing the operation of the circuit as a time chart. In FIG. 1, the ripple carry (R
C) NAND circuit provided at the terminal 5. The synchronizing signal (one clock of the input signal) input to the NAND circuit is a necessary functional block to carry out the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

Generally, in a standard television system video signal, the horizontal synchronizing signal and the 14.31818 MII2 clock are synchronized, and there are 910 clocks in one period of the horizontal synchronizing signal.

Therefore, synchronized with this horizontal synchronization signal at a specific phase every time,
When obtaining a continuous wave of about 2.5 MHz, set the count number of counter 1 to "910' and the count number of counter 2 to 159" in Fig. 1, so that the horizontal synchronization signal has a specific phase. A synchronized continuous clock with a constant period of 2,502 MHz can be obtained.

FIG. 2 is a diagram showing the operation at this time as a time chart, where ■ is, for example, the above 14.31818 MHz.
2 indicates an input signal that is a clock, and ■ indicates a synchronization signal (for example,
(2) is a synchronization signal that is synchronized with the horizontal synchronization signal and can extract one clock of the input clock;
It constitutes a control signal for the

Therefore, in the phase locked loop (PLL) circuit according to the present invention, for example, a synchronization signal that is synchronized with a horizontal synchronization signal of a video signal and extracts one clock of a human clock with a frequency sufficiently higher than that of the synchronization signal. A NAND circuit 5 performs the logical product of ① and the ripple carry (RC) signal of the counter 2, and inputs the output signal to the load (LD) terminal of the counter 2 and to the phase comparator 4. Since the counter 2 operates so as to be reset by a signal synchronized with the horizontal synchronization signal, the phase difference determined by the output of the counter 1 and the NAND circuit 5 is determined by the voltage controlled oscillator (VCO). For example, it is possible to obtain a clock signal of an arbitrary frequency determined by the count number of the counter 2, which is synchronized with the horizontal synchronizing signal and is fed back to the input of the counter 2, as shown by 3, for example.

As described above, the present invention provides an oscillator using a phase-locked loop (PLL) mechanism in which a voltage is generated by a synchronizing signal of a constant period that is synchronized with an input signal and can extract l clocks of the input signal. The feature is that a frequency division counter for a controlled oscillator (VCO) is controlled to obtain a continuous clock signal of almost any arbitrary period in synchronization with the synchronous signal of the constant period.

C. Effects of the Invention] As described above in detail, the phase-locked loop circuit of the present invention is an oscillation circuit using a phase-locked loop (PLL) circuit, in which a voltage-controlled oscillator in the phase-locked loop (PLL) circuit A ripple carry (RC) signal is output to the load (LD) terminal of a counter that divides the output of the VCO at a period determined by a preset value, and is input to the phase-locked loop CPLL) circuit. By inputting a synchronization signal with a constant period that is ANDed with one clock of the input clock, a continuous wave with a constant period that is synchronized with the synchronization signal at a specific phase and oscillates at an arbitrary frequency can be obtained. Therefore, for example, continuous waves of any frequency synchronized with the horizontal synchronizing signal of the standard television system can be economically obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a time chart showing the operation of the phase-locked loop (PLL) circuit according to the present invention. FIG. 3 is a diagram showing an example of the configuration of a conventional phase-locked loop (PLL) circuit. It is. In the drawing, 1 is a counter that divides the input signal. 2 is a counter that divides the output of voltage controlled oscillator (VCO) 3. 3 is a voltage controlled oscillator (VCO). ■ is the output signal. are shown respectively.

Claims (1)

[Claims] A phase-locked loop (PLL) mechanism is used when a periodic synchronization signal and a reference frequency whose frequency is sufficiently higher than that of the synchronization signal are input in synchronization with the synchronization signal. , in a circuit that obtains an output frequency that is an integer multiple of the synchronization signal, the voltage controlled oscillator (
A phase-locked loop circuit characterized in that a signal obtained by extracting a specific timing of the synchronization signal is applied to a control signal that determines the period of the circuit (2) that divides the output of the VCO (3).