JPS621196A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent wrong data from being written in a column latch at the end of the 1st cycle of an EEPROM, where page mode writing is executed, by informing a semiconductor memory device of the termination of the 1st cycle by another signal transmission method without a timer. CONSTITUTION:Since a conventional device does not always synchronize with external signals, such as the inverse of CE and the inverse of WE at the rise point of a timer output, right data may not be written in the column latch 1 when the inverse of CE and the inverse of WE are both of logic '0' and the timer output, trails, so that, an external writable signal trails, while data is written in the column latch 1. This invention sets the inverse of WE at logic '0' during a certain period while the inverse of CE is held at logic '1' after an external circuit recognizes that the right data Dn is written at an address position shown by An due to the leading of the inverse of WE. Because of the rise of the inverse of WE, the external writable signal trails. The combination of signals where the inverse of WE comes to logic '0' during a certain period as the inverse of CE is held at logic '1' cannot be available under other conditions.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to EEPROM (electrically
erasable programmable ROM
) is related to write control to writable nonvolatile storage devices.

Writing to EEFROM is performed in page mode and is 16 bytes (assuming 16 bytes is 1 page. 1 byte is 8
bits) of data are written at once.

Unlike ordinary static memory, IPROM requires relatively high voltage and long time to write. For example, it takes several milliseconds to 10 milliseconds to write data to a memory cell. Therefore, if writing is to be performed for each byte, in a 64-bit EEFROM with an 8-word x 8-bit configuration, it takes several 1 to write all the bits.
This will require 0 to 80 seconds. Therefore, 6
For EEFROMs with a capacity of 4 bits or more, page mode programming is performed.

If you write 16 bytes at a time, the writing time is 1/i6
becomes.

Figure 4 shows an EEPROM with page mode writing function.
1 is a block diagram showing the write system of , in which (1) is a column latch, (2) is a row address buffer, +3) is a column address buffer, (4) is a column decoder, and (5) is a data manual. A buffer, (6) a row decoder, and (7) a memory cell array. For convenience of explanation, a memory cell array (
7) has a capacity of 8 KW x 8 bits, and if an address is determined for each word (8 bits), 213 types of addresses are required for 8 words, and the address signal is composed of 13 bits of address signals. do. The upper 9 bits of these 13 bits are temporarily used as a row address, and the lower 4 bits are temporarily used as a column address.

Data and a 13-bit address signal indicating the location of the memory cell array (7) where the data should be input are input from outside the circuit shown in the drawing, and the data is temporarily stored in a data buffer, with the upper 9 bits of the address signal being low. The lower 4 bits are input to the column address buffer (3).

Writing to the memory cell array (7) is performed in two cycles, and in the first cycle, 16 words that are sequentially input to the data input buffer (5) are written to the column latch (
1) are sequentially written to the 16 address locations.

During this time, the contents of the column address buffer (3) are rooo.
oJ to rllllJ, this content is decoded by the column decoder (4), and the content of the data input buffer (5) is written to the position of the column latch fil selected by the decoding result. Column latch (1
), the first cycle ends and the second cycle begins.

The column address is from roooOJ to rllllJ'!
Since the row address does not change while the row address changes in the row decoder (6), one row (
row) is selected. The contents of column latch (1), 16 words x 8 bits, are written at once to this selected row. When this write is completed, the value 1 is added to the LSH of the row address, and then the first cycle of the next stage begins.

FIG. 5 is an operation timing chart showing the conventional timing in the operation of FIG. 4, in which the signal is logic "0" and WE is logic "1" for a read cycle, and both CE and WE are logic "0" for a write cycle. Show the cycle. At the beginning of this write cycle, a timer (not shown) is set and the timer output becomes a logic "1". While the timer output is logic "1", the external write enable signal becomes logic "1" and the first cycle is executed.

When the external write enable signal is logic "1", the address (column address) is latched into the column address buffer (3) at the later falling edge of CE or WE. This column address is decoded by the column decoder (4) to select one word in the column latch (1).

On the earlier rising edge of CE, WE, the data in the data manual buffer (5) is written to the selected word in the column latch (1). This operation is repeated while the external write enable signal is logic "1";
0'', external control signals such as CE and WE are no longer accepted, and the contents of the column latch (1) are written at once to all columns of the row selected by the row decoder (6).

[Problem that the invention seeks to solve]

The conventional device is configured as described above, and since the falling point of the timer output is not necessarily synchronized with external signals such as CE and WE, both CE and WE are logic "0". If the timer output falls while writing data to the column latch (1), and therefore the external write enable signal falls, there is a possibility that correct data may not be written to the column latch (1). The right part of FIG. 3 shows this, and at the falling edge of WE, the address
1111 J address) is latched and the next WE
The correct data Dn should be written at the rising edge of the rising edge, but since the external write enable signal fell before that, external control is no longer possible after this falling edge. The point is configured to behave similarly to the 100 rising points,
Therefore, there is a problem that erroneous data Dn' may be written at the address An.

This invention was made to solve the above problems, and provides a semiconductor memory device in which erroneous data is not written to the column latch (1) at the end of the first cycle. The purpose is to

[Means for solving problems]

In the present invention, the end of the first cycle is notified to the semiconductor memory device using another signal transmission method without using a timer. It is easy for an external circuit that writes to the semiconductor memory device to know the end of the first cycle. In other words, since the signal n etc. are output from an external circuit, WE'
The external circuit can detect that the first cycle has ended by counting whether the first cycle is set to logic "0" and then becomes logic "1", and this detected signal is transmitted to the semiconductor device. It's okay.

[Effect]

The external circuit that controls writing to the column latch is the first
After confirming the completion of the cycle, a signal is sent to the semiconductor memory circuit, so that the external write enable signal will not fall prematurely.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is an operation time chart showing the operation in one embodiment of the present invention, which is shown in the same manner as FIG.
After recognizing that n has been written to the address position indicated by An, WE is set to logic "0" for a certain period while CE is kept at logic rlJ.

The rise of the sieve causes the external write enable signal to fall.

Further, a combination of signals in which WE remains at logic "0" for a certain period while fc maintains CE at logic "1" does not occur under other conditions.

FIG. 2 is an operation time chart showing another embodiment of the present invention. In this example, WE is kept at logic "1" and 0E is set.
is set to logic "0" for a certain period of time.

External write enable signal is signal OF (output enable)
It falls at the rising point.

FIG. 3 is an operation time chart showing still another embodiment of the present invention. In this example, 0E is kept at logic "0" and WEe is
Make the logic rOJ for a certain period of time. The external write enable signal falls at the rising edge of the signal WE.

Note that in all of the above embodiments, an external writable signal is used; however, any form of signal may be used as long as it indicates the boundary point between the first cycle and the second cycle. good.

〔Effect of the invention〕

As described above, according to the present invention, there is no possibility that erroneous data will be written to the column latch at the end of the first cycle of the EEPROM in which page mode writing is performed.

[Brief explanation of the drawing]

FIG. 1 is an operation time chart showing one embodiment of this invention, FIG. 2 is an operation time chart showing another embodiment of this invention, and FIG. 3 is an operation time chart showing still another embodiment of this invention. , FIG. 4 is a block diagram showing a write system of an EEPROM equipped with a page mode write function, and FIG. 5 is an operation time chart showing conventional operation costs. (1) is a column latch, (2) is a row address buffer, (3) is a column address buffer, (4) is a column decoder, (5) is a data input buffer, (6) is a row decoder, (7) is a memory cell array.

Claims (3)

[Claims] (1) Writing to the nonvolatile storage device is executed in first and second cycles, and in the first cycle, a predetermined number of data sequentially input from the external circuit corresponds to each data. After the predetermined number of data has been stored in the column latch, the data is temporarily stored in the column latch at the address position determined by the address signal input. In a semiconductor memory device that controls writing the predetermined number of data stored in the column latch at once to a nonvolatile memory in a range determined by an address signal input from the outside for the predetermined number of data, Means for counting by the external circuit that writing of the predetermined number of data has been completed by execution of the first cycle; A semiconductor memory device comprising a signal transmission means for notifying the nonvolatile memory device using a signal on a control signal line input to the device. (2) The signal transmission means is characterized by comprising means for setting the signal @WE@ (write enable) to logic "0" for a certain period of time while keeping the signal @CE@ (chip enable) at logic "1". A semiconductor memory device according to claim 1. (3) Claims characterized in that the signal transmission means includes means for setting the signal @0E@ (output enable) to logic "0" for a certain period of time while keeping the signal @CE@ at logic "1". 2. The semiconductor memory device according to item 1. (4) The signal transmission means includes means for keeping the signal @0E@ at logic "0" and setting the signal @WE@ at logic "0" for a certain period of time. semiconductor storage device.