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JPS6211914A - Dead load control method for converter - Google Patents

Dead load control method for converter

Info

Publication number
JPS6211914A
JPS6211914A JP15151685A JP15151685A JPS6211914A JP S6211914 A JPS6211914 A JP S6211914A JP 15151685 A JP15151685 A JP 15151685A JP 15151685 A JP15151685 A JP 15151685A JP S6211914 A JPS6211914 A JP S6211914A
Authority
JP
Japan
Prior art keywords
load
point
dead
dead load
output voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15151685A
Other languages
Japanese (ja)
Inventor
Yoshio Suzuki
義雄 鈴木
Yutaka Kuwata
豊 鍬田
Shinichiro Asami
浅見 真一郎
Ryoji Saito
斉藤 亮治
Keiichi Sato
啓一 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Origin Electric Co Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Origin Electric Co Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Origin Electric Co Ltd, Nippon Telegraph and Telephone Corp filed Critical Origin Electric Co Ltd
Priority to JP15151685A priority Critical patent/JPS6211914A/en
Publication of JPS6211914A publication Critical patent/JPS6211914A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To reduce the electric power loss during the light load and to improve the reduction effect especially in a parallel operation mode and at the same time to prevent a hunting phenomenon due to the hysteresis characteristics, by providing a dead load and a variable impedance element connected in series. CONSTITUTION:When the output voltage level rises up to a dead load application point A in a light load state, an operational amplifier 7 delivers a difference signal having a level equivalent to the difference between the reference voltage level and the detecting voltage level of the output voltage to a driving circuit 8. The circuit 8 applies a control signal having a level corresponding to said difference signal to a variable impedance element 4 for linear control of the impedance. Thus the impedance of the element 4 is controlled so that the sum of the load current flowing to a load 2 and the dead load current flowing via a dead load 5 connected in series to the element 4 is approximately equal to the current I3 at a point A within a range between the point A and a no-load point. Therefore the output voltage is approximately equal to the voltage V3 at the point A within a range between the point A and the no-load point. This reduces the electric power loss and especially improves the reduction effect in a parallel operation mode. Then it is possible to prevent a hunting phenomenon caused by the hysteresis characteristics.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は整流装置或いはDC−DCコ/バータのような
コンバータ装置における死負荷の制御方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for controlling dead load in a converter device such as a rectifier device or a DC-DC co/verter.

〔従来の技術〕[Conventional technology]

一般にコンバータ装置においては、負荷が軽くなると第
5図に示すようにコンバータの出力電圧が上昇すること
は広く知られている。この軽負荷時の出力電圧の上昇全
抑制するために、死負荷全投入することが従来から行わ
れておQ5例えば、コンバータ装置における従来の比較
的進歩した死負荷投入方法としては、特開昭59−18
5160号公報に開示されたものがある。
It is generally known that in converter devices, when the load becomes lighter, the output voltage of the converter increases as shown in FIG. In order to completely suppress the rise in output voltage during light loads, it has been conventionally done to completely turn on the dead load. 59-18
There is one disclosed in Japanese Patent No. 5160.

第6図乃至第5図によりこの従来例f:説明する0 第3図において、1はコンバータ、2は負荷、6は抵抗
R1とR2とからなる分圧回路、4′はスイッチ素子、
5は死負荷、及び11は第4図に示すようなヒステリシ
ス特性を有する比較回路である。この回路の動作説明を
第4図と第5図とを用いて行うと、コンバータ1の出力
電圧がIV、l より大きくなると、比較回路11の出
力電圧がVHとなり、スイッチ4′が閉じられることに
よQ死負荷5に電流が流れる。このとき、列負荷5の抵
抗値を適当な値に選んでおくことによりコンバータ1の
出力電圧’1lv21とI■41の間に設定し得るので
、軽負荷又は無負荷の状態にある間はスイッチ4′は閉
じた状態にある。
This conventional example f: will be explained with reference to FIG. 6 and FIG.
5 is a dead load, and 11 is a comparison circuit having hysteresis characteristics as shown in FIG. The operation of this circuit will be explained using FIGS. 4 and 5. When the output voltage of converter 1 becomes larger than IV, l, the output voltage of comparator circuit 11 becomes VH, and switch 4' is closed. A current flows through the dead load 5. At this time, by selecting the resistance value of the column load 5 to an appropriate value, the output voltage of the converter 1 can be set between '1lv21 and I'41, so that the switch can be switched while in a light load or no-load state. 4' is in the closed state.

そして負荷が正常状態となって出力電圧が1v21より
小さくなると、比較器6の出力電圧は■。
When the load becomes normal and the output voltage becomes smaller than 1v21, the output voltage of the comparator 6 becomes ■.

となり、スイッチ4′ヲ開放させる。これにより列負荷
には電流が流れなくなる。従って、負荷が正常の場合に
は列負荷5に電流は流れない。
Then, the switch 4' is opened. This causes no current to flow through the column load. Therefore, no current flows through the column load 5 when the load is normal.

〔発明が解決しようとする問題〕[Problem that the invention seeks to solve]

しかし、このような従来装置は列負荷の投入、除去にヒ
ステリシス特性を有しているので、次のような欠点をも
っている。第5図において、コンバータ1の出力電圧が
負荷曲線X1  に従って■3(出力電流I、)壕で上
昇すると、前述のとおp列負荷5が投入され、列負荷5
に電流(I2− I、 )が流れるのに伴い、コンバー
タ1の出力電圧は■2  に降下する。つまクコンバー
タ出力はA点からB点に降下し、更に軽負荷になるのに
伴いコンバータの出力は変更された別の曲MAX2 に
従って上昇する0出方がA点からB点に降下(列負荷投
入の臨界点Aの電圧よシ低い)したことによシ死負荷5
全切シ離して再び元の負荷曲線X1のA点近傍に戻らな
いようつまクハンチングしないようにヒステリシス全役
け、出力電流が増えて出力電圧が電圧■2  よシ成る
電圧だけ低いVl (C点)まで降下したとき、列負荷
5を切シ離し、元の負荷曲線X1の任意の点DK戻るよ
うにしなければならない〇第5図からも分るよう、C点
においては、負荷2と列負荷5に流れる電流の和が■□
 (負荷電流はIC)になり、かなシ大きな電流(I、
−Ic)が列負荷5に流れることになシミ力損失を大き
なものとする。つまシヒステリシスが小さけれはハンチ
ング現象を起して装置の動作が不安定になシ、ヒステリ
シスが大きければ死負舊の開放が遅れると共に列負荷に
流れる電流が大きくなるので、電力損失がかな9大きく
なってしまう0 〔問題点全解決するための手段〕 コンバータの出力端子間に直列接続した列負荷と可変イ
ンピーダンス素子を備え、出力電圧が死負荷投入電圧に
達したとき前記可変インピーダンス素子のインピーダン
スを出力電圧に応じて制御する。
However, such conventional devices have hysteresis characteristics in applying and removing column loads, and therefore have the following drawbacks. In FIG. 5, when the output voltage of converter 1 rises at 3 (output current I) according to load curve X1, p-series load 5 is applied as described above, and
As the current (I2-I, ) flows through , the output voltage of converter 1 drops to ■2. The converter output drops from point A to point B, and as the load becomes lighter, the converter output increases according to another song MAX2 that has been changed. Dead load 5 due to the voltage lower than the critical point A of input
After the complete disconnection, the hysteresis is fully utilized to prevent pinch hunting so as not to return to the vicinity of point A on the original load curve When the load 5 descends to point DK, the column load 5 must be separated and returned to an arbitrary point DK on the original load curve The sum of the current flowing through load 5 is
(The load current is IC), and the large current (I,
-Ic) flows into the column load 5, causing a large stain force loss. If the hysteresis is small, a hunting phenomenon will occur and the operation of the device will become unstable; if the hysteresis is large, the release of the dead cap will be delayed and the current flowing to the column load will increase, resulting in a large power loss. [Means for solving all problems] A converter is equipped with a column load and a variable impedance element connected in series between the output terminals, and when the output voltage reaches the dead load application voltage, the impedance of the variable impedance element is changed. Control according to output voltage.

〔作 用〕[For production]

死負荷投入電圧と無負荷電圧との間の範囲では、負荷に
流れる負荷電流と列負荷に流れる電流との和が前記死負
荷投入電圧に対応する電流値にほぼ等しくなるように、
前記可変インピーダンス素子のインピーダンスが制御さ
れる0〔実施例〕 21図及び第2図によル本発明の一実施例全説明する0 第1図において、第5図に示した記号と同一のものは同
一性あるものとし、4はトラ/ラスタのような可変イン
ピーダンス素子、6は死、負荷制御系及びAVR系共通
の基準電圧回路であり、これは基準電源E1抵抗R,、
定電圧ダイオードZD、この定電圧ダイオードZDの両
端間に互いに直列接続された抵抗R1イ/ピーダンス素
子z1及び抵抗R6からなる。また7゜8はそれぞれ死
負荷制御系の演算増幅器、駆動回路、9.10はそれぞ
れAVR系の演算増幅器、駆動回路であり、説明が分り
易いように演算増幅器7と9の出力電圧検出入力端子(
非反転端子)は同一点に接続されており、ま九それら反
転入力端子は同一の基準電圧源によりバイアスされる抵
抗R4とインピーダンス素子2との接続点、インピーダ
ンス素子2と抵抗R6との接続点に夫々接続されてお9
、常に必ず演算増幅器7の反転端子の基準電圧が演算増
幅器90反転端子の基準電圧より高くなるよう設定され
ている。
In the range between the dead load application voltage and the no-load voltage, the sum of the load current flowing through the load and the current flowing through the string load is approximately equal to the current value corresponding to the dead load application voltage,
The impedance of the variable impedance element is controlled. [Embodiment] An embodiment of the present invention will be fully explained with reference to FIG. 21 and FIG. 2. In FIG. 1, the same symbols as those shown in FIG. 5 are assumed to be the same, 4 is a variable impedance element such as a tracker/raster, 6 is a reference voltage circuit common to the load control system and AVR system, and this is the reference power supply E1 resistor R, .
It consists of a constant voltage diode ZD, a resistor R1, an impedance element z1, and a resistor R6 connected in series between both ends of the constant voltage diode ZD. Further, 7°8 is an operational amplifier and a drive circuit for the dead load control system, respectively, and 9 and 10 are an operational amplifier and a drive circuit for the AVR system, respectively.For easy explanation, the output voltage detection input terminals of operational amplifiers 7 and 9 are shown. (
The non-inverting terminals) are connected to the same point, and the inverting input terminals are connected to the connection point between resistor R4 and impedance element 2 biased by the same reference voltage source, and the connection point between impedance element 2 and resistor R6. are connected to 9 respectively.
The reference voltage at the inverting terminal of the operational amplifier 7 is always set to be higher than the reference voltage at the inverting terminal of the operational amplifier 90.

従って一負荷電圧がある第1の設定レベルまで上昇する
と、AVR制御系の演算増幅器9及び駆動回路10が出
力電圧を降下させるようコンバーターに作用するが、死
負荷制御系の演算増幅器7及び駆動回路8は第1の設定
レベルよシ高いある第2の設定レベルまで出力電圧が上
昇しなければ可変インピーダンス累子4に制御信号を与
えない。軽負荷状態が進み、AVR制御系の演算増幅器
9及び駆動回路10がコンバータ1全最小パルス幅で動
作させるよう制御しているにも拘らず、出力電圧が第2
の設定レベル、つ−1列負荷投入点Aまで上昇すると、
演算増幅器7は基準電圧と出力電圧の検出電圧との差に
応じた大きさの差信号全駆動回路8へ出力し、駆動回路
8はその差信号に応じた大きさの制御信号全可変インピ
ーダンス素子4に与え、そのインピーダンスを線形的に
制御する。この結果、死貝荷投入点Aと無負荷点間の範
囲では負荷2に流れる負荷電流と、可変インピーダンス
素子4と列負荷5を介して流れる死貝荷電流との和が、
死貝荷投入点Aでの電流■3 にほぼ等しくなるよう、
可変インピーダンス素子4のインピーダンスは制御され
る。従って、第2図に示すように死貝荷投入点Aから無
負荷点に至る範囲では、出力電圧が死貝荷投入点Aの電
圧■3  にほぼ等しい電圧に保持される。
Therefore, when one load voltage rises to a certain first set level, the operational amplifier 9 and drive circuit 10 of the AVR control system act on the converter to lower the output voltage, but the operational amplifier 7 and drive circuit of the dead load control system act on the converter to reduce the output voltage. 8 does not apply a control signal to the variable impedance regulator 4 unless the output voltage rises to a certain second set level that is higher than the first set level. The light load condition progresses, and even though the operational amplifier 9 and drive circuit 10 of the AVR control system are controlling the converter 1 to operate at the minimum pulse width, the output voltage is
When the set level of 1-1 rises to the load application point A,
The operational amplifier 7 outputs a difference signal of a magnitude corresponding to the difference between the reference voltage and the detection voltage of the output voltage to a full drive circuit 8, and the drive circuit 8 outputs a control signal of a magnitude corresponding to the difference signal to a fully variable impedance element. 4 and linearly control its impedance. As a result, in the range between the dead shell loading point A and the no-load point, the sum of the load current flowing through the load 2 and the dead shell current flowing through the variable impedance element 4 and the column load 5 is:
The current at dead shell loading point A is approximately equal to ■3.
The impedance of variable impedance element 4 is controlled. Therefore, as shown in FIG. 2, in the range from the dead shell loading point A to the no-load point, the output voltage is maintained at a voltage approximately equal to the voltage 3 at the dead shell loading point A.

以上の実施例ではコンバータ単体で運転する場合につい
て述べたが、2台以上のコンバータを並列運転する場合
にも同様に適用でき、各コンバータ毎に、或いはこれら
共通に可変インピーダンス素子及び列負荷全接続するこ
とが出来る0 〔発明の効果〕 この発明によれは、死貝荷投入点から無負荷点に至る範
囲では、負荷電流と死貝荷電流との和の電流が死貝荷投
入点の電流にほぼ等しい値に保持されるので、軽負荷時
の電力損失全軽減でき、特にコンバータ全並列運転した
場合にはその効果が著しい。
Although the above embodiments have been described for the case where the converter is operated alone, it can also be applied to the case where two or more converters are operated in parallel. [Effect of the Invention] According to the present invention, in the range from the dead shell loading point to the no-load point, the sum of the load current and the dead shell loading current is equal to the current at the dead shell loading point. Since it is maintained at a value approximately equal to , it is possible to completely reduce power loss during light loads, and this effect is particularly significant when all converters are operated in parallel.

更にまた従来のようにヒステリシス特性を設ける必要が
なく、ヒステリシス特性に起因するハ/チ/グ全起すこ
ともない。
Furthermore, there is no need to provide a hysteresis characteristic as in the conventional case, and there is no occurrence of H/CH/G caused by the hysteresis characteristic.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例全実施するための装置の概略
を示す図、第2図は本発明全説明するための図、第3図
乃至第5図は従来例全説明するための図である。 1・・・コンバータ    2・・・負荷6・・・分圧
回路 4・・・可変インピーダンス素子 5・・・列負荷6・
・・基準電圧回路   7,9・・・演算回路8.10
・・・駆動回路 日本電信電話株式会社 タ nへ?−墾5王1;−1)←
FIG. 1 is a diagram schematically showing an apparatus for carrying out an embodiment of the present invention, FIG. 2 is a diagram for fully explaining the present invention, and FIGS. 3 to 5 are diagrams for fully explaining a conventional example. It is a diagram. 1... Converter 2... Load 6... Voltage divider circuit 4... Variable impedance element 5... Column load 6.
...Reference voltage circuit 7,9...Arithmetic circuit 8.10
...Drive circuit to Nippon Telegraph and Telephone Corporation tan? -Ken 5 Wang 1;-1)←

Claims (1)

【特許請求の範囲】[Claims] 直列接続された死負荷と可変インピーダンス素子とをコ
ンバータの出力端子間に備えたコンバータ装置において
、負荷が軽くなるのに伴い前記コンバータの出力電圧が
上昇して予め決められた死負荷投入電圧に達したとき前
記可変インピーダンス素子のインピーダンスの制御を開
始し、前記死負荷投入電圧と無負荷電圧との間の範囲で
は負荷電流及び死負荷電流の和が前記死負荷投入電圧に
対応する電流値にほぼ等しくなるように前記可変インピ
ーダンス素子のインピーダンスを制御することを特徴と
するコンバータの死負荷制御方法。
In a converter device including a series-connected dead load and a variable impedance element between the output terminals of a converter, as the load becomes lighter, the output voltage of the converter increases to reach a predetermined dead load application voltage. When this happens, control of the impedance of the variable impedance element is started, and the sum of the load current and the dead load current is approximately equal to the current value corresponding to the dead load application voltage in the range between the dead load application voltage and the no-load voltage. A dead load control method for a converter, characterized in that the impedance of the variable impedance element is controlled so as to be equal.
JP15151685A 1985-07-10 1985-07-10 Dead load control method for converter Pending JPS6211914A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15151685A JPS6211914A (en) 1985-07-10 1985-07-10 Dead load control method for converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15151685A JPS6211914A (en) 1985-07-10 1985-07-10 Dead load control method for converter

Publications (1)

Publication Number Publication Date
JPS6211914A true JPS6211914A (en) 1987-01-20

Family

ID=15520216

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15151685A Pending JPS6211914A (en) 1985-07-10 1985-07-10 Dead load control method for converter

Country Status (1)

Country Link
JP (1) JPS6211914A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003070241A (en) * 2001-08-24 2003-03-07 Toshiba Corp Power supply unit
WO2015125427A1 (en) * 2014-02-24 2015-08-27 株式会社デンソー Power conversion system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS573116A (en) * 1980-06-06 1982-01-08 Nec Corp Converter

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS573116A (en) * 1980-06-06 1982-01-08 Nec Corp Converter

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003070241A (en) * 2001-08-24 2003-03-07 Toshiba Corp Power supply unit
WO2015125427A1 (en) * 2014-02-24 2015-08-27 株式会社デンソー Power conversion system
JP2015159653A (en) * 2014-02-24 2015-09-03 株式会社デンソー power conversion system

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