JPS62109133A - Microprogram controller - Google Patents

Abstract

PURPOSE:To obtain a conditional branch microinstruction having a high executing speed with a short conditional field by selecting one of plural combinations produced by a combination generating means that attains its function according to the contents of a latch with which the value can be set with execution of a microinstruction. CONSTITUTION:A strobe signal is produced when a state selection latch 110 as a destination register for transfer microinstructions. Then the lower 4 bits of a data bus are latched by a state selection latch 110. A state generating circuit 111 produces 16 types of state signals G0-G15 at a time according to the contents of SF, ZF, CF and OF respectively. A state selector 112 decodes the 4-bit data and defines the state signal Gn that satisfies the decoding conditions as a selection state signal SEL. The signal SEL is connected to a single input STATEm of a selection selector 105 as a single condition of a conditional branch microinstruction. Then the selection state signal STATEm is checked as long as the contents of a conditional field COND of the conditional branch microinstruction are equal to (m).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to microprogram branch control in an information processing device that employs a microprogram control method.

[Conventional technology]

Conventionally, in an information processing apparatus employing a microprogram control method using a program number counter, the control flow (sequence) is changed by executing a PFXm microinstruction called a branch microinstruction. A branch microinstruction is implemented by replacing all or part of the current contents of a program number counter with the contents of a branch destination address field that the branch microinstruction has as an operand.

At this time, a branch microinstruction that has a condition field as another operand is called a conditional branch microinstruction. Only branch operations are performed.

FIG. 4 is a diagram showing the configuration of a conventional microprogram<1ilp device. The microinstruction register 403 is a microinstruction memory storing microinstructions specified by the contents of the microinstruction program counter 401.
The contents of 402 are latched.

Microinstruction register 4 in microinstruction decoder 404
When it is detected that the microinstruction latched in 03 is a conditional branch microinstruction, the detection signal CBR
ANCH is issued.

In this conventional example, the conditional branch microinstruction is as shown in FIG.
It has the format shown in a), where C0ND is a condition field of length C bits specifying the condition to be checked, and ADR8 is an address field of length C bits containing information regarding address control. Condition selector 40
5 is the state signal 5 specified by the content n of the condition field C0ND from among the 2△C types of state signals STATE(m) (m is O to 2△C) issued within the information processing device.
Select TATE(n). The branch signal generation circuit 406 issues a branch control signal BRANCH if the state signal 5TATE(n) selected by the condition selector 405 is true when the detection signals CBR, ANCH are issued.

The contents of micro-program counter 401 are normally incremented by one when execution of a microinstruction is completed, but when branch control signal BRANCH is issued, the lower C bits are replaced by the contents of address field ADR8.

That is, when the current content of the micro program counter 401 is M, if the branch control signal BRANCH is false, it will be updated to M+1 at the end of the execution of the micro instruction stored in the micro instruction register 403. ,
If the branch control signal BRANCH is true, ir+t(M/2△a-%2△a)+
(int is a function that takes the nearest integer).

One of the performance characteristics of branch microinstructions is that the range of addresses that can be controlled is large enough to write microprograms. That is, in the conventional example described above, the bit width a of the address field ADR8 is large.

In addition, as for other performance, conditional branch microinstructions require the ability to check more conditions. This means that the bit width C of the condition field C0ND is large.

By the way, in a microinstruction where the length of one microinstruction is fixed, the sum of the lengths of the address field ADR8 and the condition field C0ND (a+c) is:
You just can't change the word length of the microinstruction. Therefore, in actual conditional branch microinstructions, either the address control range or the number of test conditions is limited.

FIGS. 5(b) and 5(cl) show the format of a conditional branch microinstruction other than the conditional branch microinstruction used in the conventional example.

In particular, in microprograms that must implement complex functions, as the size of the program increases, the address control range inevitably becomes wider, and the number of test conditions is limited. As mentioned above, a conditional branch microinstruction with a condition field C0ND of fixed length C bits is limited to the number of conditions that can be tested, no more than 2ΔC. Some of the conditions to be checked are frequently referenced, while others are referenced only once in the entire microprogram. It would be extremely wasteful to uniformly give 1/2ΔC to these conditions with different reference frequencies.

Under the above circumstances, the selected condition needs to be the minimum necessary of all the conditions, that is, the greatest common divisor for the entire microprogram. For example, the Processor Status Word (PSW) allows a program to detect the status of an information processing device based on the magnitude relationship of binary numbers.
Let's consider making a decision based on the flag inside (called ). P
There is a sign flag (hereinafter referred to as 8E) regarding the operation in the SW.
, zero flag (hereinafter referred to as ZF), over 7°-.
It is assumed that there are flags (hereinafter referred to as OF) and carry flags (hereinafter referred to as C and F), and each flag changes as follows as a result of the operation of the subtraction instruction.

・SF・・・・・・Contents of the maximum significant bit (sign bit) of the operation result ・ZF・・・・・・Set if the operation result is zero, cleared if it is not zero ・OF・・・・・・・Set when an overflow (carry) occurs to the maximum significant bit or a borrow from the maximum significant bit during performance, otherwise it is cleared ・CF・・・・・・operation It is set when an overflow (carry) occurs from the most significant bit, or a borrow (pollow) occurs from the most significant bit; otherwise, it is cleared.

The magnitude relationship between two binary numbers can be determined by the value of the above operation-related flag that changes due to subtraction, but the meaning of the flag differs depending on whether the binary number is signed or unsigned. .

In other words, there are the following types of magnitude relationships between two signed binary numbers (letters are abbreviations, and numbers in parentheses are symbolic descriptions.・・・・・・
...... Greater than or equal to GT (>) ... GE (≧) equal ...
・－・・・・・・・・・・・・・・・・・・・・・・・・
...Less than or equal to EQ (=)...
・Less than LP, (≦)・・・・・・・・・・・・
・・・・・・・・・・・・・・・・・・LT(<)Not equal・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・NE (〆) There are also the following types of magnitude relationships between two unsigned binary numbers (alphabetic characters are abbreviations, and symbols in parentheses are descriptions).

Bigger・・・・・・・・・・・・・・・・・・
・・・・・・・・・Greater than or equal to A(〉)・・・・・・Equal to AE(≧)・・・・・・・・・
・・・・・・・・・・・・・・・・・・・・・・・・
...Less than or equal to E Q, (=')...Less than BE (≦)...
・・・・・・・・・・・・・・・・・・・・・B(〈)
Not equal・・・・・・・・・・・・・・・・・・
・・・・・・・・・NE(7') Furthermore, SF, Z
Adding that the flags F, OF, and CF can be checked, the above relationship is established when the flags in PSW satisfy the following conditions.

0T------...((SF eor OF )or
ZP )=OGE-...-(SF eor O
F)=0EQ...ZF=1 LE...--((SF eor 0F)or
ZF')=ILT-=・(SP eor 0)F
=1NE...zp=.

A-----・--(CP or ZF)=OA
E...cp=.

BE −・−−−(CF or ZF )=
1B・・・・・・CF=1 P・・・・・・S F=O M・・・・・・S F'=1NO・・・・・・
・OF200・・・・・・・・・0F=1 As mentioned above, when checking all the magnitude relationships of signed binary numbers and unsigned binary numbers, at least 14 types of conditions can be selected. something is required. Furthermore, if it is possible to further select true or false for the selected condition, the number of selection types can be reduced to eight.

The greatest common divisor of the conditions checked here includes S
There are 4% i-class flag conditions: F, Z F'', OF, and CF.If all of the above states were checked using only conditional branch microinstructions related to these conditions, multiple branches may occur depending on the type of state. This cannot be checked without the use of microinstructions, resulting in an abnormally long execution time or unbalanced execution time depending on the conditions.

Generally, in a microprogram control system with a program counter, a branch microinstruction is executed,
In this case, more execution time is consumed compared to when the program flows sequentially, so if branch microinstructions are executed frequently, the execution efficiency of the microprogram will drop significantly.

For example, check GT and if greater than PROCG
If it is not larger than T (this is as follows if we consider the process of branching to PROCNGT.Here, the if statement describes a conditional branch microinstruction, and the goto statement describes a branching microinstruction. , the branch is not beef 2
The joint instruction can be executed in T basic cycles, but if a branch occurs, it will be executed in 2T basic cycles.

if ZF=1 then goto P几0CNG
T；if 5F=l then goto TEMP
;if oF=o tllen goto PROC
-NGT; goto PROC-NGT; TENIP: if op=1then goto PROC-GT;
PROCNGT: In the above example, it consumes 5 words of microinstruction memory, and depending on the SF, ZF and OF states,
It will take an execution time ranging from 2T cycles to 5T cycles.

As described above, in order to check a plurality of complicated conditions, a plurality of selection conditions are required, or a plurality of microinstructions are used, thereby requiring a long execution time.

[Problem that the invention seeks to solve]

In view of the drawbacks of the conventional example, the present invention provides a conditional branch microinstruction with a short condition field and fast execution time for detecting a state in which multiple combinations exist although they are not used frequently. It is in.

[Means for solving problems]

The present invention provides means for generating in advance only the combinations required by a microprogram from among all possible combinations of a plurality of states, a latch whose value can be set by executing a microinstruction, and a latch whose value can be set according to the contents of the latch. It is characterized by comprising means for selecting one of the plurality of combinations generated by the means for generating combinations.

[Function/principle of the invention]

The present invention generates necessary combination states in advance based on basic states, and selects only one condition from among the combination states by setting specified conditions in latches that specify the conditions to be selected. However, by checking the selected condition with a conditional branch microinstruction, the conditions required by the conditional branch microinstruction are unified, regardless of the type of clause to be checked.

Embodiment] The configuration and operation of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention.

The state generation circuit 111 inputs the values f8F, ZF, CF, and OF related to the calculation of psw, and generates two signed binary numbers 1d and IS and unsigned binary numbers Ud and Us as shown in Table 1. The magnitude relationship and SF are determined by the subtraction result.
, ZF, CF, the contents of OF itself and the inverted state signal GO
This is a combinational circuit that generates ~G15. # state selection latch 110 is a 4-bit latch that latches the lower 4 bits of data bus 100 in response to strobe signal 5TROBE. The state selector 112 also receives 16 types of state signals Go, which are generated by the state generation circuit 111&ζ.
This is a multiplexer that selects and outputs the status signal SEL shown in Table 2 from among the status signals SEL G15 according to the contents of the status selection latch 110.

First, the condition selection latch 110 is selected as a destination register resource for a microinstruction (hereinafter, this type of microinstruction is referred to as a transfer microinstruction) that controls data transfer within an information processing device using the data bus 100. Then, a strobe signal 5TROBB is generated, and the contents n of the lower 4 bits of the data bus are latched into the condition selection latch. State generation circuit 111, state selection latch 11
SF, Z, which is always input regardless of the transfer operation to 0
F.

There are 16 types of status signals Go depending on the contents of CF and OF.
-015 is generated at the same time. The state selector 112 selects the 4-bit data n stored in the state selection latch 110.
Among the 16 types of state signals C)Q to G15, the state signal On that satisfies the decoding conditions is output as the selected state signal SEL. The selected state signal SEL generated by state selector 112 is used as a conditional branch microinstruction no condition to
Connected to TATEm. When the content of the condition field C0ND of the conditional branch microinstruction is m, the selection state signal 8T'ATEm, that is, the selection state signal SEL is checked.

Next, an example of operation will be shown. Two signed binary numbers A (OO12h) and B (0034h) are generated by the arithmetic microinstruction.
), the calculation-related flags 8F, ZF, CF, and OF change as shown below depending on the calculation result.

Binary number person Binary number B Flag state after subtraction 0012 0
034 8F=1. ZF=O, CF=1, 0F=1 The above flag relationship indicates that the calculation result is smaller. Now, if you need to check whether the result was greater than 12 (
1100b) is transferred to the state selection latch 111ζ. The state generating circuit 111 generates 16 types of states as shown in Table 3 according to SF, ZP, CF, and OF.

The state selector 112 is configured by the state selection latch 110 to
State G1 is selected as the selection state signal SEL. In this case, since the state signal G1 indicating that the value is larger is "1", the selected state signal SEL is also 0°.The fact that the selected state signal SEL is "1" means that the specified condition is met. It is also confirmed that the selection state signal SEL is 1.
01 indicates that the specified condition does not satisfy the state, so if the condition field C0ND of the conditional branch microinstruction becomes m, it means that the condition is not satisfied, so the branch control signal BR, ANCH is not issued and no branch operation is performed and the program counter advances to the next address M+1 where the conditional branch microinstruction is stored.

Further, if it is necessary to confirm that the results are not equal, 5 (0101b) is transferred to the state selection latch 110 by a transfer microinstruction.

The status signal G5 indicating that the results are not equal is 1 in this case.
11, so the selection condition signal SEL also becomes +11. Conditional branch microinstruction condition field C0ND
When becomes m, the condition is satisfied, so the branch control signal BRANCH is generated, and the contents is the address N (N=int(M/2A
Move to ayellow2Aa)+x).

Thus, the present invention allows different conditions to be checked with just one type of conditional branch microinstruction.

FIG. 2 shows an embodiment in which the present invention is used to realize processing of a conditional branch instruction (this type of instruction is called a macro instruction to distinguish it from a micro instruction) that is architecturally visible to the user. In FIG. 2, there are a processing unit (decode unit > 201) that fetches and decodes the macro instruction code, and a processing unit that actually executes all macro instructions by executing the microprogram (201).
It is possible to communicate with the execution unit 205 via a communication register 203.

Communication register 203U The conditional branch macro instruction used in the main IC1 execution unit 205 to convey necessary decode information from the decode unit 201 has an instruction format as shown in FIG. Here OP is the instruction code,
CON means the condition field, LOW means the lower address of the branch destination, and HI()H means the higher address of the branch destination. When the decode unit 201 fetches and decodes the conditional branch macro instruction, the communication register 203 latches the contents 2 of the 4-bit condition field CON obtained as a result of decoding the conditional branch macro instruction. The selection signal of the state selector 112, that is, the output of the state selection lunch 110 and the state signal GO~
If the selection relationship of G15 is matched with the condition field of the conditional branch macro instruction, there is no need to prepare a microprogram for each conditional branch macro instruction, and the entire conditional branch macro instruction can simply be prepared. Having one ready is enough.

That is, the processing for a conditional branch macro instruction in the execution unit 05 is as follows.

(2) Transfer the contents of the communication register 203 to the state selection latch 203 by a transfer microinstruction.

(2) Check the selection state signal 5TATEn by a conditional branch microinstruction whose condition field C0ND contains n.

(2) If the selection state signal SEL is 111, a branch occurs, and since the macro instruction actually requires a branch operation, control is transferred to the branch processing routine.

(2) If the selection state signal SEL is 111, no branch occurs and the macro instruction does not actually perform a branch operation, so the processing in the execution unit 205 corresponding to the conditional macro branch instruction ends.

Conventional processing consists of multiple steps for each specified condition.・) was required. By using the present invention, regardless of the number of conditions (16 in this embodiment), only one type of microprogram is required, and regardless of the content of the conditions, the microprogram required to determine whether the conditions are satisfied or not is sufficient. It is clear that there is no difference between the programs.

Next, another embodiment of the present invention will be described. FIG. 3 is a diagram showing the configuration of a non-inventive embodiment in which the state generating circuit 111 and the state selector 112 are integrated in the first embodiment of the present invention to simplify the structure. In this implementation U], the operation-related flags SF, ZF', CF,
OB" and the outputs of the state selection latch 110 are both connected to the selection condition generation circuit 600, and the outputs of the state selection latch 110 are connected to the selection condition generation circuit 600.
A direct selection condition signal S E L is generated from 00.

The selection condition generation circuit 600 is a combinational logic circuit having the logic shown in Table 4. The combinatorial logic shown in Table 4 is obtained by calculating the logical OR of the entire logic composed only of logical products having 18 product terms. Such combinational logic circuits are implemented using PLA (Programmable Logic Array), which is a well-known implementation technology for combinational logic circuits.
This can be realized using . The use of PLAi greatly simplifies the circuit configuration, and even in the case of stacked circuits, the circuit arrangement (layout) is simplified and the design effectiveness is improved.

〔Effect of the invention〕

As explained above, by using the present invention, conditional branch microinstructions that judge many combinational states with different reference frequencies can be used at high speeds without increasing the amount of condition fields and regardless of the type of state being tested. This makes it possible to process

Furthermore, since microprograms can be shared, it is possible to reduce the capacity of a storage device that stores microprograms. Furthermore, by using PLA technology, it is possible to simplify the circuit configuration.

Output signal Logic □ Comment Go (not (SF) + 0F) 4 (SF +
noL(OF))+not(ZF) Id)IsGl
(not (8F)+0F)-%(SF+no
t(OF)) Id≧Eng 3G 2
ZF
Id=Is, Ud=tIsG 3 SF'
%not (OF)+not(SF)+OF+ZP
Id≦X$G 4 SF+
not(OF")+noj(SF)-1+OF
Id<l5G5 not(
ZF)
Id〆Is, Ud〆hG 6 not (C
F)% not (ZF)
Ud) Us07 not (CF)
[Jd
≧U30RCF+ZF
Ud≦rJsG9 CF

Ud<Us output signal logic GIOOF G 11 not (OF) G12 5F G13 not (SF) G14 0 0000 Gll Of)
00001 GIOGl.

0010 G9 G2
00011 07 G3
00100 02 G4
00101 G5 ()
5 10110 08
G6 00111 06
G7 01000 G12
G8 11001 G13
G9 11010 G14
GIO11011G15
Gll 01100 01
G12 11101 04
G13 01110 Go
()14 01111 o3
G15 1 table 2
Table 3 (nnnn-()OOOb)
and OF or [nnnn-0001bl an
d not (OF) or (nnnn=OX10b)
and CF or(nnnn-()O1lb″')
and not (CF) or (nnnn-01X
Ob) and ZF or [nnnn-(1101b
]and not(ZF) or(nnnn=0111
b'l and not(CF) and not(
ZF) or [nnnn=1000b1 and
SF [nnnn=1001bl and not (S
F) or(nnnn=1010b'l and
0Cnnnn”1011b1 and 1[nnnn
=11XOb] and SF and not (OF
) or [nnnn=11XObl and not
(SF) and OF or[nnnn=1110b
] and ZF or (nnnn=1101b] a
nd not(SF) and not(OF) or
15 (nnnn=1101b'l and
SF and 0FCnnnn”l111b] a
nd not(SF) and not(ZF) an
d not(OF) or(nnnn=1111b]a
nd SF and not (ZF) and CF table 4

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the invention, FIG. 2 is a diagram showing another embodiment of the invention, FIG. 3 is a diagram showing an embodiment of the invention with a simplified configuration, and FIG. FIG. 4 is a block diagram showing a conventional microprogram control device, FIG. 5 is a format diagram of a conditional branch microinstruction, and FIG. 6 is a format diagram of a conditional branch microinstruction. 100...Data path, 101...
Micro program Φ counter, 102...
Microinstruction memory, 103...Microinstruction register, 104...Microinstruction decoder,
105... Condition selector, 106...
Branch signal generation circuit, 110...state selection latch, 111...state generation circuit, 112...
・Status selector, 20 units...decode unit), 202...data meeting bus, 203...
...Communication latch, 204...
Data bus, 205... Execution unit, 40
1...Micro program counter, 40
2...Micro instruction memory, 403...
- Microinstruction register, 404...Microinstruction decoder, 405...Condition selector, 40
6...Branch signal generation circuit, 600...
Selection state generation circuit. Agent Susumu Uchihara 81 Figure 3 ・@4 Ward (previously 7 da D

Claims (1)

[Claims] Means for generating in advance only the combinations required by a microprogram from among all possible combinations of a plurality of states, a latch whose value can be set by executing a microinstruction, and generating the combination according to the contents of the latch. and a means for selecting one of the plurality of combinations generated by the means, the microprogram control device comprising: means for selecting one of a plurality of combinations generated by the means, and determining a condition for a conditional branch operation using the combination state selected by the selecting means. .