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JPS62108539A - Manufacture of soi-structure semiconductor device - Google Patents

Manufacture of soi-structure semiconductor device

Info

Publication number
JPS62108539A
JPS62108539A JP24794485A JP24794485A JPS62108539A JP S62108539 A JPS62108539 A JP S62108539A JP 24794485 A JP24794485 A JP 24794485A JP 24794485 A JP24794485 A JP 24794485A JP S62108539 A JPS62108539 A JP S62108539A
Authority
JP
Japan
Prior art keywords
layer
type
layers
silicon
island
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24794485A
Other languages
Japanese (ja)
Inventor
Shinichiro Kaneko
信一郎 金子
Fumio Otoi
音居 文雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP24794485A priority Critical patent/JPS62108539A/en
Publication of JPS62108539A publication Critical patent/JPS62108539A/en
Pending legal-status Critical Current

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  • Element Separation (AREA)

Abstract

PURPOSE:To inhibit the generation of dislocation-defects to an silicon island by forming the single crystal N-type silicon island onto the surface of a P-type silicon substrate, changing low-concentration and high-concentration P-type layers into porous silicon layers through anodizing treatment and converting the layers into porous silicon oxide film layers. CONSTITUTION:A high-concentration P-type layer 12 and a P-type layer 13 in concentration lower than the layer 12 are shaped on the surface side of a P-type silicon substrate 11. An N-type epitaxial layer and a desired single crystal N-type silicon island 14 are formed onto the surface of the substrate 11, and the layers 13 and 12 are turned into porous silicon layers 15, 16 through anodizing treatment. The density of the layer 16 is made comparatively large and the density of the layer 15 small. The layers 15, 16 are changed into porous silicon oxide film layers 17, 18 through thermal oxidation treatment, and the N-type silicon island 14 insulated and isolated by the layers 17, 18 is obtained. Accordingly, the porous silicon layers just under the island 14 have small density, thus inhibiting dislocations and defects generated in the island 14.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は、半導体装置、特にS OI (5ilic
onOn In5ulator )構造半導体装置の製
造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) This invention relates to semiconductor devices, particularly SOI (5ilic
The present invention relates to a method of manufacturing a semiconductor device with an on-on inverter structure.

(従来の技術) 第2図は、IEDM 84 P800〜803 に記載
されるような従来のSOI構造半導体装置の製造方法を
示す工程断面図である。この従来方法では、まず、P型
シリコン基板lの表面側に高濃度P型層(P中層)2を
イオン・インプランテーションまたは拡散法により形成
する(第2図(a))。しかる後、そのP型シリコン基
板l上に、N型エピタキシャル層の形成と、周知のホト
リソ・エツチング技術により、所望のN型シリコン島3
を形成する(第2図(b))。その後、陽極化成処理に
より、高濃度P型層2を多孔質シリコン層4に変化させ
る(第2図(c))。その後、熱酸化処理を施すことに
より、多孔質シリコン層4を多孔質シリコン酸化膜層5
としく第2図(d))、これKよシ多孔質シリコン酸化
膜層5により絶縁分離されたN型シリコン島3を有する
構造を得る。この時、N型シリコン島3の表面には薄く
熱酸化膜6が形成される。なお、この絶縁分離法は、多
孔質シリコンの酸化速度と単結晶シリコンの酸化速度の
差を利用した方法である。
(Prior Art) FIG. 2 is a process cross-sectional view showing a conventional method for manufacturing an SOI structure semiconductor device as described in IEDM 84 P800-803. In this conventional method, first, a highly-concentrated P-type layer (P middle layer) 2 is formed on the surface side of a P-type silicon substrate 1 by ion implantation or a diffusion method (FIG. 2(a)). Thereafter, a desired N-type silicon island 3 is formed on the P-type silicon substrate 1 by forming an N-type epitaxial layer and using well-known photolithography and etching techniques.
(Fig. 2(b)). Thereafter, the highly concentrated P-type layer 2 is changed into a porous silicon layer 4 by anodization treatment (FIG. 2(c)). Thereafter, by performing thermal oxidation treatment, the porous silicon layer 4 is changed to the porous silicon oxide film layer 5.
As shown in FIG. 2(d), a structure having N-type silicon islands 3 insulated and isolated by a porous silicon oxide film layer 5 is obtained. At this time, a thin thermal oxide film 6 is formed on the surface of the N-type silicon island 3. Note that this insulation separation method is a method that utilizes the difference between the oxidation rate of porous silicon and the oxidation rate of single crystal silicon.

(発明が解決しようとする問題点) しかしながら、以上述べた従来方法では、高濃度P型層
2よシ得られる多孔質シリコン層4の密度が比較的大き
いため、この多孔質シリコン層4の酸化時に、シリコン
島3に転位・欠陥が発生しやすく、リーク電流などの素
子特性の劣化を招きやすいという問題点があった。
(Problems to be Solved by the Invention) However, in the conventional method described above, since the density of the porous silicon layer 4 obtained is relatively higher than that of the highly concentrated P-type layer 2, the porous silicon layer 4 is oxidized. At times, there is a problem in that dislocations and defects are likely to occur in the silicon island 3, which tends to cause deterioration of device characteristics such as leakage current.

この発明は上記の点に鑑みなされたもので、その目的は
、上述したシリコン島への転位・欠陥の発生を抑制し、
結晶性の良好なシリコン島を得ることができるSOI構
造半導体装置の製造方法を提供することにある。
This invention was made in view of the above points, and its purpose is to suppress the occurrence of dislocations and defects in the silicon islands mentioned above,
An object of the present invention is to provide a method for manufacturing an SOI structure semiconductor device that can obtain a silicon island with good crystallinity.

(問題点を解決するための手段) この発明では、P型シリコン基板の表面側に、所定深さ
に高濃度P型層、これよシ上の表面部に、前記高濃度P
型層よシは低濃度のP型層を形成し、そのようなP型シ
リコン基板上に単結晶N型シリコン島を形成した後、前
記低濃度・高濃度P型層を陽極化成処理により多孔質シ
リコン層とし、さらにこの多孔質シリコン層を多孔質シ
リコン酸化膜層とする。
(Means for Solving the Problems) In the present invention, a high concentration P type layer is formed at a predetermined depth on the surface side of a P type silicon substrate, and the high concentration P type layer is formed on the upper surface of the P type silicon substrate.
For the mold layer, a low concentration P type layer is formed, and after forming a single crystal N type silicon island on such a P type silicon substrate, the low concentration/high concentration P type layer is made porous by anodizing. Furthermore, this porous silicon layer is used as a porous silicon oxide film layer.

(作用) このような方法によれば、陽極化成処理されるP型層の
表面側が低濃度層であるため、単結晶N型シリコン島直
下の多孔質シリコン層密度は小さくなる。
(Function) According to such a method, since the surface side of the P-type layer to be anodized is a low concentration layer, the density of the porous silicon layer directly under the single-crystal N-type silicon island becomes small.

(実施例) 以下この発明の一実施例を第1図を参照して説明する。(Example) An embodiment of the present invention will be described below with reference to FIG.

第1図(a)において、11はP型シリコン基板で1)
、まず、このシリコン基板11の表面側所定深さに高濃
度P型層(P中層)12を公知の拡散技術により形成す
る。すると、シリコン基板11の表面側は、所定深さに
前記高濃度P型層12(比抵抗0,008Ω・百程度)
が形成され、それよシ上の表面部には、基板領域によっ
て、前記高濃度P型層12よシは低濃度のP型層13(
比抵抗10〜12Ω・crIK)が形成されることとな
る。
In Figure 1(a), 11 is a P-type silicon substrate 1)
First, a high concentration P type layer (P intermediate layer) 12 is formed at a predetermined depth on the surface side of this silicon substrate 11 by a known diffusion technique. Then, the high concentration P-type layer 12 (specific resistance 0,008Ω/about 100) is formed at a predetermined depth on the surface side of the silicon substrate 11.
is formed, and a low concentration P-type layer 13 (
A specific resistance of 10 to 12 Ω·crIK) is formed.

次に、そのP型シリコン基板11の表面上に、N型エピ
タキシャル層の形成と、周知のホトリソ・エツチング技
術により、所望の単結晶N型シリコン島14を形成する
(第1図(b))。
Next, a desired single-crystal N-type silicon island 14 is formed on the surface of the P-type silicon substrate 11 by forming an N-type epitaxial layer and using well-known photolithography and etching techniques (FIG. 1(b)). .

その後、陽極化成処理により、低濃度P型層13と高濃
度P型層12を多孔質シリコン層15.16とする(第
1図(c))。この時、生成される多孔質シリコン層1
5,16の密度は、変換前のP型層の濃度に依存する。
Thereafter, the low concentration P type layer 13 and the high concentration P type layer 12 are made into porous silicon layers 15 and 16 by anodization treatment (FIG. 1(c)). At this time, the porous silicon layer 1 generated
The density of 5,16 depends on the concentration of the P-type layer before conversion.

深い部分の多孔質シリコン層16は、高濃度P型層12
よシ得られるため、密度は比較的大きくなる。−万、N
型シリコン島14直下の表面側の多孔質シリコン層15
は、低濃度P型層13よυ得られるため、密度は小さく
なる。
The deep porous silicon layer 16 is a highly doped P-type layer 12.
The density is relatively large because it can be obtained easily. -10,000, N
Porous silicon layer 15 on the surface side directly below the mold silicon island 14
Since υ is obtained as compared to the low concentration P-type layer 13, the density becomes smaller.

その後、熱酸化処理を施して、多孔質シリコン層15.
16を多孔質シリコン酸化膜層17,18とすることに
より(第1図(d))、該多孔質シリコン酸化膜層17
,18で絶縁分離されたN型シリコン島14を有する構
造を得る。この時、N型シリコン島14直下の多孔質シ
リコン層(多孔質シリコン層15)は密度が小さいため
、N型シリコン島14に発生する転位や欠陥は抑制され
る。また、この熱酸化処理により、N型シリコン島14
の表面には、熱酸化膜19が薄く形成される。なお、こ
の絶縁分離法は、多孔質シリコンの酸化速度と単結晶シ
リコンの酸化速度の差を利用した方法である。
Thereafter, a thermal oxidation treatment is performed to form a porous silicon layer 15.
By making 16 into porous silicon oxide film layers 17 and 18 (FIG. 1(d)), the porous silicon oxide film layer 17
, 18 is obtained. At this time, since the porous silicon layer (porous silicon layer 15) directly under the N-type silicon island 14 has a low density, dislocations and defects occurring in the N-type silicon island 14 are suppressed. Also, by this thermal oxidation treatment, the N-type silicon island 14
A thin thermal oxide film 19 is formed on the surface. Note that this insulation separation method is a method that utilizes the difference between the oxidation rate of porous silicon and the oxidation rate of single crystal silicon.

(発明の効果) 以上詳述したように、この発明の方法では、陽極化成処
理されるP型層を、表面側から低濃度層、高濃度層の2
層とし、該P型層を陽極化成処理した時、多孔質シリコ
ン層の表面側の密度が小さくなるようにしたから、該多
孔質シリコン層を多孔質シリコン酸化膜層に変換する工
程において、単結晶N型シリコン島に発生する転位や欠
陥を抑制することができ、リーク電流の少ない優れた素
子を形成することができる。また、この発明の方法では
、低濃度P型層の下に高濃度P型層が存在しておシ、該
高濃度P型層では陽極化成が速く進むので、高濃度P型
層下のP型シリコン基板は殆ど化成されない状態、すな
わち、多孔質シリコン層を深く形成することなしに、幅
の広いシリコン島領域を得ることができる。
(Effects of the Invention) As detailed above, in the method of the present invention, the P-type layer to be anodized is divided into two layers, a low concentration layer and a high concentration layer, from the surface side.
layer, and when the P-type layer is anodized, the density on the surface side of the porous silicon layer is reduced, so in the process of converting the porous silicon layer into a porous silicon oxide layer, a simple Dislocations and defects occurring in crystalline N-type silicon islands can be suppressed, and an excellent element with low leakage current can be formed. In addition, in the method of the present invention, a high concentration P-type layer exists under the low concentration P-type layer, and since anodization proceeds quickly in the high concentration P-type layer, the P-type layer under the high concentration P-type layer is The mold silicon substrate is in a state where it is hardly chemically formed, that is, a wide silicon island region can be obtained without forming a deep porous silicon layer.

【図面の簡単な説明】[Brief explanation of drawings]

(図面) 第1図はこの発明のSOI構造半導体装置の製造方法の
一実施例を示す工程断面図、第2図は従来の方法を示す
工程断面図である。 11・・・P型シリコン基板、12・・・高濃度P型層
、13・・・低濃度P型層、14・・・単結晶N型シリ
コン島、15.16・・・多孔質シリコン層、17.1
8・・・多孔質シリコン酸化膜層。
(Drawings) FIG. 1 is a process sectional view showing an embodiment of the method for manufacturing an SOI structure semiconductor device of the present invention, and FIG. 2 is a process sectional view showing a conventional method. 11...P-type silicon substrate, 12...High concentration P-type layer, 13...Low concentration P-type layer, 14...Single crystal N-type silicon island, 15.16...Porous silicon layer , 17.1
8... Porous silicon oxide film layer.

Claims (1)

【特許請求の範囲】 (a)P型シリコン基板の表面側に、所定深さに高濃度
P型層、これより上の表面部に、前記高濃度P型層より
は低濃度のP型層を形成する工程と、(b)そのP型シ
リコン基板の表面上に単結晶N型シリコン島を形成する
工程と、 (c)その後、前記低濃度・高濃度P型層を陽極化成処
理により多孔質シリコン層とする工程と、(d)その後
、前記多孔質シリコン層を多孔質シリコン酸化膜層に変
換する工程とを具備してなるSOI構造半導体装置の製
造方法。
[Scope of Claims] (a) A high-concentration P-type layer at a predetermined depth on the surface side of a P-type silicon substrate, and a P-type layer with a lower concentration than the high-concentration P-type layer on the surface above this layer. (b) forming a single-crystal N-type silicon island on the surface of the P-type silicon substrate; (c) after that, the low-concentration/high-concentration P-type layer is made porous by anodizing. 1. A method for manufacturing an SOI structure semiconductor device, comprising the steps of: (d) converting the porous silicon layer into a porous silicon oxide film layer.
JP24794485A 1985-11-07 1985-11-07 Manufacture of soi-structure semiconductor device Pending JPS62108539A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24794485A JPS62108539A (en) 1985-11-07 1985-11-07 Manufacture of soi-structure semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24794485A JPS62108539A (en) 1985-11-07 1985-11-07 Manufacture of soi-structure semiconductor device

Publications (1)

Publication Number Publication Date
JPS62108539A true JPS62108539A (en) 1987-05-19

Family

ID=17170869

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24794485A Pending JPS62108539A (en) 1985-11-07 1985-11-07 Manufacture of soi-structure semiconductor device

Country Status (1)

Country Link
JP (1) JPS62108539A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6246068B1 (en) 1995-10-06 2001-06-12 Canon Kabushiki Kaisha Semiconductor article with porous structure
US7148119B1 (en) 1994-03-10 2006-12-12 Canon Kabushiki Kaisha Process for production of semiconductor substrate
JP2007123875A (en) * 2005-10-26 2007-05-17 Internatl Business Mach Corp <Ibm> Method for forming germanium-on-insulator semiconductor structure using porous layer and semiconductor structure formed by the method
KR100650078B1 (en) * 1997-12-26 2007-08-16 소니 가부시끼 가이샤 Semiconductor substrate and thin film semiconductor meterial, and method for manufacturing the same
US7566482B2 (en) 2003-09-30 2009-07-28 International Business Machines Corporation SOI by oxidation of porous silicon
US10833175B2 (en) 2015-06-04 2020-11-10 International Business Machines Corporation Formation of dislocation-free SiGe finFET using porous silicon

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7148119B1 (en) 1994-03-10 2006-12-12 Canon Kabushiki Kaisha Process for production of semiconductor substrate
US6246068B1 (en) 1995-10-06 2001-06-12 Canon Kabushiki Kaisha Semiconductor article with porous structure
KR100291501B1 (en) * 1995-10-06 2001-10-24 미다라이 후지오 Semiconductor substrate and manufacturing method thereof
KR100650078B1 (en) * 1997-12-26 2007-08-16 소니 가부시끼 가이샤 Semiconductor substrate and thin film semiconductor meterial, and method for manufacturing the same
US7566482B2 (en) 2003-09-30 2009-07-28 International Business Machines Corporation SOI by oxidation of porous silicon
JP2007123875A (en) * 2005-10-26 2007-05-17 Internatl Business Mach Corp <Ibm> Method for forming germanium-on-insulator semiconductor structure using porous layer and semiconductor structure formed by the method
US10833175B2 (en) 2015-06-04 2020-11-10 International Business Machines Corporation Formation of dislocation-free SiGe finFET using porous silicon

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