JPS6210742A - Microcomputer - Google Patents

Abstract

PURPOSE:To decrease a chip area by providing a means to generate a selecting signal to designate the access of either of plural PROM arrays and a register group to store data read by a reading means corresponding to a selecting signal. CONSTITUTION:At the time of writing the data, when a selecting signal 8 is '0', (1), the first FROM 3, (4) is selected by an address control circuit 9 and the instruction on a data bus 1 is written by a writing circuit 2. At the time of reading the data, when the selecting signal 8 is '0', (1), the first PROM 3, (4) is accessed by the address control circuit 9, simultaneously, the data are read by a reading circuit 5 as the condition is which registers 6 and 7 can be accepted, and latched to registers 6 and 7 through the data bus. Thus, by providing the address control circuit 9 and changing over the selecting signal 8, the writing circuit 2 and the reading circuit 5 can be commonly used by the first PROM 3 and the second PROM 4. Thus, the chip area can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer incorporating a plurality of PROMs.

[Conventional technology]

Conventionally, some microcomputers are equipped with a plurality of read-only memories (hereinafter referred to as ROMs) for storing different information such as instructions and table data for display. However, since the contents of the ROM are stored in microcomputers with a built-in ROM during the manufacturing stage, the contents of the ROM cannot be changed after the product is completed.
Instead, there are microcomputers that have a built-in electrically writable read-only memory (hereinafter referred to as PROM).

FIG. 2 is a block diagram showing a conventional example of a main part of a PROM section of a microcomputer incorporating two PROM arrays.

When data is stored in the circuit shown in FIG. 2, the selection signal 18 is set to the "θ" level, for example, to make the control circuit 20 ready for writing into the first PROM 13, and then the data bus 11 is transmitted to the control circuit 20, For example, instruction data on the data bus 11 is transferred to the first PROM through the write circuit 12.
13. Next, by setting the selection signal 18 to the "L" level, for example, the control circuit 20 is set to the second PROM.
14, the data bus 11 is connected to the data bus 11 through the control circuit 20 and the write circuit 21.
For example, the above table data is stored in the second PROM 14.

When reading data, the first PROM 13 and the second (7
) The PROMs 14 operate independently of each other, and when reading instruction data, the reading circuit 15 starts from the first PROM 13.
The instruction data is latched into the instruction register 16 through the instruction register 16.

When reading table data, the table data is latched from the second PROM 14 into the data register 17 through the read circuit 22.

[Problem that the invention seeks to solve]

As shown in FIG. 2, conventionally the first PR stores instructions.
In a microcomputer that incorporates multiple sets of PROMs, such as an OM and a second PROM that stores table data, each PROM must have independent write and read circuits, which results in an increase in chip area. There is a drawback.

[Means for solving problems]

The microcomputer of the present invention has data lines of a plurality of PROM arrays connected in common, a writing means for writing data to the plurality of PROM arrays, and a reading means for reading data from the plurality of PROM arrays. and means for generating a selection signal specifying access to one of the plurality of PROM arrays, and a register group for storing data read by the reading means in response to the selection signal. do.

By providing a common writing means and reading means for a plurality of PROM arrays in this manner, the chip area can be reduced.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of essential parts of an embodiment of a microcomputer according to the present invention. In this embodiment, two PROMs are built in, as in the conventional example shown in FIG.

The first PROM 3 and the second PROM 4 are connected to share a data line for inputting data, and the data on the data bus l is written by the write circuit 2, and the data is written via the read circuit 5. The data is read out and transferred to the data bus l.
is output to. The address control circuit 9 is the first PROM 3
and generates an address signal specifying a predetermined address PROM cell of the second PROM 4, and generates a predetermined address signal during writing and reading. Further, the address control circuit 9 is controlled by a selection signal 8 that selects either the first PROM 3 or the second PROM 4. For example, when writing or reading from a predetermined address of the first PROM 3, the selection signal 8 is set to "0" (low level), and the selection signal 8 is set to "1" when writing or reading to a predetermined address of the second PROM 4.
(high level) control. When the selection signal 8 is "O", the instruction register 6 latches the data on the data bus 1,
The data register 7 latches the data on the data bus 1 when the selection signal 8 is "L".

Next, operations in this embodiment, ie, data write and read operations, will be described.

(1) When writing data, when the selection signal 8 is 0'', the address control circuit 9
The second PROM 3 is selected, the instruction on the data bus 1 is written by the write circuit 2, and when the selection signal 8 is "1", the second PROM 4 is selected by the address control circuit 9,
Data on data bus 1 is written through write circuit 2.

(2) In the case of reading data When the selection signal 8 is "0", the first PROM 3 is accessed by the address control circuit 9, and at the same time the instruction register 6
The instruction is read out by the readout circuit 5 in a state where it can be accepted, and when the 0 selection signal 8 latched by the instruction register 6 via the data bus 1 is "1", the address control circuit 9 selects the second PROM 4. At the same time, the data register 7 is read out by the read circuit 5 and latched into the data register 7 via the data bus l.

In this way, by providing the address control circuit 9 and switching the selection signal 8, the first PROM 3 and the second PROM
4, the write circuit 2 and read circuit 5 can be shared.

Although this embodiment is an example of a microcomputer with two built-in PROMs, the present invention can also be applied to a microcomputer with three or more built-in PROMs.

〔Effect of the invention〕

As explained above, the present invention has the effect of reducing the chip area by using a common write circuit and read circuit for a plurality of PROMs, and by latching the read data into a predetermined register in response to a selection signal when reading data. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of the main parts of an embodiment of a microcomputer according to the present invention, and FIG. 2 is a block diagram of the main parts of a conventional example of a microcomputer incorporating two PROM arrays.
This is a link diagram. 1: Data bus, 2: Write circuit, 3: First (7
) PI (OM, 4: 2nd (7) PROM, 5: Read circuit, 6: Instruction register, 7: Data register, 8
: Selection signal, 9 near address control circuit.

Claims (1)

[Scope of Claims] A microcomputer incorporating a plurality of PROM arrays, wherein data lines of the plurality of PROM arrays are connected in common, and a writing means for writing data to the plurality of PROM arrays; reading means for reading data from a PROM array; means for generating a selection signal for designating access to one of the plurality of PROM arrays; and means for generating data read by the reading means in response to the selection signal. A microcomputer characterized by having a group of registers for storing data.