JPS62107301A - Programmable controller - Google Patents

Abstract

PURPOSE:To install a process input part ad a process output part to a place which has been separated from a CPU, by providing a watch dog timer (WDT) on a block unit of an IO, and impressing a power source for process output for the first time, after an access has been executed normally from a CPU in the process output side. CONSTITUTION:A power source for driving an output relay 13c for a process control is given by a power source 4 for process input. This power source generates by an interface circuit 13a a signal for confirming a fact that an access has been executed normally from a CPU 11, and drives a WDT circuit 130. The WDT 130 drives a transistor 131 for a prescribed time after the access has been executed normally, a relay 132 is driven and a contact 133 becomes on, and a power source 3 for process output is impressed to a process output. If the CPU or the process output part becomes abnormal and the WDT 130 is not brought to an access exceeding a prescribed time, the WDT becomes time-up, the transistor 131 becomes off, the contact point 133 becomes off, an output contact point 13d becomes off automatically, and a runaway, etc., of the process are prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a programmable controller, and particularly to failure detection and treatment when a failure is detected.

[Conventional technology]

FIG. 4 is a diagram showing the configuration of a conventional programmable controller. In the figure, (1) is the programmable controller control section, aυ is the CPU section, (6) is the process input section (PI), and (to) is the process output section ( PO). (
2) is the 5V logic power supply of the programmable controller, which supplies power to the programmable controller control unit (1) through the power line (202), and the 5■ power supply normal signal line (
201) notifies the CPU section (b) that the 6v power supply is normal.

(3) is the process output power supply, and in this device example, DC24
V is used, cll) is the contact point of W when the process output power supply is normal, and (801) is its power line. (4) is the process input power supply, which uses DC48V in this device example, and (6) is “ON” when the process input power is normal.
”, the contact (401) is its power line.05υ
is a relay that turns 1 ON' when the programmable controller is normal; (531 is a contact point of relay υ, and ward is a relay) is a surge killer. Note that (IO1) is a CPU normal signal.

FIG. 5 is a diagram showing details of the process output section (to) of this programmable controller (1), where (IJlla) is the interface section with the CPU αυ, (13b) is the memory that holds the output signal, []'lc ) is the output relay, (
18d) is a contact of the output relay (18c), (18e) is a surge killer of the output relay (18c), and (18f) is a transistor that drives the output relay (18C).

Next, the operation will be explained. The 5V logic power supply (2) is supplied to the programmable controller control unit (1) through the power line (202), and the 5V power supply normal signal line (201) is supplied to the programmable controller control unit (1) through the power line (202).
) to the CPU Oυ, the CPU QI) performs a self-check and sends a CPU normal signal to the process output power supply (3) through the CPU normal signal line (1IO). At this time, for process output [source (3)
) is operating normally, its contact C13) is 1oN.
1, and similarly, if the process input power supply (4) is operating normally, its contact 0 becomes 'ON'. So C
The relay (fill operates and contact F is activated by the PU normal signal.
J2J2i31 becomes 'ON'. Then contact Cj becomes 'ON'.
By turning ON', the process output power supplied through the power line (801) is applied to the process output section (2) of the programmable controller (1), and the final output becomes operational. In other words, the process output part α3 is C
PU 01) commands to the interface circuit (18a)
), it is stored in the output memory (18b), and the output drive transistor (18f) drives the output relay (18c) to turn the output contact (LAD) 'ON' or 'OFF'. If the output is "OFF" due to some kind of failure, no external output will be made.This means that the power supply unit (2L (3), (4)
And when the CPU (6) is normal, the process output power (4) is applied to the process output section (to) and the final output relay (18C) can be driven.

[Problem that the invention seeks to solve]

Since the conventional programmable controller is configured as described above, it has had problems such as when the process input section, process output section, and power supply device are located far apart, it is necessary to route the normal signals of each. Furthermore, if the power supplies are installed in separate locations, there are problems such as the inability to turn off the output in the event of an abnormality.

This invention was made to solve the above-mentioned problems, and its purpose is to provide a programmable controller configured to apply process output power only after the process output side is normally accessed by the CPU. shall be. Furthermore, it is an object of the present invention to obtain a programmable controller that can take in the applied power and send a normal process output to a CPU.

[Means for solving problems]

The programmable controller according to the present invention has a watchdog timer for each IO block.
gTimer) (hereinafter abbreviated as WDT) is provided, and when the IO is normally accessed, the WDT is operated and the process output power is applied based on this signal. It is also configured to capture the fact that the process output power is applied and send it back to the CPU.

[Effect]

The process output power according to the present invention is applied to the process output only when it is normally accessed by the CPU, and if it is not accessed for a certain period of time (in case of failure), the WDT is applied to the process output.
operates and the output is automatically turned off. Furthermore, if the applied voltage is monitored and sent back to the CPU, each IO can be monitored by the CPU.

[Embodiments of the invention]

Hereinafter, a diagram of an embodiment of the present invention will be described. 1st
In the figure, 0υ is the CPU, the foundation is the 5Vm source that supplies 5V power to the CPU, and the system normality detection relay is
Akatsuki is a relay surge killer, and my sister is 'O' when the system is normal.
The contact point ``N'' is a process input section, and the slope is a power source that supplies a 5 Vi source to the process input section (a), and (4) is a process input power supply device, which is DC48V in this embodiment.

(to) goes to the process output section, (goods) goes to the process output section 5
(3) A power supply for supplying power, (3) is a power supply for process output, which is 24V DC in this embodiment. Figure 2 is a diagram showing the details of the process output section (to), and (18a) is the CP
Interface section with Uαυ, (13b) is a memory that holds output signals, (18C) is an output relay, (18d)
l is the contact of the output relay (18c), (18e) is the surge killer (taf) of the output relay (18c) is the transistor that drives the output relay (llc), and (180) is the C
WDT, which monitors access from PU, (18
2) is a transistor (
181) is the relay amplified and driven, (184) is the surge killer of the relay (182), and (11313) is its contact point. FIG. 3 shows the process output section of FIG. 2 provided with a power supply voltage monitoring circuit (185).

Next, the operation will be explained. As shown in Figure 1, the CPU
The section αη, the process input section (2), and the process output section (to) are connected only by BLJS, so that they can be installed in far away locations. The CPU (B) detects that the 5V [source (goods) is normal and cyclically turns on the process input section (2).
) takes in the process signal, executes the calculation, and sends the process output signal to the process output section 0 to drive the process. The process output section (to) determines the command of the CPU αυ by the interface circuit (18a), stores it in the output memory (1lb), drives the output relay (18c) by the output drive transistor (18f), and turns on the output contact (18d). Alternatively, the process is controlled by turning it "OFF", but the power supply that drives this output relay (r18c) is the process output power supply (4
) is given by This power supply generates a signal confirming that it has been normally accessed by the CPU αD in an interface circuit (18a) and drives a WDT circuit (180). After the WDT (180) is normally accessed, it drives the transistor (181) for a certain period of time and then relays (1).
82) is driven, the contact (188) becomes 1ON1, and the process output power source (3) is applied to the process output. If the CPU or process output section becomes abnormal and the WDT (180) is not accessed for more than a certain period of time, the WDT times out and the transistor (181)
OFF”, the contact (1fl13) becomes OFF, and the output contact (1&I) automatically turns OFF.
This makes it possible to prevent the process from running out of control.

Fig. 8 is a further improvement of Fig. 2, in which a voltage monitoring circuit (185
) is configured to be able to detect the signal and send the signal back to the CPU (b), which allows the CPU (b) to monitor the state of the process output section. Furthermore, the relay in Figure 1 is activated when the CPU 01) operates normally and the process input section @ and process output section (to) operate normally, and the contact - is turned 'ON', confirming the normality of the system from the outside. It is configured so that it can be done.

In the above embodiment, there is one process input section and one process output section, but any number may be used, and there may be any number of output circuits of the process output section. Further, (llc) is an output relay, but of course it may be a semiconductor such as a transistor or a photocoupler, and the relay (182) may also be a semiconductor.

Furthermore, although no mention was made of the BUS that connects the CPU, the process input section, and the process output section, the BUS may or may not be insulated, and may be a parallel BUS or a serial path.

〔Effect of the invention〕

As described above, according to the present invention, the process input section and the process output section of the programmable controller are provided with power, and the power is supplied through the contacts that operate when the process output section is normally accessed. It has become possible to install the input section and the process output section at a location away from the CPU.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing the internal circuit configuration of the process output section in FIG. Block diagram showing an example when adding
This figure is a block diagram showing the configuration of a conventional programmable controller, and FIG. 5 is a block diagram showing the internal circuit of the process output section in FIG. 4. In the figure, (3) is a 24V power supply for process output, (
4) is a 28Vlt source for process input, aυ is the CPU,
Qa is the process input part, 0 is the process output part, (Foundation) is the 5V logic power supply for the CPU, (A) is the 5V logic power supply for the process input, Rut is the 5V logic J source for the process output, (18a) is the CPU θυ and interface section, (18b) is a memory that holds output signals, (180)
is a watchdog timer (WDT). Figure 3 J Figure 4 Chiku5

Claims (2)

[Claims] (1) In a programmable controller composed of a CPU and an IO device, in which the IO device is cyclically accessed, a watchdog timer is provided for each block of the IO device, and when the IO device is accessed normally, the The watchdog timer is activated and the output power is applied to the process output using this signal, and the above IO
A programmable controller characterized in that when the device is no longer accessed normally, the watchdog timer times out and automatically turns off the output. (2) The programmable device according to claim 1, wherein the final check of the IO device can be monitored by the CPU by capturing the fact that the output power is applied and sending the status back to the CPU. controller.