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JPS62104342A - Monitor device for operation margin extent of digital repeater - Google Patents

Monitor device for operation margin extent of digital repeater

Info

Publication number
JPS62104342A
JPS62104342A JP24538285A JP24538285A JPS62104342A JP S62104342 A JPS62104342 A JP S62104342A JP 24538285 A JP24538285 A JP 24538285A JP 24538285 A JP24538285 A JP 24538285A JP S62104342 A JPS62104342 A JP S62104342A
Authority
JP
Japan
Prior art keywords
circuit
repeater
margin
extent
pcm
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24538285A
Other languages
Japanese (ja)
Other versions
JPH0683265B2 (en
Inventor
Kunitetsu Makino
牧野 州哲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60245382A priority Critical patent/JPH0683265B2/en
Publication of JPS62104342A publication Critical patent/JPS62104342A/en
Publication of JPH0683265B2 publication Critical patent/JPH0683265B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To monitor the extent of the operation margin of a digital repeater accurately from a distant place by providing an operation margin extent testing circuit to the input part of the digital repeater, controlling the operation margin extent testing circuit according to additional bits, and sending the code error rate during a test back to the distant place. CONSTITUTION:When the extent of the operation margin is measured, additional bits obtained by coding a number assigned to the PCM repeater 21, a measurement item, and measurement condition are inputted from a terminal station repeater, etc., through a PCM transmission line 20. The additional bits inputted to the PCM repeater 21 are separated by an additional bit separating circuit 26 and decoded by a control circuit 220 to discriminates the measurement item and measurement condition that the bits contain; and an attenuator inserting circuit 221 in the case of an input level margin extent or a noise generator 222 in the case of an S/N margin extent is controlled and error rate information from a code error counting circuit 28 is sent back to the terminal station repeater by a monitor information inserting circuit 34 through a transmission line 36.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は光通信方式やPCM通信方式等のディジタル通
信方式におけるディジタル中継器の動作余裕度監視装置
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an operating margin monitoring device for a digital repeater in a digital communication system such as an optical communication system or a PCM communication system.

〔従来の技術〕[Conventional technology]

従来、ディジタル中継器の動作を監視する方式としては
、光中継器で採用されるLDバイアス監視方式と、PC
M中継器で採用されるパルストリオ余裕度監視方式とが
知られている。
Conventionally, methods for monitoring the operation of digital repeaters include the LD bias monitoring method used in optical repeaters, and the PC
A pulse trio margin monitoring method employed in M repeaters is known.

第2図は、LDバイアス監視を行なう光中継器のブロッ
ク図であり、光伝送路2から光中継器1に入力した光信
号はO/E変換回路3で電気信号に変換され、再びE1
0変換回路4で光信号に変換されることにより波形整形
等の中継動作が行なわれて光伝送路5に送出される。E
10変換回路4内の半導体レーザ(LD)のバイアス値
はLDバイアス監視回路6で監視されており、LDバイ
アス監視回路6で得られた半導体レーザのバイアス値は
、監視情報挿入回路7において監視用光伝送路等の別の
光伝送路8に挿入され、監視光に返送される。なお同図
において、9は光伝送路8を介して光中継器lに入力さ
れた光信号を電気信号に変換する0/E変換回路、10
は監視情報挿入回路7でO/E変換回路9の出力にLD
バイアス監視情報が挿入された電気信号を光信号に変換
するE10変換回路である。
FIG. 2 is a block diagram of an optical repeater that monitors the LD bias. The optical signal input to the optical repeater 1 from the optical transmission line 2 is converted into an electrical signal by the O/E conversion circuit 3, and then E1
The signal is converted into an optical signal by the 0 conversion circuit 4, subjected to relay operations such as waveform shaping, and sent to the optical transmission line 5. E
The bias value of the semiconductor laser (LD) in the conversion circuit 4 is monitored by the LD bias monitoring circuit 6, and the bias value of the semiconductor laser obtained by the LD bias monitoring circuit 6 is used for monitoring in the monitoring information insertion circuit 7. It is inserted into another optical transmission line 8 such as an optical transmission line and sent back to the monitoring light. In the same figure, reference numeral 9 denotes an O/E conversion circuit that converts the optical signal input to the optical repeater l via the optical transmission line 8 into an electrical signal, and 10
The monitoring information insertion circuit 7 connects the LD to the output of the O/E conversion circuit 9.
This is an E10 conversion circuit that converts an electrical signal into which bias monitoring information is inserted into an optical signal.

また第3図は、パルストリオ余裕度の監視を行なうPC
M中継器のブロック図であり、PCM伝送路11からP
CM中継器12に入力したバイポーラなPCM信号はB
/U変換回路13でユニポーラなPCM信号に変換され
、同調回路17で生成された再生クロ7りに基づいて等
他罪14で等化された後、U/B変換回路15でバイポ
ーラなPCM信号に変換されてPCM伝送路16に送出
される。PCM中継器12のパルストリオ余裕度の監視
は、PCM伝送路11を介してPCM中継器12にパル
ストリオ監視用の信号を入力し、U/B変換回路15の
出力からそのパルストリオ監視用信号に応じた信号成分
のみを帯域ろ波器18で抽出して監視伝送路19により
監視元に返送し、返送された信号に基づき監視元でパル
ストリオ余裕度の測定が行なわれる。
Figure 3 also shows the PC that monitors the pulse trio margin.
It is a block diagram of M repeater, and it is a block diagram of PCM transmission line 11 to P
The bipolar PCM signal input to the CM repeater 12 is B
The /U conversion circuit 13 converts the signal into a unipolar PCM signal, and the tuning circuit 17 equalizes the signal based on the reproduction signal 14, and then the U/B conversion circuit 15 converts the bipolar PCM signal into a unipolar PCM signal. and is sent to the PCM transmission line 16. To monitor the pulse trio margin of the PCM repeater 12, a pulse trio monitoring signal is input to the PCM repeater 12 via the PCM transmission line 11, and the pulse trio monitoring signal is input from the output of the U/B conversion circuit 15. Only the signal component corresponding to the signal is extracted by the bandpass filter 18 and sent back to the monitoring source via the monitoring transmission line 19, and the pulse trio margin is measured at the monitoring source based on the returned signal.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

このように、従来のディジタル中継器においても何等か
の監視手段は備えられているが、ディジタル中継器の誤
り率を正確に監視するまでには到っていない、即ち、上
述した従来の光中継器1における監視方式では、中継器
の全回路のうちのE10変換回路4の余裕度のみしか監
視できず、半導体レーザの劣化等は監視し得るが、全体
的な誤り率は監視できず、また第3図の従来のPCM中
継器12のパルストリオ監視方式でも、監視結果と中継
器の誤り率等との相関関係を正確に把握することが困難
である。
In this way, conventional digital repeaters are also equipped with some kind of monitoring means, but the error rate of digital repeaters has not yet been accurately monitored. The monitoring method in device 1 can only monitor the margin of the E10 conversion circuit 4 among all the circuits in the repeater, and although it can monitor the deterioration of the semiconductor laser, it cannot monitor the overall error rate. Even with the conventional pulse trio monitoring method of the PCM repeater 12 shown in FIG. 3, it is difficult to accurately grasp the correlation between the monitoring results and the error rate of the repeater.

本発明はこのような事情に鑑みて為されたもので、その
目的は、ディジタル中継器の動作余裕度を誤り車止して
正確に測定し得る動作余裕度監視装置を提供することに
ある。
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an operating margin monitoring device that can accurately measure the operating margin of a digital repeater by preventing the vehicle from erroneously stopping the vehicle.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は上記目的を達成するために、自ディジタル中継
器に伝送路を介して入力された信号中から付加ビットを
分離する付加ビット分離回路と、自ディジタル中継器の
入力部に設けられ、前記付加ビット分離回路で分離され
た付加ビットの内容に応じて動作余裕度の試験を行なう
動作余裕度試験回路と、 この動作余裕度試験回路の試験中における前記伝送路を
介して入力される信号の符号誤り率を検出する符号誤り
率検出回路と、 この符号誤り率検出回路で検出された符号誤り率を伝送
路に送出して返送する監視情報挿入回路とを設ける。
In order to achieve the above object, the present invention includes an additional bit separation circuit that separates additional bits from a signal input to the own digital repeater via a transmission path, and an additional bit separation circuit that is provided at the input section of the own digital repeater; An operation margin test circuit that tests the operation margin according to the contents of the additional bits separated by the additional bit separation circuit, and a signal input through the transmission line during the test of this operation margin test circuit. A code error rate detection circuit for detecting a code error rate and a monitoring information insertion circuit for sending the code error rate detected by the code error rate detection circuit to a transmission path and returning it are provided.

〔作用〕[Effect]

監視元例えば端局中継器より被測定中継器番号。 Monitoring source, for example, the number of the repeater being measured from the end station repeater.

測定項目等の情報を含む付加ビットが伝送路を経由して
被測定中継器に入力されると、この付加ビットは付加ビ
ット分離回路で分離され、動作余裕度試験回路は指定さ
れた動作余裕度の試験を行なうための各種の動作、例え
ば人力レベル余裕度試験のためのアッテネータの挿入、
S/N余裕度試験のための雑音の挿入、ジッタ余裕度試
験のための等化器用同調回路の中心周波数の変動操作等
を行なう、このような動作が行なわれている最中に、伝
送路を介して中継器にディジタル信号が入力されると、
符号誤り率検出回路で符号の誤り率が検出され、その符
号誤り率が監視情報挿入回路により伝送路に挿入されて
端局中継器等の監視元に返送される。
When the additional bits containing information such as measurement items are input to the repeater under test via the transmission line, the additional bits are separated by the additional bit separation circuit, and the operating margin test circuit performs the operation margin test circuit according to the specified operating margin. Various operations for conducting tests, such as inserting attenuators for human power level margin tests,
During operations such as inserting noise for S/N margin testing and varying the center frequency of the equalizer tuning circuit for jitter margin testing, the transmission line When a digital signal is input to the repeater via
The code error rate is detected by the code error rate detection circuit, and the code error rate is inserted into the transmission path by the monitoring information insertion circuit and sent back to the monitoring source such as the terminal repeater.

〔実施例〕〔Example〕

第1図は本発明の実施例のブロック図であり、本発明を
PCM中継器に適用した例を示す。
FIG. 1 is a block diagram of an embodiment of the present invention, showing an example in which the present invention is applied to a PCM repeater.

同図において、PCM伝送路20を介してPCM中継器
21に入力されたバイポーラなPCM信号は、動作余裕
度試験回路22を経由してB/U変換回路23に加えら
れ、ここでユニポーラなPCM信号に変換される。B/
U変換回路23の出力は、等他罪24に入力され、ここ
で同調回路25で生成された再生クロックにより等化処
理された信号が付加ビット分離回路26に入力される。
In the figure, a bipolar PCM signal input to a PCM repeater 21 via a PCM transmission line 20 is applied to a B/U conversion circuit 23 via an operating margin test circuit 22, where a unipolar PCM converted into a signal. B/
The output of the U conversion circuit 23 is input to an equalizer 24, where a signal equalized by a reproduced clock generated by a tuning circuit 25 is input to an additional bit separation circuit 26.

付加ビット分離回路26は、入力された信号を別の中継
器に中継する為にそのまま後段の符号誤り検出回路27
に送出すると共に、人力信号中に付加ビットが含まれて
いればこれを抽出して動作余裕度試験回路22の制御回
路220へ入力する。
The additional bit separation circuit 26 is directly connected to the code error detection circuit 27 at the subsequent stage in order to relay the input signal to another repeater.
At the same time, if an additional bit is included in the human input signal, it is extracted and input to the control circuit 220 of the operating margin test circuit 22.

符号誤り検出回路27は信号中の符号誤りを検出するも
ので、符号誤りを検出すると符号誤り計数回路28をカ
ウントアツプする。また、例えば所定文字数だけの符号
誤り処理を行なうと符号誤り計数回路28をリセットす
る。
The code error detection circuit 27 detects code errors in the signal, and when a code error is detected, the code error counting circuit 28 is counted up. Further, for example, when code error processing is performed for a predetermined number of characters, the code error counting circuit 28 is reset.

符号誤り検出回路27の出力は、U/B変換回路29に
入力され、ここで再びバイポーラなPCM信号に変換さ
れてPCM伝送路30に送出される。
The output of the code error detection circuit 27 is input to the U/B conversion circuit 29, where it is again converted into a bipolar PCM signal and sent to the PCM transmission line 30.

また、監視用伝送路や下り伝送路等の別のPCM伝送路
31からPCM中継器21に入力されたバイポーラなP
CM信号は、B/U変換回路32でユニポーラなPCM
信号に変換され、等他罪33で等化されたのち監視情報
挿入回路34に入力される。監視情報挿入回路34は、
等他罪33からの信号に符号誤り計数回路28の出力で
ある誤り率情報を挿入し、これをU/B変換回路35に
送り、ここでバイポーラなPCM信号に変換されたPC
M信号がPCM伝送路36に送出される。
In addition, the bipolar P that is input to the PCM repeater 21 from another PCM transmission line 31 such as a monitoring transmission line or a downlink transmission line is also used.
The CM signal is converted to unipolar PCM by the B/U conversion circuit 32.
After being converted into a signal and equalized by an equalizer 33, it is input to a monitoring information insertion circuit 34. The monitoring information insertion circuit 34 is
The error rate information that is the output of the code error counting circuit 28 is inserted into the signal from the 33, and sent to the U/B conversion circuit 35, where it is converted into a bipolar PCM signal.
The M signal is sent to the PCM transmission line 36.

上記動作余裕度試験回路22は、本実施例の場合、PC
M伝送路20とB/U変換回路23間に接続されたアッ
テネータ挿入回路221 と、雑音発生器222と、雑
音発生器222で発生した雑音信号を中継器入力に重畳
する加算器223と、付加ビット分離回路26で分離さ
れた付加ビットをデコードし、自中継器の番号が含まれ
ている場合には指定された試験項目を指定された測定条
件の下で試験するためにアンテネータ挿入回路221.
雑音発生器222を制御し、また同調回路25の中心周
波数を変化させる信号を発する制御回路220とから構
成されている。
In this embodiment, the operating margin test circuit 22 is a PC
An attenuator insertion circuit 221 connected between the M transmission line 20 and the B/U conversion circuit 23, a noise generator 222, and an adder 223 that superimposes the noise signal generated by the noise generator 222 on the repeater input; The additional bit separated by the bit separation circuit 26 is decoded, and if the number of the own repeater is included, the antenna insertion circuit 221 is used to test the specified test item under the specified measurement conditions.
It is comprised of a control circuit 220 that controls a noise generator 222 and generates a signal that changes the center frequency of the tuning circuit 25.

本実施例では、PCM中継器21の入力レベル余裕度と
S/N余裕度とジッタ余裕度の測定が可能であり、各余
裕度の測定を行なう場合、当該PCM中継器21に割当
てられた中継器番号と、測定項目と、測定条件をコード
化した付加ビットをPCM伝送路20を経由して端局中
継器等から入力する。
In this embodiment, it is possible to measure the input level margin, S/N margin, and jitter margin of the PCM repeater 21, and when measuring each margin, the relay assigned to the PCM repeater 21 Additional bits encoding the instrument number, measurement items, and measurement conditions are input from a terminal repeater or the like via the PCM transmission line 20.

PCM中継器21に入力された付加ビットは、付加ビッ
ト分離回路26で分離されて制御回路220に入力され
、制御回路220は付加ビットをデコードすることによ
り自中継器の番号が含まれているか否か、および含まれ
ていればその測定項目、測定条件を識別し、その内容に
応じて次のような制御を行なう。
The additional bits input to the PCM repeater 21 are separated by an additional bit separation circuit 26 and input to the control circuit 220, and the control circuit 220 decodes the additional bits to determine whether or not it contains the number of its own repeater. If included, the measurement item and measurement conditions are identified, and the following control is performed depending on the content.

・測定項目−人力レベル余裕度 この場合、アッテネータ挿入回路221内のアッテネー
タをPCM伝送路20とB/U変換回路23の間に挿入
し、且つそのアッテネータ値を測定条件で指定された値
に変化させる。
・Measurement item - Human power level margin In this case, the attenuator in the attenuator insertion circuit 221 is inserted between the PCM transmission line 20 and the B/U conversion circuit 23, and the attenuator value is changed to the value specified by the measurement conditions. let

このように所定のアッテネータ値が入力部に入力された
状態で伝送路20を介してPCM信号が入力されると、
符号誤り検出回路27で符号誤りが検出され、符号誤り
計数回路28からそのアッテネータ値に応じた誤り率情
報が出力され、監視情報挿入回路34にて伝送路31か
らの信号に挿入され、伝送路36を経由して端局中継器
に返送される。従って、端局中継器でその誤り率情報と
指定したアッテネータ値とから当該PcM中継器21の
入力レベル余裕度を監視することができる。
When a PCM signal is input via the transmission line 20 with a predetermined attenuator value input to the input section in this way,
A code error is detected by the code error detection circuit 27, and error rate information corresponding to the attenuator value is output from the code error counting circuit 28. The error rate information is inserted into the signal from the transmission line 31 by the monitoring information insertion circuit 34, and is inserted into the signal from the transmission line 31. The signal is sent back to the end station repeater via 36. Therefore, the input level margin of the PcM repeater 21 can be monitored from the error rate information and the designated attenuator value at the terminal repeater.

・測定項目=S/N余裕度 この場合、雑音発生器222から測定条件で指定された
レベルの雑音信号を発生させ、加算器223で中継器入
力に加算させる。後の動作は入力レベル余裕度試験と同
じであり、その雑音レベルに応じた誤り率情報が伝送路
36を経由して端局中継器に返送され、端局中継器側で
返送された誤り率情報と指定した雑音レベルとからS/
N余裕度を監視する。
- Measurement item = S/N margin In this case, the noise generator 222 generates a noise signal of a level specified by the measurement conditions, and the adder 223 adds it to the repeater input. The subsequent operation is the same as the input level margin test, and error rate information corresponding to the noise level is sent back to the end station repeater via the transmission line 36, and the error rate returned at the end office repeater side is From the information and the specified noise level, S/
Monitor the N margin.

・測定項目=ジッタ余裕度 この場合、同調回路25の中心周波数を測定条件で指定
された量だけ変化させる信号を同調回路25に加える。
-Measurement item = jitter margin In this case, a signal is applied to the tuning circuit 25 that changes the center frequency of the tuning circuit 25 by an amount specified by the measurement conditions.

これにより、同調回路25で生成される再生クロックが
正規の位置より変動するので、そのときの誤り率を見る
ことでジッタ余裕度の監視が可能となる。
As a result, the reproduced clock generated by the tuning circuit 25 fluctuates from its normal position, so it becomes possible to monitor the jitter margin by looking at the error rate at that time.

なお、制御回路220は、余裕度の測定が指示されてい
ないときは、アッテネータ221の挿入、雑音信号の重
畳、同調回路25の中心周波数の変動は何れも行なわな
いことは勿論のことである。
It goes without saying that the control circuit 220 does not insert the attenuator 221, superimpose the noise signal, or vary the center frequency of the tuning circuit 25 when the margin measurement is not instructed.

以上の実施例では、測定項目として人力レベル余裕度、
S/N余裕度、シフタ余裕度の3種類としたが、本発明
はそのうちの1種類或いは2種類の測定を行なうように
変更しても良く、他の種類の余裕度を測定するように構
成しても良い。また、PCM中継器について適用した実
施例のみ示したが、光中継器へも同様に適用することが
可能である。
In the above embodiment, the measurement items include the manpower level margin,
Although there are three types of measurement, S/N margin and shifter margin, the present invention may be modified to measure one or two of them, and may be configured to measure other types of margin. You may do so. Further, although only an example applied to a PCM repeater has been shown, the present invention can be similarly applied to an optical repeater.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、ディジタル中継
器の入力部に入力レベル余裕度、  S/N余裕度、ジ
ッタ余裕度等の1種類或いは複数種類の余裕度の試験を
行なう動作余裕度試験回路を設け、遠隔地より伝送路を
芥して送出した付加ビットにより動作余裕度試験回路を
制御し、試験中の符号誤り率を中継器内で求めて遠隔地
に返送するように構成したので、中継器の動作余裕度を
誤り率として正確に遠隔地から監視でき、ディジタル伝
送路の保守の信鯨性を向上させることができる効果があ
る。
As explained above, according to the present invention, there is an operational margin for testing one or more types of margins such as input level margin, S/N margin, jitter margin, etc. at the input section of a digital repeater. A test circuit was installed, and the operating margin test circuit was controlled by additional bits sent from a remote location through the transmission line, and the code error rate during the test was determined within the repeater and sent back to the remote location. Therefore, the operating margin of the repeater can be accurately monitored from a remote location as an error rate, and the reliability of maintenance of the digital transmission line can be improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例のブロック図、第2図および第
3図は従来例のブロック図である。 図において、21はPCM中継器、20.30.31゜
36はPCM伝送路、22は動作余裕度試験回路、26
は付加ビット分離回路、27は符号誤り検出回路、28
は符号誤り計数回路、34は監視情報挿入回路である。
FIG. 1 is a block diagram of an embodiment of the present invention, and FIGS. 2 and 3 are block diagrams of a conventional example. In the figure, 21 is a PCM repeater, 20.30.31.36 is a PCM transmission line, 22 is an operating margin test circuit, and 26
27 is an additional bit separation circuit, 27 is a code error detection circuit, and 28 is an additional bit separation circuit.
34 is a code error counting circuit, and 34 is a monitoring information insertion circuit.

Claims (1)

【特許請求の範囲】 自ディジタル中継器に伝送路を介して入力された信号中
から付加ビットを分離する付加ビット分離回路と、 自ディジタル中継器の入力部に設けられ、前記付加ビッ
ト分離回路で分離された付加ビットの内容に応じて動作
余裕度の試験を行なう動作余裕度試験回路と、 該動作余裕度試験回路の試験中における前記伝送路を介
して入力される信号の符号誤り率を検出する符号誤り率
検出回路と、 該符号誤り率検出回路で検出された符号誤り率を伝送路
に送出して返送する監視情報挿入回路とを具備したこと
を特徴とするディジタル中継器の動作余裕度監視装置。
[Scope of Claims] An additional bit separation circuit that separates additional bits from a signal input to the own digital repeater via a transmission line; An operation margin test circuit that tests the operation margin according to the content of the separated additional bits, and detects the bit error rate of the signal input through the transmission line during the test of the operation margin test circuit. An operating margin of a digital repeater characterized by comprising a code error rate detection circuit that detects the code error rate, and a monitoring information insertion circuit that sends the code error rate detected by the code error rate detection circuit to a transmission path and returns it. Monitoring equipment.
JP60245382A 1985-10-31 1985-10-31 Operational margin monitoring device for digital repeater Expired - Lifetime JPH0683265B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60245382A JPH0683265B2 (en) 1985-10-31 1985-10-31 Operational margin monitoring device for digital repeater

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60245382A JPH0683265B2 (en) 1985-10-31 1985-10-31 Operational margin monitoring device for digital repeater

Publications (2)

Publication Number Publication Date
JPS62104342A true JPS62104342A (en) 1987-05-14
JPH0683265B2 JPH0683265B2 (en) 1994-10-19

Family

ID=17132826

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60245382A Expired - Lifetime JPH0683265B2 (en) 1985-10-31 1985-10-31 Operational margin monitoring device for digital repeater

Country Status (1)

Country Link
JP (1) JPH0683265B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003007578A1 (en) * 2001-07-13 2003-01-23 Anritsu Corporation Jitter resistance measuring instrument and method for enabling efficient measurement of jitter resistance characteristic and adequate evaluation

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5341487A (en) * 1976-09-27 1978-04-14 Nippon Paint Co Ltd Immobilized enzyme and its preparation

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5341487A (en) * 1976-09-27 1978-04-14 Nippon Paint Co Ltd Immobilized enzyme and its preparation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003007578A1 (en) * 2001-07-13 2003-01-23 Anritsu Corporation Jitter resistance measuring instrument and method for enabling efficient measurement of jitter resistance characteristic and adequate evaluation
US7245657B2 (en) 2001-07-13 2007-07-17 Anritsu Coporation Jitter resistance measuring instrument and method for enabling efficient measurement of jitter resistance characteristic and adequate evaluation

Also Published As

Publication number Publication date
JPH0683265B2 (en) 1994-10-19

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