JPS62104065A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPS62104065A JPS62104065A JP60244972A JP24497285A JPS62104065A JP S62104065 A JPS62104065 A JP S62104065A JP 60244972 A JP60244972 A JP 60244972A JP 24497285 A JP24497285 A JP 24497285A JP S62104065 A JPS62104065 A JP S62104065A
- Authority
- JP
- Japan
- Prior art keywords
- resistors
- terminals
- resistor
- solder
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
- H05K1/092—Dispersed materials, e.g. conductive pastes or inks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Non-Adjustable Resistors (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は抵抗体を形成している混成集積回路に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit forming a resistor.
一般に、混成集積回路はセラミック等の絶縁基板上に導
体あるいは抵抗体を印刷あるいは蒸着法によって形成し
、トランジスタ、ダイオードなどの半導体チップあるい
はコンデンサチップを半田付けまたはグイボンディング
などの方法で取り付けて回路を構成している。In general, hybrid integrated circuits are constructed by forming conductors or resistors on an insulating substrate such as ceramic by printing or vapor deposition, and attaching semiconductor chips such as transistors and diodes or capacitor chips by methods such as soldering or hard bonding. It consists of
前記絶縁基板上の導体間に形成される抵抗体の由に加減
することができるため、通常抵抗インクとして例えば百
Ω/ロ、IKΩ/口、■0にΩ/口。Since the resistance can be adjusted depending on the resistor formed between the conductors on the insulating substrate, the resistance ink is usually 100Ω/Ω, IKΩ/Ω, and 0Ω/Ω/Ω.
50にΩ/口というように標準化されたものを使用し、
その前後の抵抗値を抵抗体の巾や長さで調整するものと
して特公昭57−41103号公報が開示されている。Using standardized values such as Ω/mouth for 50,
Japanese Patent Publication No. 57-41103 discloses a method in which the resistance values before and after the resistor are adjusted by the width and length of the resistor.
ところガ、抵抗体の抵抗値をより正確に所望の値とする
には、通常基板上に形成された抵抗体の両端にテスター
の測定端子を直接接続し、抵抗体にレーザー光を照射し
て抵抗体に傷をつけ抵抗値を変化させるトリミングが行
われている。However, in order to more accurately measure the resistance value of a resistor to the desired value, the measurement terminals of a tester are usually connected directly to both ends of the resistor formed on the board, and the resistor is irradiated with laser light. Trimming is performed to change the resistance value by scratching the resistor.
このようなトリミングは直列接続されている抵抗体には
有効であるが、互いに並列接続されている抵抗体や、第
4図に示すように閉回路を構成している抵抗体R1の抵
抗値を検出する場合、抵抗体R1の両端にテスターの測
定端子を接続しても検出される抵抗値は抵抗体R2とR
3とを含めた合成抵抗値となってしまい、抵抗体R1の
正確な抵抗値を検出できない。このため、第5図に示す
ように、閉回路を構成しないよう、抵抗体R2とR3と
の接続点となる端子Tを分割して隙間Sを入れ抵抗体R
2とR3を分断するようにしている。This kind of trimming is effective for resistors connected in series, but the resistance value of resistors connected in parallel or resistor R1 forming a closed circuit as shown in Figure 4 may be When detecting, even if the measurement terminals of the tester are connected to both ends of the resistor R1, the detected resistance value is the same as that of the resistors R2 and R.
The resistance value becomes a composite resistance value including 3 and 3, and the accurate resistance value of the resistor R1 cannot be detected. Therefore, as shown in FIG. 5, in order to avoid forming a closed circuit, the terminal T, which is the connection point between the resistors R2 and R3, is divided and a gap S is inserted between the resistors R and R3.
2 and R3 are separated.
そして、トリミングの後、他の半導体チップたとえばコ
ンデンサチップを半田付けする際、この分割された端子
TをコンデンサチップCの端子りを介して半田Hにより
電気的に結合するようにしている。After trimming, when another semiconductor chip, such as a capacitor chip, is soldered, the divided terminals T are electrically connected by solder H via the terminals of the capacitor chip C.
しかし、溶解している半田Hには液体のように表面張力
があり、この性質によって、端子Tが大きいと半田付け
を行っても分割されている端子Tの一方にのみ半田Hが
のって端子T同士が連結されず、回路不良になる場合が
ある。この抵抗体R2とR3との接続点に他のコンデン
サチップCなどの部品が取り付けられる場合には分割さ
れた両端子TがコンデンサチップCの端子りに接触して
接続されるため、一方の端子TとコンデンサチップCと
が半田Hにより結合されても回路上支障はないが、抵抗
体以外には部品がない場合には、このように閉回路を切
断するとその再結合の際、半田Hの表面張力によって再
結合が難しく不良品が生ずる問題があった。However, melted solder H has surface tension like a liquid, and due to this property, if the terminal T is large, even if soldering is performed, the solder H will only be on one side of the divided terminal T. The terminals T may not be connected to each other, resulting in a circuit failure. When a component such as another capacitor chip C is attached to the connection point between the resistors R2 and R3, both the divided terminals T are connected to the terminals of the capacitor chip C, so one terminal There is no problem in the circuit even if T and capacitor chip C are connected by solder H, but if there are no components other than the resistor, if the closed circuit is cut in this way, the solder H will be disconnected when reconnecting. There was a problem in that recombination was difficult due to surface tension, resulting in defective products.
本発明は前記事情を考慮してなされたもので、閉回路を
構成する抵抗体をトリミングする際に分割された接続点
を容易に半田付けにより再結合できる混成集積回路を提
供することを目的とするものである。The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a hybrid integrated circuit in which connection points that are separated when trimming a resistor forming a closed circuit can be easily recombined by soldering. It is something to do.
前記目的を達成するための本発明の構成は絶縁基板上に
導体と抵抗体とを形成する混成集積回路において、複数
の抵抗体を接続する端子に各抵抗体の接続を電気的に分
断するギャップを設けると共に、前記端子の大きさに対
応した半田を前記端子に載置することにより、前記分断
された端子を結合するようにしたことを特徴とするもの
である。The structure of the present invention to achieve the above object is that in a hybrid integrated circuit in which a conductor and a resistor are formed on an insulating substrate, a gap is provided at a terminal connecting a plurality of resistors to electrically separate the connection of each resistor. The present invention is characterized in that the divided terminals are connected by providing a solder and placing solder corresponding to the size of the terminal on the terminal.
以下、図面に基づいて本発明の一実施例を詳述する。 Hereinafter, one embodiment of the present invention will be described in detail based on the drawings.
第1図及び第2図において、セララミ、り基板lに所望
のパターンを持つ導体2をスクリーン印刷形成する。こ
の際、前記第4図及び第5図で示した閉回路を構成する
各抵抗体の抵抗値調整用として端子3も同時に分割形成
される。この端子3は略中間にギャップ4を有して電気
的に分断されており、このギャップ4は前記端子3印刷
形成の際、分断された端子3間が短絡しない程度たとえ
ば0.1m〜0.2鰭に設定され、端子3はギャップ4
も含めてたとえば1.0mm”程度の大きさとなってい
る。1 and 2, a conductor 2 having a desired pattern is formed on a ceramic laminated substrate 1 by screen printing. At this time, the terminals 3 are also separately formed at the same time for adjusting the resistance values of the respective resistors constituting the closed circuit shown in FIGS. 4 and 5. The terminals 3 are electrically separated by a gap 4 approximately in the middle, and the gap 4 is set to an extent of, for example, 0.1 m to 0.0 m to prevent a short circuit between the separated terminals 3 when printing the terminals 3. Set to 2 fins, terminal 3 is set to gap 4
For example, the size including the diameter is about 1.0 mm.
次に、基板l上の所定導体2間に抵抗体5をスクリーン
印刷形成する。Next, a resistor 5 is formed by screen printing between predetermined conductors 2 on the substrate l.
次に、第3図Aで示すように、少なくとも前記端子3を
除く基板l上に基板1表面保護用のガラス6をスクリー
ン印刷形成する。Next, as shown in FIG. 3A, a glass 6 for protecting the surface of the substrate 1 is formed by screen printing on the substrate 1 excluding at least the terminals 3.
以上のように構成される本発明は抵抗体5の両端にテス
ターの測定端子を直接接続し、前記同様抵抗体5にレー
ザー光を照射してその抵抗値を調整する。この際、端子
3が分断されているので、閉回路は未だ構成されておら
ず、抵抗値を調整したい所定の抵抗体5の抵抗値を他の
抵抗体5に影響されることなく検出できるものであり、
こうして全ての抵抗体5の抵抗値を調整する。In the present invention configured as described above, the measurement terminals of a tester are directly connected to both ends of the resistor 5, and the resistance value is adjusted by irradiating the resistor 5 with a laser beam as described above. At this time, since the terminal 3 is separated, a closed circuit is not yet configured, and the resistance value of the predetermined resistor 5 whose resistance value is to be adjusted can be detected without being influenced by other resistors 5. and
In this way, the resistance values of all the resistors 5 are adjusted.
このような調整の後、端子3上に半田7を載置し、この
半田7により分断形成した端子3を電気的に結合して閉
回路を構成する。゛
)/ 1 n −ノ
この場合、端子3はギャップ4
球状に硬化して、端子3をほぼ被覆してギャップ4によ
り分断された端子3を良好に結合する。この端子3が大
きいと、半田7は表面張力の影響で一方の端子上にのみ
縮まってギャップ4を結合しない恐れがあるが、端子3
がギャップ4を含めてl1m”程度であれば最少量の半
田7によりギャップ4を結合してほぼ完全に接続不良を
防止できる。After such adjustment, solder 7 is placed on the terminals 3, and the separated terminals 3 are electrically connected by the solder 7 to form a closed circuit.゛)/1 n - In this case, the terminal 3 is hardened into a spherical shape, substantially covering the terminal 3 and bonding the terminals 3 separated by the gap 4 well. If this terminal 3 is large, the solder 7 may shrink only on one terminal due to surface tension and may not connect the gap 4.
If the distance including the gap 4 is about 11 m'', the gap 4 can be bonded with the minimum amount of solder 7, and connection failure can be almost completely prevented.
従って、この種の端子3に他のチップ部品C(第5図参
照)がなくとも抵抗体5のトリミングが可能となる。Therefore, it is possible to trim the resistor 5 even if there is no other chip component C (see FIG. 5) in this type of terminal 3.
以上、本発明の一実施例について詳述したが、本発明の
要旨の範囲内で種々変形可能である0例えば、第3図A
では端子3の形状をギャップ4を含んで略正方形とした
が、第3図Bで示すようにギャップ4を含んで略円形の
形状としても良く、半田7が表面張力の影響によりギャ
ップ4で分割された端子3を結合する形状であれば良い
。尚、第3図A、Bで示した寸法の単位は鶴である。ま
た、端子3の大きさを大きくしても、半田7の量を多く
することにより前記同様分断された端子3を結合するこ
とができる。Although one embodiment of the present invention has been described in detail above, various modifications can be made within the scope of the gist of the present invention.
In this case, the shape of the terminal 3 is approximately square including the gap 4, but it may also be approximately circular including the gap 4 as shown in FIG. Any shape is sufficient as long as it connects the terminals 3 that are connected to each other. The units of dimensions shown in FIGS. 3A and 3B are cranes. Further, even if the size of the terminal 3 is increased, the separated terminals 3 can be joined together in the same manner as described above by increasing the amount of solder 7.
以上詳述したように本発明によれば、絶縁基板上に導体
と抵抗体とを形成する混成集積回路において、複数の抵
抗体を接続する端子に各抵抗体の接続を電気的に分断す
るギャップを設けると共に、前記端子の大きさに対応し
た半田を前記端子に載置することにより、前記分断され
た端子を結合するようにしたことにより、閉回路を構成
している抵抗値をトリミングした後半田付けで複数の抵
抗体を接続している分断された端子のギャップ間を確実
に結合することができ、半田付けによる接続不良を抑制
して回路基板の歩留りを向上する混成集積回路を提供で
きる。As detailed above, according to the present invention, in a hybrid integrated circuit in which a conductor and a resistor are formed on an insulating substrate, a gap electrically separates the connection between each resistor at a terminal connecting a plurality of resistors. In addition, the separated terminals are connected by placing solder corresponding to the size of the terminal on the terminal, thereby trimming the resistance value constituting the closed circuit. It is possible to reliably connect gaps between separated terminals that connect multiple resistors by soldering, and it is possible to provide a hybrid integrated circuit that suppresses connection failures caused by soldering and improves the yield of circuit boards. .
第1図は本発明の一実施例を示す平面図、第2図は同断
面図、第3図Aは要部の拡大平面図、同図Bは他の実施
例を示す要部の拡大平面図、第4図は従来例を示す回路
図、第5図は同平面図である。
1−・−セラミック基板
2・−導体
訓−・端子
4−ギャップ
5−抵抗体
7−半田
特 許 出 願 人 日本精機株式会社代理人
弁理士 生木 護
!3図
、1゜ (A)
!4図
g5図Fig. 1 is a plan view showing one embodiment of the present invention, Fig. 2 is a sectional view thereof, Fig. 3 A is an enlarged plan view of the main part, and Fig. 3 B is an enlarged plan view of the main part showing another embodiment. 4 are circuit diagrams showing a conventional example, and FIG. 5 is a plan view thereof. 1 - Ceramic substrate 2 - Conductor pattern - Terminal 4 - Gap 5 - Resistor 7 - Solder patent Applicant: Agent for Nippon Seiki Co., Ltd.
Patent attorney Mamoru Iki! Figure 3, 1゜ (A)! Figure 4 g Figure 5
Claims (1)
において、複数の抵抗体を接続する端子に各抵抗体の接
続を電気的に分断するギャップを設けると共に、前記端
子の大きさに対応した半田を前記端子に載置することに
より、前記分断された端子を結合するようにしたことを
特徴とする混成集積回路。In a hybrid integrated circuit in which a conductor and a resistor are formed on an insulating substrate, a gap is provided at a terminal connecting a plurality of resistors to electrically separate the connection of each resistor, and a gap corresponding to the size of the terminal is provided. A hybrid integrated circuit characterized in that the separated terminals are connected by placing solder on the terminals.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60244972A JPS62104065A (en) | 1985-10-30 | 1985-10-30 | Hybrid integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60244972A JPS62104065A (en) | 1985-10-30 | 1985-10-30 | Hybrid integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62104065A true JPS62104065A (en) | 1987-05-14 |
Family
ID=17126687
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60244972A Pending JPS62104065A (en) | 1985-10-30 | 1985-10-30 | Hybrid integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62104065A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5334866A (en) * | 1992-01-06 | 1994-08-02 | Mitsubishi Denki Kabushiki Kaisha | Integrated circuit device with functions selectable by changing interconnection pattern |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5742181U (en) * | 1980-08-13 | 1982-03-08 |
-
1985
- 1985-10-30 JP JP60244972A patent/JPS62104065A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5742181U (en) * | 1980-08-13 | 1982-03-08 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5334866A (en) * | 1992-01-06 | 1994-08-02 | Mitsubishi Denki Kabushiki Kaisha | Integrated circuit device with functions selectable by changing interconnection pattern |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3741512B2 (en) | LED chip parts | |
US7089652B2 (en) | Method of manufacturing flip chip resistor | |
JPS6160593B2 (en) | ||
JP2544976B2 (en) | Semiconductor integrated circuit module | |
JP3139613B2 (en) | Surface mounted semiconductor light emitting device and method of manufacturing the same | |
JPS62104065A (en) | Hybrid integrated circuit | |
JPH04255264A (en) | Hybrid integrated circuit | |
JPH02122594A (en) | Circuit board device | |
JPS60160641A (en) | Mounting of leadless package ic for board | |
JPH03225890A (en) | Printed wiring board | |
JPH01304795A (en) | Method for wiring printed board | |
JPH0961494A (en) | Pattern for testing printed circuit board | |
JPH0724332B2 (en) | Printed circuit board | |
JPH07162123A (en) | Circuit module | |
JPS63124539A (en) | Hybrid integrated circuit | |
WO2004070837B1 (en) | Support system for an organic light-emitting diode | |
JPS61269394A (en) | How to mount circuit components | |
JPS61212088A (en) | Defective display for film circuit board | |
JPH06302933A (en) | Mounting structure for chip component | |
JPH06310820A (en) | Electronic device | |
JPH08102596A (en) | Method for mounting surface-mounting parts | |
JPH05251612A (en) | Hybrid ic | |
JPH05129767A (en) | Printed wiring board | |
JPS60180157A (en) | Manufacture of film resistor | |
JPS61236191A (en) | Substrated carrying integrated circuit |