JPS62100802A - Programmable controller - Google Patents

Abstract

PURPOSE:To take a detailed measure to meet the break of power in accordance with the control specifications at the side of each user, by executing with interruption a user program exclusive for break of power when the break of power occurs. CONSTITUTION:If an AC 100V has a break of power, the power break interruption signal is supplied to an interruption request terminal IRQ1 of a CPU 1 from a power break interruption circuit 9 in response to the power break detecting signal delivered from a power break detecting circuit 8b. Thus a normal program which is hitherto executed is interrupted and the execution permitting time for user program is set to a timer circuit 11. Then the circuit 11 is started and a power break processing program contained in the user program is executed. Then a countermeasure is carried out to the power break in accordance with the control specifications of each user. When the time set to the circuit 11 passed, an interruption is given to the CPU 1. Then the power break processing contained in a system program is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention provides a programmable system that enables the operation of a controlled object in the event of a power outage to be defined by a user program.
Regarding the controller.

(Summary of the invention) In this invention, after an interrupt request due to a power outage is issued,
Until the DC power supply goes down, a user program dedicated to power outages is configured to be executed with an interrupt, and the user can create an arbitrary sequence program as the user program dedicated to power outages. This allows the user program to specify the operation of the controlled device when it is turned off.

(Prior art and its problems) Conventionally, in this type of programmable controller, when a power outage occurs, from the time an interrupt request is issued due to the power outage until the DC power supply goes down,
By executing a system program dedicated to power outages, that is, a fixed program that cannot be arbitrarily rewritten by the user, using an interrupt, the operation of the controlled device in the event of a power outage is defined.

For this reason, there is a problem in that, depending on the user's control specifications, it is not always possible to take sufficient measures in the event of a power outage. In other words, power-off processing using a system program generally forces all output states to be turned off, but in the case of a control device for a boiler, for example, the fuel gas supply valve, exhaust gas discharge valve, etc. may be programmably turned off at the same time. If the controller's output shuts off, the timing of the joint venture's operation may be incorrect, causing the exhaust gas to flow back to the fuel gas side due to internal pressure differences within the boiler, or the fuel gas supply valve may close too late, resulting in ignition. If this is not done, there is a risk of the combustion furnace filling with gas and causing an explosion.

(Objective of the Invention) An object of the present invention is to provide a programmable controller that can take detailed countermeasures in the event of a power outage in accordance with the control specifications of each user.

- (Structure and Effects of the Invention) In order to achieve the above object, the present invention includes an interrupt request generating means that issues an interrupt request in response to a power outage, and a means for generating an interrupt request that causes the DC power to be turned off after the interrupt request is issued. The apparatus is characterized by comprising a program execution means for executing a user program exclusively for power outage by interruption until the apparatus goes down.

According to this configuration, by creating and storing a user program specifically for power outages in the user program memory in advance, it is possible to take detailed measures against power outages in accordance with each user's specifications. Become.

(Description of Embodiments) FIG. 1 is a block diagram showing the hardware configuration of a programmable controller and its peripheral devices to which the present invention is applied.

In the figure, a CPU 1 is mainly composed of a microprocessor, and executes various system programs stored in a system program memory 2.
In addition to the basic functions as a programmable controller, it is designed to realize various service functions.

Here, the basic functions as a programmable controller include an input update function that rewrites the input canister of the input/output memory 4 using input data taken in from the external input/output device 3, and an input/output function that refers to the input/output data of the input/output memory 4. It is possible to execute an instruction to execute a user instruction read from the user program memory 5 and rewrite the output data of the input/output memory 4 with the execution result. This includes an output update function that sends output data from the external input/output device 3 to the outside.

Typical system service functions 17 include a program function for writing a user program manually entered from the program console 6 into the user program memory 5, and an input/output function for a designated program portion of the user program memory 5. Examples include a monitor function that reads data from the input/output memory 4 and displays it on the display of the program console 6.

The working memory 7 is used as a storage area for intermediate calculation results when executing the various system programs described above.

Power supply unit '748 LJ, based on ACloov, DC5
It is composed of a Y65VR generation circuit 8a that forms a V, and a power failure detection circuit 8b that generates a power failure signal when a power failure occurs in AolooV.

The output voltage of the 5V generation circuit 8a is supplied to the CPU 1, the system program memory 2. External input/output device 3゜input/output memory 4. User program memory5. Power is supplied to the program console 6 and working memory 7, respectively.

So-C1 As is well known, the 5v generation circuit 8a
Even if AClooV is cut off, the output voltage of
It never drops below the allowable ifi, but after being maintained for a certain period of time by the action of the internal capacitor, it drops below the allowable ifi.

When the power failure interrupt circuit 9 receives the power failure detection signal from the power failure detection circuit 8b, it generates a power failure interrupt signal in response to the power failure detection signal, and supplies the generated power failure interrupt signal to the interrupt request terminal IRQ1 of the CPU 1.

In addition, when a power failure detection signal arrives from the power failure detection circuit 8b, the reset circuit 10 resets the D
Generate a reset signal before C5V goes down. This reset signal is supplied to the reset terminal RESET of the CPUI.

Further, the timer circuit 11 is composed of a preset counter that is automatically incremented by a built-in clock, and counts the preset data given from CPLJl, and generates a count end signal (timer interrupt signal). This count end signal is supplied to the interrupt request terminal IRQO of the CPU 1.

Next, with reference to the flowcharts shown in FIGS. 2 to 4, the memory maps shown in FIGS. 5 and 6, and the time chart shown in FIG. 7, the processing at the time of power cut-off according to the present invention will be explained.

As shown in FIG. 6, there are 20 normal programs in the user program memory in order from the start address oooo.
For example, eight words are stored corresponding to a ladder diagram, and an END instruction is stored at the final address of the normal program.

Up to this point, the same applies to conventional programmable controllers.

On the other hand, in the programmable controller of the present invention, in the area following the END command, a power outage processing program dedicated to power outages is stored in a predetermined PC language, also corresponding to a ladder diagram, etc. PEND for final address
Give the END command.

Regarding the control of writing the user program into the user program memory, a well-known method has already been established for this type of programmable controller, so it will not be explained in detail. After setting the mode corresponding to , the command keys, numeric keys, write keys, etc. are operated to sequentially input each command word, and this is written to a designated program address in the user program memory 5.

Next, when a mode setting operation corresponding to the operation mode is performed on the program console 6, the normal program from the start address of the user program memory to the END command is cyclically executed, and the input and output are updated each time, as described above. Processing takes place.

In this state, as shown in FIG.
Assuming that a power outage occurs in the C100V power supply, a power outage detection signal is output from the power outage detection circuit 8b in response to a drop in the AC waveform due to the power outage.

Then, as shown in FIG. 7, in response to the fall of the power failure detection signal, the power failure interrupt circuit 9 outputs a power failure interrupt signal.
When this signal is supplied to the interrupt request terminal -RQ1 of the CPU 1, the execution of the normal program that has been in progress is interrupted, and instead, the power cutoff process shown in FIG. 2 is started by the interrupt.

Then, by first reading the state of the power interruption interrupt signal, it is confirmed whether the interruption was actually caused by a power interruption or by noise (step 201>). If it is determined that the interrupt request is erroneous due to noise (No in step 202), the process immediately returns to the original process without performing the interrupt process.

On the other hand, if it is confirmed that the power has actually been cut off (step 202, affirmative), a power cut-off occurrence flag is set in a special flag area provided in the working memory, as shown in FIG. 5 (step 203). ). This process is necessary in order to enable optimal processing when power is restored, depending on the state of the power outage occurrence flag, when the power is restored.

Next, in step 204, the timer circuit 11 is preset to β seconds, which is the allowable execution time of the user program.
Thereafter, the timer circuit 11 is activated (step 205).

As a result, a timer interrupt is applied to the CPU 1 after β seconds have elapsed.

Thereafter, the execution of the power cut processing program in the user program shown in FIG. 3 is repeated (step 206).

In this process, first, the input data taken in from the external input/output device 3 is written to the input canister of the input/output memory 4 by the input update process (step 2061), and then the value of the program counter PC is changed to the value shown in FIG. Set it to the address next to the indicated END instruction storage address in step 20.
62>, thereafter update the program counter PC by +1 (Step 2066>, read out the instructions at the corresponding program address sequentially Step 2063),
The instructions issued one after another until the PENDEND instruction (step 2
064 (No), each read instruction is executed, and the output data of the input/output memory 4 is rewritten with the execution results (step 2065).

When the PENDEND instruction is finally decoded (step 20644), the output data in the input/output memory 4 that has been rewritten by the output update process is sent out from the external input/output device 3 (step 2067).
).

The above process is repeated until the above-mentioned timer interrupt occurs.

Therefore, if you set the power outage processing program in advance so that each output state turns off with a certain time difference from each other, when a power outage occurs, all outputs will be forcibly turned off at the same time like in conventional devices. In addition to being able to turn off the power in a certain order to meet the user's specifications without having to turn it off, various known commands can be used to take various measures against power outages. It is.

Next, when β seconds have elapsed and a timer interrupt occurs, the execution of the power cut processing program in the user program is interrupted, and instead, the timer interrupt processing shown in FIG. 4 is started.

Then, first read the state of the timer interrupt signal and confirm that it is not an erroneous interrupt due to noise (step 4).
01,402N constant), the latch circuit that constitutes the external input/output device 3 is forcibly cleared, and all output states are set to the OFF state (step 403), after which an idle link operation that does not affect input/output is performed. and enters a self-loop state (step 404).

Then, when γ seconds have elapsed and a reset signal arrives,
The microprocessor constituting the CPU 1 is forcibly reset by hardware, and the operation of the CPU 1 is stopped.

In this way, as is clear from the time chart in Figure 7, in the case of conventional power failure processing, the system program In contrast, in this embodiment, the first α seconds of the above y seconds are performed by the user leading to steps 201 to 205. The next β seconds are used for power cut processing in the system program to prepare for program execution, the next β seconds are used for power cut processing in the user program shown in step 206, and the remaining γ seconds are used for power cut processing in the system program to prepare for system down. This is done to deal with the power outage.

As a result, following the END command, an optimal power outage processing program that conforms to each user's specifications is stored in the user program memory in advance, and the PENDEND command is stored at the final address.
If a command is given, even if a power outage occurs, the output state can be turned off according to a preset procedure without automatically turning off the output state, or a signal specific to a power outage can be sent to the outside. It is possible to take various measures in the event of a power outage, such as switching from normal power supply to emergency power supply by issuing a power supply, or transferring part of the data in I10 memory to external non-volatile memory. I will be there.

In the above embodiment, the END command and the PENDEND command are used to store a user program dedicated to power outages in the user program memory and execute it only at power outages.
Although the configuration was configured to specify the instruction power outage processing program, instead of this, an address space dedicated to the power outage processing program is prepared in advance, and the value of the program counter is forcibly set to the start address of the corresponding address space at the start of the power outage processing. Of course, you can also skip to

In addition, in the above embodiment, input update and output update are performed using EN
Although the description has been made using a so-called END refresh type controller that performs each execution of the D instruction, it is of course applicable to a so-called refresh type controller that updates input and output each time an instruction is executed. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the hardware configuration of the entire programmable controller and peripheral devices to which the present invention is applied, FIG. 2 is a flowchart showing details of power interruption processing executed in response to a power interruption The figure is a flowchart showing the details of the execution of the power cut processing program in the user program, Figure 4 is the flowchart showing the details of the timer interrupt processing executed by the timer interrupt, and Figure 5 is the flowchart showing the details of the timer interrupt processing executed by the timer interrupt. Memory map showing power outage flag,
FIG. 6 is a memory map showing the states of the normal program and the power-off processing program stored in the user program memory, and FIG. 7 is a time chart showing the signal states of each part. 1... CPU 2... System program memory 3... External input/output device 4... Input/output memory 5... User program memory 6... Program console 7... Working memory 8... Power supply Device 8a...5V generation circuit 8b...Power failure detection circuit 9...Power failure interrupt circuit 10...Reset circuit 11...Timer circuit Figure 3 Figure 5

Claims (1)

[Claims] (1) An interrupt request generating means that issues an interrupt request in response to a power outage, and a means for interrupting a user program dedicated to power outages from when the interrupt request is issued until the DC power supply goes down. A programmable controller comprising: program execution means for executing a program.