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JPS6199362A - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS6199362A
JPS6199362A JP59221525A JP22152584A JPS6199362A JP S6199362 A JPS6199362 A JP S6199362A JP 59221525 A JP59221525 A JP 59221525A JP 22152584 A JP22152584 A JP 22152584A JP S6199362 A JPS6199362 A JP S6199362A
Authority
JP
Japan
Prior art keywords
chip
chips
package
pads
semiconductor equipment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59221525A
Other languages
Japanese (ja)
Inventor
Shinji Emori
江森　伸二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59221525A priority Critical patent/JPS6199362A/en
Publication of JPS6199362A publication Critical patent/JPS6199362A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F55/00—Radiation-sensitive semiconductor devices covered by groups H10F10/00, H10F19/00 or H10F30/00 being structurally associated with electric light sources and electrically or optically coupled thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は複数個の半導体チップを結合してなる半導体装
置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device formed by combining a plurality of semiconductor chips.

大規模集積回路（ＬＳＩ）の高機能化、高集積化により
、近年各種機能の回路を同−ＬＳＩ内に構成する場合が
多くなってきた。例えばＣＭＯＳとＴＴＬ、またはアナ
ログと０ＭＯ３のディジタル、さらにインクフェイス回
路を設けて０ＭＯ３とＥＣＬ等の構成を有するＬＳＩの
要求に対し、同一チップ内に構成することは困難である
。無理をして強行しても製造工程上、またその歩留りの
上からも極めて不利である。2. Description of the Related Art In recent years, as large-scale integrated circuits (LSIs) have become more sophisticated and highly integrated, circuits for various functions have increasingly been configured within the same LSI. For example, it is difficult to configure LSIs in the same chip to meet the requirements for LSIs having configurations such as CMOS and TTL, analog and 0MO3 digital, and 0MO3 and ECL with an ink face circuit. Even if it is forced, it will be extremely disadvantageous in terms of manufacturing process and yield.

従って回路機能別に独立のチップを用いれば、それぞれ
に最適なプロセスが適用でき、各機能毎の特徴が生かせ
ることになり、そのため複数個のチップを結合してなる
ＬＳＩが検討されるようになった。Therefore, if independent chips were used for each circuit function, the optimal process could be applied to each, and the characteristics of each function could be utilized. Therefore, LSIs made by combining multiple chips began to be considered. .

この場合ＬＳＩは、有効なチップ間結合手段が必要にな
る。In this case, the LSI requires effective inter-chip coupling means.

〔従来の技術〕[Conventional technology]

第２図は従来例による２個のチップよりなるＬＳＩの断
面図である。FIG. 2 is a sectional view of a conventional LSI consisting of two chips.

図において、パッケージ８の上に第１のチップ１を搭載
し、その上に第２のチップ４をフェイスアップに載せ、
パッド（ボンディングするための接続端子）３，５をワ
イヤ６でボンディングして両チップを結線する。つぎに
第１のチップ１の周辺のバッド２と、パフケージ８にメ
タライズして形成された内部リード９とをワイヤ７でボ
ンディングする。内部リード９はパッケージの外部り−
ド１０に接続されている。１１はパッケージの蓋を示す
。In the figure, the first chip 1 is mounted on the package 8, and the second chip 4 is mounted face-up on top of it.
Pads (connection terminals for bonding) 3 and 5 are bonded with wires 6 to connect both chips. Next, the pads 2 around the first chip 1 and the internal leads 9 formed by metallizing the puff cage 8 are bonded using the wires 7. Internal lead 9 is external to the package.
connected to the card 10. 11 indicates the lid of the package.

この例では両チップの結線をパッド間のワイヤボンディ
ングで行ったが、第１のチップ１の上に第２のチップ４
をフェイスダウンに載せ、バンプ（隆起した接続端子）
、ビームリードを用いて行う場合もある。In this example, the two chips are connected by wire bonding between the pads, but the second chip 4 is placed on top of the first chip 1.
Place it face down and connect the bumps (raised connection terminals).
, sometimes using a beam lead.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来例によるチップ間の結合は、パッドまたはバンプ等
を結線して行うため大きな面積を必要とした。The conventional coupling between chips requires a large area because it is performed by connecting pads or bumps.

チップ間は電気的に接続されるため、各チップの電位を
自由に設定できない。インタフェイスは例えば信号を送
る方のチップのレベルがＴＴＬの場合は、受ける方のチ
ップのレベルもＴＴＬでなければならない。Since the chips are electrically connected, the potential of each chip cannot be set freely. For example, if the level of the chip sending the signal is TTL, the level of the chip receiving the signal must also be TTL.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点の解決は、複数個の半導体チップを噴 その表面が対向するよう積み重ね、チップ間の信号伝送
を該表面間での光信号で行う手段を有する本発明による
半導体装置により達成される。The above-mentioned problems can be solved by a semiconductor device according to the present invention, which has means for stacking a plurality of semiconductor chips so that their surfaces face each other and transmitting signals between the chips using optical signals between the surfaces.

〔作用〕[Effect]

各チップに設ける発、受光素子の面積はパッドやバンプ
より小さい面積で形成でき、高集積化が可能となる。The area of the light emitting and light receiving elements provided on each chip can be smaller than that of pads and bumps, making it possible to achieve high integration.

またチップ間の信号伝送を光信号で行うため、チップ間
は電位的に分離され、設計の自由度が増す。Furthermore, since signals are transmitted between chips using optical signals, the chips are separated electrically, increasing the degree of freedom in design.

〔実施例〕〔Example〕

第１図（ａ）、　（ｂｌはそれぞれ本発明による２個の
チップよりなるＬＳＩの断面図、光伝送部を拡大した断
面図である。FIGS. 1A and 1B are a cross-sectional view of an LSI consisting of two chips according to the present invention, and an enlarged cross-sectional view of an optical transmission section, respectively.

図において、パフケー、ジ８の上に第１のチップ１を搭
載し、その上に第２のチップ４をフェイスダウンに載せ
１．バンプ３，５を溶着して両チップの電源等電流の流
れる所を結線する。つぎに第１のチップｌの周辺のパッ
ド２と、パッケージ８にメタライズして形成された内部
リード９とをワイヤ７でボンディングする。内部リード
９はパッケージの外部リード１０に接続されている。１
１はパッケージの苦を示す。In the figure, the first chip 1 is mounted on a puffer jacket 8, and the second chip 4 is placed face down on top of it.1. Bumps 3 and 5 are welded to connect the parts of both chips where current flows, such as the power source. Next, the pads 2 around the first chip 1 and the internal leads 9 formed by metallizing the package 8 are bonded using the wires 7. Internal leads 9 are connected to external leads 10 of the package. 1
1 indicates the severity of the package.

ここでチップ間の信号の伝達、交換は発光素子１２と受
光素子１３により光で行う。第１図（ｂｌに示されるよ
うに発光素子１２としてエミッターベース間のブレーク
ダウン発光を用いたトランジスタを、受光素子１３とし
てベース開放のフォトトランジスタを用いる。Here, the transmission and exchange of signals between chips is performed using light using the light emitting element 12 and the light receiving element 13. As shown in FIG. 1 (bl), a transistor using breakdown light emission between emitter and base is used as the light emitting element 12, and a phototransistor with an open base is used as the light receiving element 13.

第１のチップ１は、珪素（Ｓｉ）を用い低速部と電源回
路を形成する。The first chip 1 uses silicon (Si) to form a low-speed section and a power supply circuit.

第２のチップ４は、ガリウム砒素（ＧａＡｓ）を用い高
速部を形成し、ここである程度まとまった処理を済ませ
、結果的に遅い信号授受でよいような構成にして、光に
より第１のチップ１と信号授受を行う。The second chip 4 uses gallium arsenide (GaAs) to form a high-speed section, where a certain amount of processing is completed, and as a result, it is configured so that only slow signal transmission and reception is required. and sends and receives signals.

例えば第２のチップ４はプロセッサを構成し、内部は回
路を簡単化するため１ビツトの演算器にする。しかし出
力はパラレルになるようにインクフェイスを考慮すれば
よい。しかし第２のチップ４は高価であるためパラレル
処理の回路をチップに入れるとチップサイズは大きくな
り、歩留りが低下する。For example, the second chip 4 constitutes a processor, and has a 1-bit arithmetic unit inside to simplify the circuit. However, it is only necessary to consider the ink face so that the output is parallel. However, since the second chip 4 is expensive, if a parallel processing circuit is included in the chip, the chip size will increase and the yield will decrease.

ここでは１ビツトを直列処理する簡単な回路にしたため
、その高速性を生かしてビットを小さく落とした演算処
理をして、結果だけを光でやりとりをする。Here, we have created a simple circuit that processes one bit in series, so we take advantage of its high speed to perform arithmetic processing on smaller bits, and only exchange the results using light.

以上のようにシリアルに処理したデータをパラレルに出
すような構成に適している。As described above, it is suitable for a configuration in which serially processed data is output in parallel.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、 １、チップ２個を１チップ分の面積で構成できる。 As explained above, according to the present invention, 1. Two chips can be constructed with an area equivalent to one chip.

ｉｉ、各チップは異なるテクノロジのＬＳＩで構成でき
る。ii. Each chip can be configured with LSIs of different technologies.

ｉｉｉ　、チップ間の信号の伝達手段に要する面積はパ
ッドまたはバンプより小さくてすむ。iii. The area required for the means for transmitting signals between chips is smaller than that of pads or bumps.

ｉｖ、チップ間の電位は自由に選択できる。iv. The potential between chips can be freely selected.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）、　（ｂｌはそれぞれ本発明による２個の
チップよりなるＬＳＩの断面図、光伝送部を拡大した断
面図である。 第２図は従来例による２個のチップよりなるＬｓｒの断
面図である。 図において、 １は第１のチップ、　　２はパッド、 ３．５はバンプ、　　　４は第２のチップ、６．７はワ
イヤ、　　　８はパッケージ、９は内部リード、　　　
１０は外部リード、１１は蓋、　　　　　　１２は発光
素子、１３は受光素子 を示す。 第１記 滲２侶FIGS. 1(a) and (bl are a cross-sectional view of an LSI made of two chips according to the present invention, and an enlarged cross-sectional view of an optical transmission part. FIG. 2 is a cross-sectional view of an LSI made of two chips according to a conventional example). In the figure, 1 is a first chip, 2 is a pad, 3.5 is a bump, 4 is a second chip, 6.7 is a wire, 8 is a package, 9 is an internal lead,
10 is an external lead, 11 is a lid, 12 is a light emitting element, and 13 is a light receiving element. Part 1

Claims (1)

【特許請求の範囲】[Claims] 　複数個の半導体チップをその表面が対向するよう積み
重ね、チップ間の信号伝送を該表面間での光信号で行う
手段を有することを特徴とする半導体装置。1. A semiconductor device comprising means for stacking a plurality of semiconductor chips so that their surfaces face each other and transmitting signals between the chips using optical signals between the surfaces.
JP59221525A 1984-10-22 1984-10-22 semiconductor equipment Pending JPS6199362A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59221525A JPS6199362A (en) 1984-10-22 1984-10-22 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59221525A JPS6199362A (en) 1984-10-22 1984-10-22 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS6199362A true JPS6199362A (en) 1986-05-17

Family

ID=16768076

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59221525A Pending JPS6199362A (en) 1984-10-22 1984-10-22 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS6199362A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999044236A1 (en) * 1998-02-27 1999-09-02 Seiko Epson Corporation Method of manufacturing three-dimensional device
WO1999045593A1 (en) * 1998-03-02 1999-09-10 Seiko Epson Corporation Three-dimensional device
US6777801B2 (en) 2000-03-17 2004-08-17 Oki Electric Industry Co., Ltd. Semiconductor device and method of manufacturing same
US7112468B2 (en) 1998-09-25 2006-09-26 Stmicroelectronics, Inc. Stacked multi-component integrated circuit microprocessor
US7554169B2 (en) * 2002-12-17 2009-06-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
JP2009260373A (en) * 2009-07-27 2009-11-05 Fujitsu Microelectronics Ltd Semiconductor device, its method for manufacturing, and semiconductor substrate

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6627518B1 (en) 1998-02-27 2003-09-30 Seiko Epson Corporation Method for making three-dimensional device
WO1999044236A1 (en) * 1998-02-27 1999-09-02 Seiko Epson Corporation Method of manufacturing three-dimensional device
EP0986104A1 (en) * 1998-02-27 2000-03-15 Seiko Epson Corporation Method of manufacturing three-dimensional device
EP0986104A4 (en) * 1998-02-27 2003-07-30 Seiko Epson Corp METHOD FOR MANUFACTURING A THREE-DIMENSIONAL COMPONENT
US6846703B2 (en) 1998-03-02 2005-01-25 Seiko Epson Corporation Three-dimensional device
WO1999045593A1 (en) * 1998-03-02 1999-09-10 Seiko Epson Corporation Three-dimensional device
US7112468B2 (en) 1998-09-25 2006-09-26 Stmicroelectronics, Inc. Stacked multi-component integrated circuit microprocessor
US6777801B2 (en) 2000-03-17 2004-08-17 Oki Electric Industry Co., Ltd. Semiconductor device and method of manufacturing same
US6905913B2 (en) 2000-03-17 2005-06-14 Oki Electric Industry Co., Ltd. Semiconductor device and method of manufacturing same
US7414320B2 (en) 2000-03-17 2008-08-19 Oki Electric Industry Co., Ltd. Semiconductor device and method of manufacturing same
US7554169B2 (en) * 2002-12-17 2009-06-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
US7939831B2 (en) 2002-12-17 2011-05-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
US8153506B2 (en) 2002-12-17 2012-04-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
JP2009260373A (en) * 2009-07-27 2009-11-05 Fujitsu Microelectronics Ltd Semiconductor device, its method for manufacturing, and semiconductor substrate

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