JPS6196594A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To increase an accumulated charge quantity and to expand a action margin without increasing a pattern area, by connecting a memory cell through a bit line and an inverting bit line to a differential type detecting amplifier. CONSTITUTION:When a memory cell 111 is selected, a word line WL1 is set to a high electric potential at the time of writing, a transistor Q11 is connected, bit lines BL and -BL are biased in accordance with the writing data, + or -(VCC)-(VSS) is impressed to both ends of a capacitor C11 and the information charge quantity becomes 2VCC.C11. On the other hand, after the lines BL and -BL are set to an equal electric potential at the time of reading, a line WL1 is made into a high electric potential and Q11 is connected. An electric potential difference of the lines BL and -BL is read by the differential type detecting amplifier 12 and information OUT is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a dynamic semiconductor memory device, and in particular to realizing a larger capacity and faster speed.

[Technical background of the invention]

Generally, as a dynamic type semiconductor memory device, a memory cell consisting of one transistor and one capacitor as shown in FIG. 5 is widely used. In FIG. 5, WL is a word line, BL is a bit line, and a memory cell 1 is located at the intersection of the word line WL and BL.
1 is arranged. The memory cell 1 has a bit 1 at one end.
It consists of a transistor Q1 connected to fMBL and whose conduction is controlled by having its dart connected to the word line WL, and a capacitor C1 connected between the other end of this transistor Q1 and the power supply vCc.

Next, the operation in the above configuration will be explained. In the write mode, first, the word line WL is set to a high potential, the transistor Q1 is turned on, and the memory cell 1 is selected.

Next, by setting the bit line BL to a high potential or a low potential depending on the write data, the potential of the memory 7-D is set to QV or V. By setting the voltage to C, information is stored by applying a voltage of Ov or vCc across the storage capacitor C1.

On the other hand, in the read mode, the bit line BL is set to a predetermined potential in advance and placed in a floating state, and then the transistor Q1 is made conductive by the word line WL. Then, by detecting and amplifying the signal potential of the bit line BL, which changes slightly depending on the charge of the storage node M, the memory cell 1
Read out the memory information of .

[Problems with background technology]

However, the above configuration has various problems as described below. First of all, write and read information is stored in the form of electric charge in the capacitor C1, and the difference in the amount of charge between '1' and 'O' is Vco-C1 (here, the capacitor C1 is In order to protect the signal charge from α rays and other noise, it is necessary to set the capacitance C1 large.For this reason, the capacitance C1 for information storage is It requires a large turn area and is difficult to achieve high density.

Second, in order to realize a highly sensitive sense amplifier, pit line pairs BL are usually complementary.

BL is required, in this case, p) fv” & Il
The L side needs to be connected to a dummy cell. Therefore, extra chip area is required.

Third, if the power supply voltage during writing, reflation, or shutdown is different from the power supply voltage during reading, malfunctions are likely to occur.

This is because the potentials of the dummy cell and the memory cell are set at different times and are directly affected by fluctuations in the power supply voltage.

[Purpose of the invention]

This invention was made in view of the above circumstances,
The purpose is to provide an excellent semiconductor memory device that can increase the amount of stored charge without increasing the area of the 9-channel transistor, and can achieve a wide range of operating characteristics.

[Summary of the invention]

That is, in this invention, in order to achieve the above object, one end of a memory cell configured by connecting one transistor and one capacitor in series is connected to one end of a differential sense amplifier via a bit line. At the same time as connecting to the input end of
The other end of the memory cell is connected to the other input end of the differential sense amplifier via an inverted bit line.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. A memory cell 111 is located between one pit line pair BL, BL in FIG.

No. 12, . . . are provided for the bit line pair BL.

BL are each connected to the input end of the differential sense amplifier 12. Each of the memory cells 111e7J2+... has one transistor Qu+Qlz+...
. . and one capacitor C11+C12, . . . .

One end of each of the transistors Ql 1 +Q12 +... is connected to the bit line BL, and the other end is connected to one electrode of the 9-channel C port IC 12e..., and each dirt is connected to the word % W L @ ＋W
It is connected to L21... and conduction is controlled. Further, the other electrodes of the above-mentioned capacitors C1□, C12, . . . are respectively connected to the inverted pin WDBL.

Next, the operation in the above configuration will be explained. now,
Assuming that the memory cell 111 is selected, in the write mode, the word line WLI is set to a high potential to make the Q-th transistor conductive.

Then, the bit lines BL and BL are biased to the CC level and the v8s level, or the opposite, the vs8 level and the vcc level, respectively, according to the write data, so that the voltage of Apply. By doing this, the information charge amount is 2Vc, @
C1 (as v, 5=Ov).

On the other hand, reading and retrieving are performed as follows. First, set the bit line pair BL and BL to equal potential,
After that, the word line WL1 is set to a high potential (usually the power supply voltage ■cc
The voltage is set to a voltage higher than the threshold voltage of the transistor Qll to make the transistor 9 conductive. If the potential of the storage node IvIl is lower than the inverted bit line BL, the potential of the storage node IvIl is lower than the inverted bit line BL. If c is lower, a current flows in the direction of the arrow shown in the figure for the canopy C1l, and the bit line BL is an inverted pit. The potential is lower than that of hBL. In addition, storage node M1 is inverted (pitch)
In 5JA '6, which is longer than BL by vcc, the current flows in the opposite direction to the above arrow, and the bit line BL becomes the inverted bit line B.
L) becomes a high potential.

The potential difference between the bit line pair BL and BL is amplified by the differential sense amplifier 12 to obtain read information OUT, and the differential sense amplifier 12 amplifies the potential difference between the bit line pair BL and the capacitor C1l via the bit line pair BL and BL. Refreshing is performed by applying a voltage with a polarity corresponding to the information stored in the memory cell. 0 Figure 2 shows the timing chart when reading '1#' from the memory cell, and Figure 3 shows the timing chart when reading 0''. The charts are shown respectively.As shown in the figure, time 1
G to pit line pair BL.

The potential of BL is set to an equal value by Zorichaso or Zoldawan, and information is read from the memory cell at time tl. As a result, time 1. The potential of the bit lines BL and BL is ``H#'' when the stored information is @1''.
level, if the stored information is "O", the bit line BL is "
These potential differences are amplified by the differential detection amplifier 12, and at time t3,
If the stored information is @1m, the bit line BL is "
cc level and inverted bit iBL become Vss level.

Also, if the stored information is “O”, the bit line B
L is at the v8s level, and the inverted bit and g lines BL are at the vcc level.

According to such a configuration, twice the amount of information charge can be obtained compared to the case shown in FIG. 5, even if the storage capacitor/mother has the same capacity. Therefore, higher density is possible. Also, bit line pair BL.

The signal appearing at both ends of BL corresponds to the polarity of the potential difference applied to both ends of each storage capacitor, so even if the power supply voltage is changed between refreshing and reading. be able to perform correct movements,
A wide range of motions can be obtained.

FIG. 4 shows another embodiment of the present invention, which includes nine transistors #Q12+Qts+- for memory cell selection, a capacitor 011e CI Z +C13+ for memory,
. . . are alternately connected to the bit line pair BL, BL. In the figure, the same components as those in FIG.

According to such a configuration, the pit line pair BL.

Since the load capacitance of BL can be set to be the same, the balance of characteristics during writing or reading can be improved.

In addition, pattern layout is easier and higher density can be achieved.

Furthermore, in the configurations shown in FIGS. 1 and 4, one end of the 8th element (capacitor) is connected to a common line (for example, bit line BL), so that unselected memory cells Then, when a low potential is stored in the storage node, the bit line BL becomes -vcc (+vsa) after the read operation.
) is sometimes transferred. At this time, if the substrate potential is biased to V8s or the like, there is a risk that the source and drain of the transistor will be in a negative relationship with the substrate, resulting in malfunction. In order to prevent this, it is sufficient to apply a substrate voltage lower than -vcc to the substrate. Setting the absolute value of the substrate bias voltage high in this way has the effect of reducing the parasitic capacitance of the bit line and also reducing the leakage current of the information transfer transistor.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to obtain an excellent semiconductor memory device which can increase the amount of stored charge without increasing the pattern area and can achieve a wide range of operating characteristics.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining a semiconductor memory device according to an embodiment of the present invention, FIGS. 2 and 3 are timing charts for explaining the read operation in the circuit of FIG. 1, and FIG. The figure is a circuit diagram for explaining another embodiment of the present invention, and FIG. 5 is a diagram for explaining a conventional semiconductor memory device. "l m112 #... Memory cell, 12.
...Differential sense amplifier, wt, 1, WL, 2.・・・
...Word starvation, BL, BL...Bit line, OUT
...Output signal. Time opening - Figure 3 UT

Claims (1)

[Claims] In a dynamic semiconductor memory device in which memory cells each consisting of one transistor and one capacitance element connected in series are arranged in row and column directions, one end of the memory cell is connected to a bit line via a bit line. The memory cell is connected to one input end of a differential sense amplifier for reading, and the other end of the memory cell is connected to the other input end of the differential sense amplifier via an inverted bit line. A semiconductor storage device.