JPS6195612A - Reset signal generating circuit - Google Patents

Abstract

PURPOSE:To keep surely the pulse width of a reset signal by charging a capacitor with the 1st charging and charging the capacitor with the 2nd charging circuit having a short time constant when a capacitor terminal voltage reaches a prescribed voltage. CONSTITUTION:When an output voltage of a constant voltage circuit rises and exceeds a prescribed value after application of power, an output of the 2nd comparator 28 goes to high level, a discharge transistor (TR)23 of a discharge circuit 21 is turned off and the charging of the capacitor 13 by a charging resistor 14 is started. The terminal voltage of the capacitor 13 rises and a voltage of an output terminal 12 also rises. When the voltage at the output terminal 12 is a prescribed value or over, the output of the 1st comparator circuit 27 goes to high and the 2nd charging circuit 16 having a charging time constant shorter than that of the 1st charging circuit is activated.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a reset signal generation circuit that generates a signal to reset a microcomputer, etc., and particularly relates to an IC (integrated circuit) The present invention relates to a reset signal generation circuit suitable for.

(b) Prior Art Recently, microcomputers have been used in various consumer devices. In order for the microcomputer to operate normally, the microcomputer must [K I when power is cut off
After setting J, the internal circuit must be reset to XKL. However, since the reset signal for applying a reset needs to be generated for a certain period of time when the tolerance voltage of the microcomputer becomes sufficiently high, it must be generated appropriately in relation to the power supply voltage trap of the microcomputer. Must be. Therefore, as a reset signal generating circuit, for example, the magazine "Transistor Technology" published on December 1, 1982, December 1982 issue advertising feature 4
Those described on page 3 are known. This reset signal generation circuit is simplified as shown in FIG. 2, and includes a power supply terminal (1) to which a power supply voltage is applied, a constant voltage circuit (2) that generates a constant voltage from the power supply voltage, A capacitor 13) charged by the power supply voltage, a comparator circuit (4) that compares the terminal voltage of the capacitor (3) with a reference voltage, and a reset function generated in response to the output signal of the comparator circuit (4). It is composed of a transistor (5). In the case of Figure 2, when the power is turned on, the capacitor (
3) starts charging, but while the terminal voltage of the capacitor (3) is lower than the reference voltage, the output of the comparator circuit (4) becomes rHJK and the transistor (5) is turned on. When the terminal voltage of the capacitor (3) increases according to the time constant determined by the resistor (6) and the capacitor (3) and becomes higher than the reference voltage, the output of the comparator circuit (4) becomes rLJ, and the transistor ( 5) is turned off. Therefore, when the power is turned on, it is possible to generate a predetermined reset signal at the output terminal (power), and if this reset signal is applied to the microcomputer that becomes the controlled circuit (not shown), the reset signal when the TiL source is turned on can be It can be done.

1 Furthermore, when the power is cut off, the charge accumulated in the capacitor (3) is discharged via the resistor (8). Therefore, the terminal voltage of the capacitor (3) decreases to below the reference voltage, and the output of the comparator circuit (4) becomes rH.
J and the transistor (5) turns on. Therefore, even when the power is cut off, a reset signal can be generated and the microcomputer can be reset.

←→ Problems to be Solved by the Invention However, the circuit shown in FIG. 2 has the disadvantage that, when integrated into an IC, the number of external connection terminals increases. That is, the circuit shown in Figure 2 has an external connection terminal for externally connecting a capacitor (3) for setting the width of the reset signal to a predetermined value to the input terminal of the comparator circuit (4), and a terminal for controlling the reset signal. This required an external connection terminal for applying voltage to the circuit. Therefore, if the signal generation circuit shown in FIG. 2 was incorporated into a power supply phase IC having other functions such as a muting function in addition to a reset function, there was a risk of running out of external connection terminals.

B) Means for Solving the Problems The present invention has been made in consideration of the above points, and it connects a capacitor to the output terminal where the reset signal is generated, and charges the capacitor. The first charging with a time constant
a reference voltage generation circuit that generates a reference voltage, a comparison circuit that compares the voltage of the output terminal with the reference voltage, and a charging time constant that charges the capacitor according to the output signal of the comparison circuit; The present invention is characterized in that a second optical generating circuit for charging with a second charging time constant shorter than the second charging time constant, and a discharging circuit for the capacitor are provided.

(E) Function The present invention connects a capacitor to the output terminal to ensure the pulse width of the reset signal, and first connects the capacitor to the first
The capacitor is charged with a first time constant by a photoelectric circuit, and when the terminal voltage of the capacitor reaches a predetermined value, the capacitor is charged with a second time constant by a second charging circuit.

(f) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the invention, and (9) is 1! The power supply terminal to which the source pressure is applied, α■ is a constant voltage circuit that obtains a constant voltage from the reverse voltage of the power supply, 0υ is the first and second reference tEEVI and ['V2 (t start, V, > V,) 0 is the output terminal from which the reset signal is obtained, f131 is the capacitor connected to the output terminal azK, a voltage V! obtained at the furnace power supply output terminal 09;
Accordingly, the capacitor α3 is filled with the first charge.

A charging resistor (first photoelectric circuit) that charges with a time constant T1, exposed is an inverter αη, and the first and second resistors connected by a current mirror.
Consists of transistors U and ■ and a diode QO,
A second photoelectric circuit that charges the capacitor (131) with a charging time constant T of 5g2, which is shorter than the first charging time constant, is composed of an inverter (23) and a discharge transistor (c), and 0 is a voltage dividing circuit consisting of a resistor Ca and (2) that divides the output voltage 71 of the constant voltage circuit port 0), and (2) is a reference voltage generating circuit (second standard of lυ). Awakening pressure■2
a first comparison circuit that compares the voltage of the output terminal (2) and the voltage (4) of the output terminal (2), and drives the second charging circuit (4) with the output signal thereof;
and (c) compares the first base voltage (1) of the reference voltage generation circuit Uυ with the output voltage V of the voltage dividing circuit [with], and drives the discharge circuit with the output signal thereof. 2 comparison circuit.

Next, the operation will be explained. When the power is turned on, first, the reference magnetic pressure generation circuit 0υ generates the first and second magnetic pressures V1 and ■,
occurs, and the first and second voltages V.

and ■ are the n second and first comparison circuits C28 and □, respectively.
is applied to the negative input terminal of - 10,000, since the output voltage V of the constant voltage circuit αα is not yet high enough, and the output voltage V of the voltage divider O is in the relationship V,>V, the second comparison circuit (c) The output becomes rLJ, and the number range transistor in the discharge circuit turns on. Furthermore, if the capacitor αJ is completely discharged in the initial state, the voltage at the output terminal 03 applied to the positive input terminal of the first comparator circuit (3) is
4 is V! >V4, and the output of the first comparison circuit (c) is rLJ, so the second photoelectric circuit board has stopped operating. Therefore, the 1 voltage at the output terminal α2 remains in the "L" state immediately after the power is turned on.

As time passes and at time t1, the output voltage V of the constant voltage circuit aG increases, and from the voltage dividing circuit C'4) vl<
A voltage of V S is generated, the output of the second comparator circuit becomes HJK, and the discharge transistor of the discharge circuit is turned off. Therefore, a capacitor (1
31 starts, but since the first charging time constant T1 determined by the charging resistor I and the capacitor OJ is large, the terminal voltage of the capacitor D gradually rises, and the voltage at the output terminal 03 increases. will be accordingly. Therefore, at time t, the voltage ■4 of the output terminal 02 becomes V, (V,
When it becomes vc, the output of the first comparator circuit becomes rHJVc, and the second photoelectric circuit cape starts operating. In the second photoelectric circuit wing, when the input of the inverter Q7) is rLJ, the output of the inverter Q7) becomes rHJ, and the collector current of the first transistor 0υ does not flow, and the collector current of the second transistor a9 also does not flow. In addition, the inverter Q71
When the input of the inverter Qη is rHJ, the output of the inverter Qη is rLJ
, the collector of the first transistor t181'! [The accent flows and a predetermined value 1 is applied to the collector of the second transistor 4 in a mirror relationship! It is designed to create a flow.

Therefore, when the output of the first comparison circuit □□□ becomes rHJK, a charging current is generated from the second photoelectric circuit 4, and the capacitor a3 receives a second charging current that is shorter than the first charging time constant T1. The capacitor α is photoelectronized with a time constant T, and the capacitor α
The terminal voltage of the moat, that is, the rolling pressure V4 of the output terminal u4 becomes rHJ almost immediately.

When the above-mentioned 90<, 1 source is turned on, the power supply output terminal Q
5 becomes a constant voltage, the voltage at the output terminal a2 is maintained at rLJ, so the voltage at the output terminal az becomes rLJ.
By applying the constant voltage of the X source output terminal 0S to the controlled circuit as a reset signal and the constant voltage of the X source output terminal OS as a power supply voltage to the controlled circuit, it is possible to reliably reset and drive the controlled circuit. In addition, in the example,
The first reference voltage v1 of the reference voltage generation circuit Uυ is set to 4.5V,
The second reference voltage V is set to 1.2V, the output constant voltage of the constant voltage circuit Ql is set to 5.6V, and the power supply voltage applied to the power supply terminal (9) is set to 8V.

Next, the operation when the power is cut off will be explained. When the power is cut off at time [,, the output voltage V of the constant voltage circuit CIQI first decreases and becomes V+>Vs. Therefore, the output of the second comparator circuit becomes "LJK", the discharge transistor of the discharge circuit O is turned on, and discharge of the capacitor u31 is started. Go on,
When the voltage V4 of the output terminal 0z decreases until v2>V4, the output of the first comparator circuit becomes rLJK,
The operation of the second charging circuit stops, and then the power terminal (
9), the circuit of FIG. 1 returns to its initial state in response to a decrease in the power supply voltage applied to the circuit.

Incidentally, the discharge of the capacitor 0 when the power supply is cut off can be arbitrarily performed using a discharge circuit other than the discharge circuit shown in the embodiment of FIG.

Figure 3 shows the source voltage Vs (Figure 3 (A)) obtained at the power supply output terminal 0SK for the controlled circuit, and the output voltage (reset signal) obtained at the output terminal Q2 (Figure 3 (Ro)). )). When the power is turned on at time t0,
The power supply voltage ■ increases until time t.

When the voltage exceeds the first reference voltage (1), the discharge transistor in the discharge circuit is turned off. Therefore, capacitor Q3
1 is charged by a charging resistor (14), and the output voltage (2) gradually rises, and when it exceeds the second voltage (41) V at time t, the second photoelectric circuit is activated, and the output voltage (4) increases. Rapid K
Become rHJ. Also, if the power is cut off at time t,
The Souki Houya transistor (23) turns on and quickly discharges the charge of the capacitor αJ, so the output voltage becomes rLJ.

(F) Effects of the Invention As described above, according to the present invention, it is possible to provide a reset signal generation circuit that can generate a reset signal at a timing corresponding to a change in the ta voltage of a controlled circuit. Since the circuit configuration is such that a capacitor that determines the generation time of the reset signal is connected to the output terminal of the reset signal, the present invention can provide a reset signal generation circuit with a small number of terminals when integrated into an IC.Furthermore, Since the capacitor is sequentially charged by the first photoelectric circuit with a long time constant and the second photoelectric circuit with a short time constant, the pulse width of the reset signal can be reliably maintained at VC and can be set arbitrarily.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional reset circuit, and FIG. 3 (a) and middle) are characteristic diagrams for explaining the present invention. It is. Explanation of main drawing numbers αQ...Constant voltage forming circuit, Uυ...Reference signal generation circuit, ■...Output terminal, α3...Capacitor, α
ka...charging resistor, 4...second photoelectric circuit, g...
Discharge circuit, @...first comparison circuit. Applicant: SANYO Electric Co., Ltd. (1 person) and 1 other agent: Yasuo Sano, patent attorney Figure 1 Figure 3

Claims (1)

[Claims] (1) A circuit for generating a reset signal to be applied to a controlled circuit, comprising an output terminal from which the reset signal is obtained, a capacitor connected to the output terminal, and a capacitor connected to the capacitor during first charging. a first photoelectric circuit that charges at a constant rate; a reference voltage generation circuit that generates a reference voltage; a comparison circuit that compares the voltage of the output terminal with the reference voltage; a second photoelectric circuit that photoelectrically charges the capacitor with a second charging time constant that is shorter than the first charging time constant; and a discharging circuit for the capacitor.