JPS6195406A - Input/output control device - Google Patents

Abstract

PURPOSE:To reduce the number of control lines for the display of an operation key sharply by providing the titled device with a circuit for switching data input/output and a serial data I/O circuit for controlling an I/O terminal on the basis of serial data. CONSTITUTION:An address deciding circuit 37 decides an inputted address of n-bit on the basis of serial signals 34, 35 applied to a serial data I/O circuit 38, and when the address corresponds to the address of the I/O control device, applies the succeeding serial data to a data I/O switching circuit 39. The circuit 39 switches the data in the sending direction, outputs the serial data of m-bit to an output circuit 40 to drive output transistors 45 in I/Os 44-50. On the other hand, data inputted to I/O terminals 47-51 are applied to an input circuit 41, the circuit 39 is switched in the data extracting direction and the inputted data are extracted as a signal 34 by the circuit 38.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an input/output control device that controls a plurality of input/output terminals using military data.

Conventional configurations and their problems In recent years, video equipment such as television receivers have many functions, so many switches and displays for operating them are installed on the front panel. It is becoming.

A conventional input/output control device will be described below with reference to the drawings. FIG. 1 shows a block diagram of a conventional input/output control device. In the figure, 1 is an input/output control device, 2 is a key display block attached to the front operation panel, 3 to 8 are input/output lines for the key matrix, 9 to 17 are output lines for status display, 18 to 26 is various operation keys, 2
There are 6 to 33 various display elements.

In the above-described configuration, the input/output control device is actually located on the main body side, and the operation key display element is often installed mainly on the front panel separated from the main body side. Therefore, in the configuration shown in FIG. 1, as many as 15 lines are connected between the main body and the front panel, and the number of lines increases or decreases depending on the type of operation key display.

In the configuration of the input/output control device as described above, a very large number of lines are connected between the main body and the front panel for displaying operation keys, and a large number of input lines are connected in the input/output control device. The problem is that an output terminal is required.

OBJECTS OF THE INVENTION An object of the present invention is to provide an input/output control device It that solves the above-mentioned conventional problems and can significantly reduce the number of control lines next to the operation key display. do.

Structure of the Invention The input/output control device according to the present invention includes a plurality of input/output terminals,
It includes an output circuit that drives the output terminal, an input circuit that inputs data from the input terminal, a circuit that switches all data input/output, and a serial data input/output circuit that controls the input/output terminal using serial data. , the input/output terminals of the pocket number can be controlled by serial data.

Description of Persimmon Examples An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 shows a functional block diagram of an input/output control device in an actual case of the present invention. In the figure,
34, 35, 36 are signals for serial data transfer, 37 is an address discrimination circuit, 38 is a serial data input/output circuit,
39 is a data input/output switching circuit, 40 is an output circuit, 41 is an input circuit, 42 is one of the output signals, one of the 43 input signals, 44 is an input/output transistor circuit, 46 is an output transistor, 46 is an input transistor , 47 is one of the input/output terminals, 48.50 is another input/output transistor circuit, 49
．． 51 is another input/output terminal.

The operation of the input/output control device configured as described above will be described below.

In FIG. 2, the serial signals 34, 36, and 36 are
They look like figures a, b, and c. 34 is a data signal;
36 is a data transfer clock, and 36 is an input/output switching signal. Outputting data to the input/output terminal is called "data transfer," and putting data at the input/output terminal on a serial signal is called "data transfer." ``Removal of ``. FIG. 3C shows the signal 36 when data is sent, and FIG. 3D shows the signal 36fc when data is taken out.

First, considering the case of taking in data, an n-bit address signal specific to the input/output control device is set in 34 during period A, and is added using transfer lock 36. Next [34
Transfer m bits of data to the lock 36 in period B.
Add using. At this time, when sending data, the input/output switching signal 36 is set to high level after a period clc. Furthermore, 36 adds a negative pulse at intervals as an end pulse. This completes the data transfer.

As a result of the above operations, in FIG. 2, the address discrimination circuit 37 discriminates the input yc n-bit address from the signals 34 and 35 applied to the 7 real data input/output circuit 38, and the address of the input/output control device. , the following serial data is transferred to the data input/output switching circuit 3.
In addition to 9, the output circuit is switched to the galo which sends data by the signal 36, the output circuit outputs 40Km bits of serial data, and the output transistor 46 of the input/output circuit 44...5o
to drive.

In addition, when extracting data, the process up to the period in FIG. 3 is the same as the case of data sending, but in period E, the signal 36 is set to low level as shown in FIG. 3 d, and the signal 35 is added. Accordingly, serial data is output during period E.

Furthermore, the end pulse of period F ends the data transfer.

The above operation is shown in FIG. 2 at the input/output terminals 47...
61 is applied to the input circuit 41, the data input/output circuit 39 is switched to the data extraction direction by the signal 3θ, and the serial data input/output circuit w! 13B, the signal 34 is extracted -n.

For the purpose of explanation, a non-inventive circuit is shown in FIG. In FIG. 4, 62 is a serial input/parallel output shift register, 53 is a "res decoder, 64 is
is a counter 1.56 to 58 that counts n pulses.
is a gate, 69 is a shift register, soq latch, 61
is a gate, 62 is a counter 2 that counts ma pulses, 63 to 64 are gates, 65 is a shift register with parallel manual serial output, 66 is a gate, 67 is a counter 3 that counts m pulses, and 68 to 69 are counters that count m pulses. It is a gate.

The operation will be explained below based on the operation timing chart shown in FIG. First, consider the case where m-bit data is output to all input/output terminals. Gates 55, 58 are now in a state where they each pass signal 34, 35;
The first n bits of data are input to the shift register 62 by the clock signal 35 (FIGS. 5d and 5e).

At the same time, the signal 35f'i is counted by the counter 1 of 64, and the output at the time when all n pulses have been counted is made into a signal (FIG. 5f). At this time, n pieces of data are input to the shift register 62, and data n, Q, to Qn are established (FIG. 5q). The data for Q1 to Qn is 6
The decoder IK of No. 3 determines the address, and if it matches the address of the input/output control device, sets its output to high level (Fig. 6h).

When n data are input f'L7, 54 and 5
The output of gate 67 becomes high level, and the output of gate 67 becomes high level (FIG. 6, 1). At this time, the gates 55 and 56 are closed by the output of 64, and thereafter, no data or transfer lock is input to the shift register 52 until the counter 1 of 54 is cleared n. When the output of the gate 57 becomes high level, the signal 36 is at the high level during the m-bit data period, so the signal 36 is passed through the gate 58 to the signal 36.
4 is added to soft register 59 (FIG. 6j).

On the other hand, regarding the signal 35, the output of the gate 67 is at a high level in the gate 61, and when the signal 36 sends data as shown in FIG. 5C, the m-bit data period is at a high level, so the shift register 59 (Fig. 6k).

Therefore, in the data period of m bits, the signal 36
When is at a high level, data is input to the shift register 59, and data Q1 to Qm of the shift register 59 are established by m clocks (FIG. 6, 1).

At the same time, the output of the gate 61 is counted by the counter 2 of 62, and when n1m pulses have been counted, the output is set to high level (Fig. 5).

At this time, a positive pulse is generated at the gate 63 by the falling pulse of the signal 36, as shown in FIG.
Joins latch 60 and latches data 01 to QIn,
Output No. 100 Q, /~Qm' (Fig. 6 0) This 01
'~Qfn/ is the output signal 42 of the output circuit in FIG.
etc., and drives the output transistor 45 etc. and outputs to the input/output terminal 47 etc.

The output of gate 63 simultaneously clears counter 2 of 63, and the output of gate 64 clears counter 1 of 54 as shown in FIG. The shift register 62 is completely cleared and prepared for the next data input.

As described above, m-bit data is output by the serial signals 34, 35, and 36.

Next, a case will be described in which m-bit data is taken in from the input/output terminal. FIG. 6 shows a timing diagram of each signal. In FIG. 6, except for the signal 36, the operation until the n-bit address signal is established, that is, FIG.
The operation up to this point is the same as the case of sending data in Fig. 6, so the explanation will be omitted and the explanation will focus on the part for extracting the data. When the address is determined, the output of the gate 57 becomes a no-y level (6th Figure 1). Now, since the signal 36 is at a low level during the continuous m-bit data period as shown in FIG. The inverted clock is applied to the shift register 66 via the gate 66 as shown in FIG. Shift register 66 is gate 6
The input data D1'-Dml are sequentially outputted as serial data by the clock signal No.6 (FIG. 6k).

At this time, the reason why the shift clock of the shift register 66 is inverted is because the data acquisition clock of the device that is trying to take out data from this input/output control device is the signal 35 itself, so the hand clock phase is advanced and the data is This is to send out. The output data of the shift register 66 is output as serial data to the signal 34 via the gate 69 (FIG. 6, 1). On the other hand, the output of the gate 66 is counted by the counter 3 at 6, and when m pulses are counted, the output is set to high level as shown in FIG. A negative pulse is output by (m in Fig. 6).

The output of gate 68 clears counter 3 at 670 and passes through counter 64 to counter 1.54 as shown in FIG. Clear the shift register 62 and prepare for the next operation.

As described above, by setting the m-bit data period signal 36 to a low level, the input signals D1' to Dm/ of the shift register 65 can be taken out as the signal 34 as serial data. This input signal D1/~Dm' is the second
It is a signal 43 etc. applied to the input circuit shown in the figure, and is applied to the output of the input transistor 46 etc. of the input/output circuit, and shows data of the input/output/ml element 47 etc.

As described above, by using the circuit as shown in FIG. 4, using the signal 34 as input/output data, the signal 36 as a shift clock, and the signal 36 as an input/output switching signal, the four input/output control devices t are configured. be able to.

Mayu, Figure 4 is an example of a leprosy, and the signal is 34°35.3.
The form of 6 may be different.

Effects of the Invention As described above, according to the present invention, the input/output terminals for the number of bubbles can be controlled using a fixed number of serial signals. By using this device, one of the input/output terminals is used for the output signal of the key matrix of the operation key, one is used for the input signal of the key matrix, and one is used for the output signal for displaying all m books. By distributing the input/output control device t on the front panel, the input/output terminals can be controlled with an extremely small number of wires, which is an excellent effect.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a 6-configuration example using a conventional input/output control device IT, Fig. 2 is a functional block diagram of an input/output control device according to an embodiment of the present invention, and Fig. 3 is a serial control thereof. A timing diagram showing a specific example of a signal, FIG. 4 is a specific circuit diagram of an input/output control device in an actual example of the present invention,
Fig. 6 is an operation timing diagram when sending data to the input/output control device shown in Fig. 4, Fig. 6 is an operation timing diagram when taking out data from the input/output control device shown in Fig. 4, and Fig. 7 is an operation timing diagram of the input/output control device shown in Fig. 4. FIG. 2 is a block diagram showing an example of an application of the input side #device of the invention. 34.35.36...Second input/output terminal, 37
... Address discrimination circuit, 38 ... Serial data input/output circuit, 39 ... Data input/output switching circuit, 40 ... Output circuit, 41 ...・・・
・Input circuit, 46... Output transistor, 46
...Input transistor, 47°49.51...
...First input/output terminal. Name of agent: Patent attorney Toshio Nakao and 1 other person
5 Figure (b) Official number 35 -LJ-LI], -1-[J-
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+59 output
Prisoner <p) Diagram 6 of the slant - ndo note - 1 竫 - rn bit - 1 < 0
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Claims (3)

[Claims] (1) a plurality of first input/output terminals, an output circuit that drives an output element connected to the input/output terminal, and an input circuit that inputs a signal of the input element connected to the input/output terminal;
A data input/output switching circuit that switches data between the output circuit and the input circuit, and a serial data input/output circuit that inputs and outputs the data as serial data from a plurality of second input/output terminals. An input/output control device, wherein the first input/output terminal is controlled by serial data applied to the output terminal. (2) The input/output circuit according to claim 1, wherein the serial data input/output circuit includes an address discrimination circuit, and controls the first input/output terminal when serial data indicating a specific address is input. Output control device. (3) The serial data input/output circuit includes one serial data input/output terminal, one clock timing input terminal, and one input/output control terminal. input/output controller.