JPS6194372A - Semiconductor memory element - Google Patents

Abstract

PURPOSE:To obtain a semiconductor memory element having the high degree of integration by forming a P<+>N<+> junction to the lower section of a source diffusion layer and fixing a source layer at the substrate potential of an Si substrate. CONSTITUTION:Field regions 1 and word lines 2 are superposed on a P<-> Si substrate 9 through a normal NMOS process, floating gates 4 are shaped. P ions are implanted, and N<+> type source-drain layers 3, 7 are formed through heat treatment. When a resist mask 11 is applied and B ions are introduced just under the source layer 3 and a P<+> layer 10 is formed through heat treatment, a semiconductor memory element displays Zener diode characteristics at not more than several V withstanding voltage. When concentration is further increased and a diffusion is inhibited, withstanding voltage can be reduced to approximately 0.5-1V, the element displays tunnel diode characteristics, and withstanding voltage often extends over approximately 0V. Accordingly, the potential of the source layer 3 can be operated by controlling the junction characteristics of the P<+> layer 3 and the N<+> layer 10 without using a bit line 6 and a connecting hole 5. The allowance of mask alignment is also unnecessitated, thus improving the degree of integration.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a semiconductor memory device designed to improve the degree of integration, and particularly to an ultraviolet erasable EFROM.

Alternatively, it is suitable for a memory matrix array such as a mask ROM.

(Prior Art) Among semiconductor memory devices, ultraviolet-erasable electrically programmable ROM, or EPROM, will be described in particular. A device structure of a silicon gate MOS memory having two layers of polysilicon is disclosed in Japanese Patent Publication No. 52-47675. The memory array cells of an EPROM having this structure are arranged on a semiconductor substrate as shown in FIG.

This FIG. 3 is a plan view, and FIG. 4 is a sectional view taken along line AB in FIG. 3. Reference numeral 1 in both FIGS. 3 and 4 is a field region, which is composed of a thick wiring film. This field region 1 is a region other than the so-called active region which becomes a MOSFET. Running vertically in the center is a source diffusion layer 3 formed in the silicon substrate 9, which serves as the source of the MOSFET.

Two words vertically on both sides of this source K scattering layer 3!
5L2 is provided. Word line 2 is a two-layer polysilicon gate, with wiring as a word line and EPROM
It also serves as a control gate. A drain diffusion layer 7 is formed outside each word line 2 . The drain diffusion layer 7 is the drain of the MOSFET.

In addition, the hatched area overlapping the lower part of the word line 2 is a floating gate 4, which is a first layer polysilicon gate electrode, and includes a source diffusion layer 3, a drain diffusion layer 7, and a word line. 2, and information is stored by injecting charges into the floating gate 4.

Also, in the lateral direction, an aluminum bit 1s6 is formed and connected to the drain diffusion layer 7 through the contact hole 5. Although not shown, the source diffusion layer 3 is connected to an aluminum ground line through a contact hole at a rate of about one for each MOS FET 8 to fix the potential.

1. The source diffusion layer 3 (hereinafter referred to as v11. line) is grounded. There is an aluminum bit $6 and word line 2 (
By raising the voltage of the second polysilicon (second polysilicon) to the voltage vcc (usually 5V), one bit is selected and data is read.

Normally, the source diffusion layer 3 of each bit is shared to form an ss line as shown in FIG. The potential is fixed at 1, ov). Normally, such as when reading data, the vo line is fixed to the ground potential.

When writing data, the source diffusion layer 3, ie, the vss line, may be raised to approximately +1 to 2V.

In this way, by adopting the (1) o line, it is no longer necessary to provide a contact hole in the source diffusion layer for one bit, and the degree of t, aWi has been improved.

(Problem to be solved by the invention) However, in such a conventional method, word m2 (
A mask alignment margin (Figure 3) is required to prevent the field region 1 (second polysilicon) from overlapping the vs line 3, and an aluminum bit line for fixing the potential of the vSs line 3 is required. 6. Since the contact hole 5 is required, it is an obstacle to further improving the degree of integration.

The present invention provides a semiconductor memory device that solves the above-mentioned problems of the prior art, such as the mask alignment margin and the need for aluminum pit lines and contact holes for fixing the vsS line potential. It is something to do.

(Means for Solving the Problems) The present invention provides a semiconductor memory device in which a diffusion layer of an opposite conductivity type is provided below a source diffusion layer to form a P″N+N+ junction.

(Function) According to the present invention, since the semiconductor memory element is configured as described above, the source diffusion layer and the P+ diffusion layer exhibit Zener characteristics with a withstand voltage of several volts or less, and the impurities in both diffusion layers are suppressed to a high level. Then, it exhibits tunnel diode characteristics and is fixed at a potential in a constant relationship with the silicon substrate.

(Embodiments) Hereinafter, embodiments of the semiconductor memory device of the present invention will be described based on the drawings. FIG. 1 is a plan view of one embodiment of the invention, and FIG. 2 (al) and FIG. In Figures 1 and 2 (al, Figure 2 (bl), Figure 3
The same parts as those in FIG. 4 will be described with the same reference numerals.

In FIG. 1, FIG. 2 1al, and FIG. 2[bl, 1.2 word fields are formed on the silicon substrate 9 through the normal NMO3 manufacturing process. s2 and this word line 2
As shown by the diagonal line overlapping the floating gate 4
After forming P and patterning the gate electrode,
Donor type impurities such as S and P are introduced into the entire surface of the - type silicon substrate 9 by ion implantation or the like.

Next, a heat treatment is performed to diffuse the impurities to form N+ diffusion layers 3 and 7, which are source/drain diffusion layers, with an impurity concentration of 2.times.10''c+n-'.

Next, resist 1 is applied so that only source diffusion layer 3 is exposed.
1, and 17 receptor type impurities such as B and sh are introduced directly under the source diffusion layer 3 by ion implantation at a high acceleration voltage as shown in FIG. , impurity concentration 5 × 10
A "cn+-" P diffusion layer 10 is formed. In the case of B, the source diffusion layer 3 and the P'' diffusion layer 10 form a vertical P+N" junction (FIG. 2(b)).

Source diffusion layer 3 and P1 diffusion layer 1 made in this way
0 indicates Zener diode characteristics with a breakdown voltage below V. If the concentration of these two diffusion layers is further increased (and diffusion is suppressed), the withstand voltage can be further lowered to about 05 to IV, exhibiting tunnel diode characteristics, and in some cases becoming almost OV.

Therefore, the potential of the source diffusion layer 3 can be fixed to the substrate potential without using the bit line 6 formed of aluminum wiring, the contact hole 5, or the like.

The potential of the source diffusion layer 3 at this time can be manipulated by controlling the characteristics of the P"N" junction between the source diffusion layer 3 and the P"diffusion layer 1o with respect to the substrate potential. Note that 8 is an insulating film.

The memory array of the EPROM element using this does not require connecting the source diffusion layer like the v, S line 3 shown in Figure 3. Therefore, the field regions 1 on both sides of the SS line 3 can be connected as shown in FIG.

This eliminates the need for the mask alignment margin.

Furthermore, the conventional aluminum wiring and contact holes for fixing the vss line potential are no longer necessary.

Note that when introducing B or sb, it is not introduced by ion implantation at a high acceleration voltage (but by ion implantation at a low acceleration voltage,
The heat treatment may be used to diffuse deeper than the source diffusion R3. In this case, the concentration of S and P in the source diffusion layer is set to B
What is necessary is to make it dark so that it can compensate for and sb.

Alternatively, a method may be used in which a P'' diffusion layer is buried in advance and an N'' diffusion layer is formed thereon.
It can be applied to the O3 process (PMO3 or well structure without any problems).

Although the above embodiments have been described with reference to EPROMs, it goes without saying that they can be easily applied to mask ROMs and other memory devices.

(Effects of the Invention) As described above, according to the present invention, a diffusion layer of the opposite conductivity type is provided below the source diffusion layer, a P''N' layer is formed, and the potential of the source diffusion layer is kept constant with that of the silicon substrate. Since the potentials are fixed at related potentials, the mask alignment margin L1 is not required, and the aluminum wiring and contact holes for fixing the vss line potentials are also not required.

Thereby, a highly integrated semiconductor memory device can be realized. This is particularly effective in EPROMs and mask ROMs, and if applied to 256-bit EFROMs, the device area can be reduced to about 90%.

[Brief explanation of drawings]

FIG. 1 is a plan view of one embodiment of the semiconductor memory device of the present invention, and FIG. 2 (11) and FIG. 3 is a plan view of a conventional semiconductor memory element, and FIG. 4 is a cross-sectional view taken along the line A-B in FIG. 3.
1 is a diagram illustrating a process of a conventional semiconductor memory device cut along a line; FIG. 1 field fiI region, 2... word line, 3... source diffusion layer, 4... floating gate, 5 contact hole, 6... bit line, 7 N'' diffusion layer, 8
...Insulating film, 9...Silicon substrate, 1o...P+ diffusion layer. Figure 1 Figure 2 Figure 3 Figure t1

Claims (1)

[Claims] In a semiconductor memory device structure in which field regions, word lines, bit lines, and floating gates are formed on a silicon substrate, and a source diffusion layer and a drain diffusion layer are formed on this silicon substrate, P^+N^ is formed below the source diffusion layer. A semiconductor memory element characterized in that a + junction is provided and a source diffusion layer is fixed at a substrate potential.