JPS6194158A - Control system of storage device - Google Patents

Abstract

PURPOSE:To improve cost performance by coupling close a high-speed IC memory to a main memory and managing the use condition of an IC file with a memory map to execute the data transfer control by a private microprocessor. CONSTITUTION:A main processor 21, a main memory 1, a file memory, and input/output control parts 21-1-21-n are connected to a common bus 31. The file memory consists of a large-sized RAM file 2. An address mapping decoder 3 is connected to the main memory 1, and this address mapping decoder 3 includes a circuit which defines the memory space of the main memory 1 as the combination of scattered areas on the RAM file 2. A microprocessor 4 controls data transfer passing the address mapping decoder 3 and a signal line 31-1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for controlling a storage device that accommodates memory files in an information processing device.

INDUSTRIAL APPLICATION This invention is utilized for the control method of the storage device in the information processing apparatus in which each device is path-connected.

[Conventional technology]

Conventionally, a circuit configuration as shown in FIG. 5 has generally been adopted as a circuit configuration of a small to medium-sized information processing device.

In FIG. 5, a main processor (CPU) 21, a main memory (MM) 1, and a plurality of input/output control units (IOCI~■0Cn) 22-1~2 are arranged on a common bus (C-BUS) 31.
A magnetic disk control unit (DKC) 23 that controls the magnetic disk drives 2-n and a magnetic disk device (DK) 24 is connected thereto.

In this storage circuit configuration, at the time of initial program loading, program modules and data resident in the main memory are read from a predetermined area of the magnetic disk drive 23 and stored in the main memory 1.

The memory capacity of the main memory 1 is usually determined based on the addressing ability of the main processor 21, memory cost, etc.
A memory capacity that is equal to or smaller than the actual addressing capacity of the main processor is set. Programs and data that cannot reside in the main memory are stored in the magnetic disk device, and are rolled in or out between the main memory and the magnetic disk device whenever necessary.

In particular, the virtual memory type has a very large virtual address space, with 5.
A relatively small data unit of 128 or IKB (hereinafter referred to as
It's called a page. ), this page is frequently replaced.

[Problem that the invention seeks to solve]

However, magnetic disk devices require a long time to access, and small fixed disk devices have an access time of 20 to 30 minutes.
It takes 100m5. Therefore, such a required time value becomes a very large drawback for requests for high-speed page replacement.

In order to solve this drawback, the present invention aims to provide a storage device control method that can be constructed economically with high performance.

Furthermore, according to the present invention, in a small-scale information processing device,
The aim is also to realize a large-capacity memory system that does not require fixed disks.

[Means for solving problems]

The present invention has a main processor, a main memory, a file memory, and an input/output control unit, and these are connected to one common bus, and the control means reads the contents of the file memory and transfers it to the main memory for use. In a control system for a storage device, the file memory is configured with a large RA, M, and a signal separate from the common bus that connects the main memory and the file memory and can transfer data at high speed is provided. an address mapping decoder connected to the main memory; and a microprocessor separate from the main processor and configured to control data transfer via the address mapping decoder and the signal line, The mapping decoder is characterized in that it includes a circuit that defines the memory space of the main memory as a combination of discrete areas on the file memory.

Preferably, the file memory includes an auxiliary battery for retaining its memory contents even when its main power source is disconnected.

[Effect]

The storage unit has a RAM file structure constituted by an IC memory, and this storage unit uses an address mapping decoder to map a spatial portion inside the storage unit to each data unit, that is, page, stored in the main memory. In addition, since the storage section is connected so that it can be accessed via a common bus, the storage section of the information processing device can be accessed from the magnetic disk that is often used in conventional devices. It is possible to use static RAM, which has significantly higher speed.

〔Example〕

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of the above embodiment. In this figure, a main processor 21, a main memory 1, a RAM file 2 serving as a file memory, and n input/output control units 22 are shown.
-1 to 22-n are connected to the common bus 31.

The RAM file 2 is composed of a large static RAM, and as a control means for reading out the contents and transferring it to the main memory 1 for use, (1) the above-mentioned common method for transferring data at high speed between the main memory 1 and the RAM file 2; A signal line 31 different from the bus is provided, and (2) an address mapping decoder 3 connected to the main memory 1 and (3) data transfer via this address mapping decoder 3 and the above signal line 31-1. (4) The address mapping decoder 3 includes a circuit that defines the memory space of the main memory 1 as a combination of discrete areas on the RAM file 2. .

The above are the features of the present invention, and since the RAM file 2 is composed of a group of static RAM elements as described above, the memory contents are retained in case the main power of the entire storage device is cut off. An auxiliary battery 30 is provided.

In addition, the microprocessor 4 interprets and executes transfer commands issued from the main processor 21 between the main memory 1 and the RAM file 2, processes a specified number of retries in the event of a read error, processes errors, and notifies the main processor 1 of interrupts. It controls the

FIG. 2 shows a circuit diagram of the memory device of this embodiment. Second
In the figure, main memory 1 is a 256 Kb dynamic R
The RAM file 2 is composed of a 256 Kb static RAM, which has a capacity of 5 Mb, and is buffered up by the auxiliary battery 30 in the event of a power outage. Both the main memory 1 and the RAM file 2 have a parity change function in units of hides.

As shown in Figure 3, the main memory and RAM files are IKb
Unit logical pages P o , P + ,”----
-'-P, 1 and address mapping decoder (M
AP), and one page is the unit of transfer between the main memory and the RAM file. In the example shown in Figure 3, Po and P+ in the main memory are p in area O of the RAM file.
o・0, po・1, P2, P3 are Pl・1 of area 1
．． Pi・2, P 1021, P4O10 is Elijah's P
The data of the RAM file is loaded into the main memory as 3.1021 and P3.1022, and the relationship between the main memory and the RAM file is clarified by the address mapping decoder.

FIG. 4 is a diagram showing the structure of the address mapping decoder, and shows the area address (A) of IMb in the RAM file.
,. ~A, 2), page address in area (A I
o = A Iq ) and a page valid (PV) bit indicating whether the page is valid/invalid, and an on-memory (ONM) bit indicating that the page resides in the main storage, i.e. in main memory or a RAM file. It consists of a disc libter consisting of a page control pin of bits, one disc libtar is allocated for each page of main memory, and a page valid bit and an on-memory pin are used to indicate an invalid page, that is, a page that does not exist in this storage device. Detect that has been accessed.

Next, data transfer between the main memory and the RAM file will be explained.

The table shows an example of commands related to transfer between the main memory and RAM files. By issuing commands and parameters from the main processor, the microprocessor 8 in the circuit will interpret them and create a transfer path between the main memory and RAM files. MM-RF path) 31-1 executes data transfer at high speed.

When the command operation is completed, the completion status is written to the status register 10 and an interrupt (INT) is generated to the main processor. GETI and PUTI are used to update the memory map when changing the correspondence between the main memory and the RAM file (for example, when a task that does not exist in the main memory is activated and requires a program in the RAM file). GET2 and PUT2 do not update the current memory map, but reload fixed data or R the processed data.
It is used when storing data in the data pool area within an AM file.

In addition to this, of course, commonly used memory clear commands, diagnostic commands, etc. are provided.

Next, a case will be described in which the RAM file is accessed from outside the storage device according to this embodiment.

The RAM file can be accessed by a circuit having a demand address (DMA) of the main processor or any of the input/output controllers 22-1 shown in FIG.

In this case, first, the area address register (
AR), set a specific area number, and then set the common lotus 3
1, turn on the RAM file select signal (RFS). As a result, the path between the main memory and the RAM file is separated, and data transfer is executed between the RAM file and the external circuit using the common bus addresses AB19-0 and data buses DB15-0. - As mentioned above, the main memory and RAM file can be accessed independently, so a RAM file select signal may be generated from the external demand address circuit during transfer between the main memory and the RAM file. For this reason, a contention control circuit 15 is provided, and RAM file selection is not permitted during transfer between main memory RAM files.

Next, the functions realized by the microprocessor (μp) 4 are: (1) Command interpretation and execution and termination processing.

■ If a parity error is detected during transfer between main memory RAM files, a retry operation is automatically performed from the address where the error occurred, and if the read is successful after the retry, the transfer continues without notifying the main processor of the error. Execute. Conversely, if an error occurs again at the same address, the transfer is stopped, an error status is prepared, and an interrupt notification is sent to the main processor. By performing the retry operation in this manner, it is possible to relieve random errors in the memory and increase the reliability of the memory system.

■ Detects battery voltage drop and notifies interrupt (BATA
LM function).

■ Function to refresh main memory.

■ Function to dummy access and initial clear the main memory using the initialize signal (INLZ).

■ Features include detecting page invalidity and page absence and notifying the main processor.

Note that the above functions can be achieved by combining discrete ICs, but by using the microprocessor 4, H/W1 is reduced and additional functions such as an error retry function can be easily achieved.

Next, comparing the performance of the conventional storage circuit system with fixed disk shown in FIG. 5 with that shown in FIG. Average seek time + average rotation waiting time (20ms-
100ms) (approximately 8m5) → IKb data transfer time (0.6 to 1.2 as /b) + command analysis completion processing time (approximately 400μs) Therefore, TI#29 to 109rns On the other hand, in the case of the present invention, MM-RF The transfer rate between is 0.
This can be achieved at 5 μs/2b.

T2=Command analysis completion processing time (approximately 300 as) +I Kb data transfer time (0.25 μs/b) Therefore, Tz =550 ps =0.55 m5 Therefore, approximately 50 to 200 times higher performance can be achieved. The larger the amount of data to be transferred, the better the transfer efficiency will be.

Moreover, in terms of reliability, there is not much difference between the two, and in terms of price, although this example is currently a little more expensive, if you compare the total cost including the disk controller and power supply circuit, there is not much difference. .

Furthermore, if we take into consideration the possibility that the price of 256 Kb static RAM will fall and IMb static RAM will be put into practical use in the future, it is expected that an even larger capacity storage circuit control system with IC file will be realized economically.

RAM files require an auxiliary battery to retain data, but if a primary battery with a capacity of about 10Ah is used, the replacement inspection cycle will be about one year, and if a disparity alarm detection function is added, battery maintenance work can be reduced. This is done without any practical inconvenience.

Furthermore, performance can be improved by adopting the storage device control method of the present invention and placing frequently used programs/data on IC files according to business programs even in information processing devices having large-capacity fixed disk devices. What is possible is clear from the above explanation.

〔Effect of the invention〕

As explained above, according to the present invention, a high-speed IC file is tightly coupled with the main memory, the usage status of the IC file is managed by a memory map, and data transfer control is executed by a dedicated microprocessor, thereby achieving cost performance. This has the effect of providing an excellent storage device control method.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention. FIG. 2 is a circuit configuration diagram of the storage device of the above embodiment. FIG. 3 is an explanatory diagram of the functions of the map. FIG. 4 is an explanatory diagram of the disc libter in the map. FIG. 5 is a block diagram of a conventional example. 1...Main memory, 2...RAM file, 3...
Address mapping decoder, 4... Microprocessor, 5... Read-only memory, 6... Map address register, 7... RAM file address register, 8... Page count register, 9... Command Register, 10...Status register, 1)...
・Area address register, 12...Multiplexer circuit, 13...Memory control unit, 14...Input/output controller control, 15...Conflict control circuit, 16...Command/RAM file transfer control unit, 17...Error control unit, 18...Interrupt initialization control unit, 21...
- Main processor, 22-1 to 22-n... Input/output control unit, 23... Magnetic disk control unit, 24... Magnetic disk, 30... Auxiliary battery, 31... Common bus, 3
1-1...Main memory/RAM file dedicated bus, BA
TALM...Battery voltage drop signal, INLZ...Initialize signal, INT...Interrupt signal, RFS...
・RAM file select signal.

Claims (2)

[Claims] (1) A main processor, a main memory, a file memory, and an input/output control unit, all of which are connected to a common bus, and a controller that reads the contents of the file memory and transfers them to the main memory for use. a signal line separate from the common bus that connects the main memory and the file memory and can transfer data at high speed; an address mapping decoder connected to the main memory; and a microprocessor that controls data transfer via the address mapping decoder and the signal line and is separate from the main processor; . A control method for a storage device, comprising a circuit that defines a memory space of the main memory as a combination of discrete areas on the file memory. (2) Even if the main power to the file memory is turned off,
A control system for a storage device according to claim (1), which includes an auxiliary battery for retaining the memory contents.