JPS6191690A - image display device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides sequential reading of image data stored in a memory.
The present invention relates to an image display device that displays images on a RT, and particularly to an image display device that can display image data stored in a plurality of different memories on a CRT in any relative positional relationship.

In recent years, with the development of data communication using Office Automation 7171 images, the form of images displayed on CRTs has shifted from displaying characters to displaying figures containing characters, and more sophisticated displays are being sought.

One of these display forms is the display of moving figures.

In conventional display devices, a software method using a computer is used to move the display position of a figure. However, moving figures using software not only places a heavy burden on the combiator, but also slows down the movement speed of figures due to the limits of the comviator's processing capacity. Processing such as moving only the data has the disadvantage that the software becomes complicated.

An object of the present invention is to eliminate the drawbacks of the conventional art and to provide an image display system that enables rapid movement and display of figures, and that allows multiple images to be superimposed and displayed in any relative positional relationship without complicating software. There is a particular thing.

In order to achieve the above object, the present invention provides a display address generating means, at least one first display image storage means receiving a first display address generated from the display address generating means, and a first display It has at least one display address converting means for inputting an address and at least one second display image storage means for inputting a second display address supplied by the display address converting means, The first image data read from the first display image means and the second image data read from the second display image storage means are displayed in a superimposed manner in an arbitrary relative positional relationship. 1, wherein the display address conversion means has an address data holding means, a calculation means, and an image data display restriction means, and the display address converting means converts the first display address and the value of the address data holding means by the calculation means. A second display address is generated by the calculation, and when the second display address in the image data output restriction circuit becomes a value outside the address range designated by the image data output restriction circuit, the second display address is generated. The second percentage point is that display of image data can be prohibited.

The present invention will be explained below with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, 1 is an oscillation circuit, 2 and 3 are frequency dividing circuits, 11 is a first memory, 12 is a second memory, 21 is a horizontal address register, 22 is a vertical address register, 24 is a horizontal address adder, and 25 is a vertical address register. an address adder; 31 is a first image display area limiting circuit; 32 is a second image display area limiting circuit;
G1 and G5 are AND gates, and G2 is an OR gate.

In the embodiment shown in FIG. 1, there are two sets of memories, memory 11 and memory 12, and image 1 read from memo 1 and image 2 read from memory 12 are superimposed and transferred to a CRT.
It is an image display device that can display on the top, and image 1 is 256
Image 2 has a size of 128 x 256 pixels.
It has a size of 12B pixels.

In particular, image 2 has a function that allows its display position to be changed according to the values of register 21 and register 22.

The frequency of the reference clock generated by the oscillation circuit 1 is divided by the frequency dividing circuit 2 and the frequency dividing circuit 3, and the first horizontal display address H1 is obtained from the frequency dividing circuit 2, and the first vertical display address r1 is obtained from the frequency dividing circuit 3. . Below is the first horizontal display address H1
When the first vertical address V1 is collectively referred to as the first display address H1.rl. Make a note of the first display address H1/rl! 711&C is directly supplied to this first display address H1
- Read the first image data D1 from the memory 11 using rl and display the image 1. On the other hand, the first horizontal display address H
1 is the horizontal register 2 in the horizontal address adder circuit 24.
The first vertical display address V1 is added with the value of the vertical address register 22 in the vertical address adding circuit and converted to the second vertical display address r2. Second horizontal display address H2 and second vertical display address r2 obtained here
is supplied to the second image display area limiting circuit 32 and the memory 12 and is used as an address for reading out the second image data D2 stored in the memory 2. The second image display area limiting circuit 52 is a circuit that outputs a signal that defines a period for outputting the second image data D2, and the second horizontal display address is 1.
A signal is output to open the AND gate G5 during a period in which the second vertical display address takes a value from 128 to 255, and during this period the second image data D2 passes through the AND gate G3 (or game) G2. The image data D1 is superimposed on the first image data D1 read out from the memory 11. The first image display area limiting circuit 31 has a first horizontal address of 0 to 255.
, and the first vertical address is a value between 0 and 255, a signal is output to open gate G1, and during this period, image data D1 and image data D2 superimposed on it pass through AND gate G1 and are output to the CRT. displayed above. The table (α) below shows the relationship between the first horizontal display address H1 and the second horizontal display address H2, and the table below (Al shows an example of the relationship between the first vertical display address r1 and the second vertical display address V2).

(Left below) Ship (hl In this example,
The horizontal address register 21 is set to 40 (28), and the vertical address register 22 is set to 100 (64) 1@, and the value of the second horizontal display address H2 is the first
The value of the horizontal display address H1 is set to the horizontal address register 21.
It is the value obtained by adding the direct 40 (28) rs of
The value of vertical display address r2 is the first vertical display address r1
The value of the vertical address register 22 is 100 (64),
The value is the sum of The first step is to display the image on the CRT.
If the value of horizontal display address H1 is 0 to 255 and the first
This is performed during a period in which the value of the vertical display address r1 is 0 to 255, and during this period, image 1 is displayed on the CRT, and in image 2, the value of the second horizontal display address H2 is 128.
255 and the value of the second vertical display address V2 is 128 to 255, C is superimposed on image 1.
In the example in Table 1, image 2 is displayed on RT, so in the example of Table 1, image 2 changes to image 1 during the period when the value of the first horizontal display address H1 is 88 to 215 and the value of the first vertical display address V1 is 28 to 155. The images will be superimposed and displayed on the CRT. FIG. 2 shows an image displayed on the CRT in this example. The coordinates in FIG. 2 represent the value of the first horizontal display address H1 in the horizontal direction, and the value of the first horizontal display address H1 in the vertical direction.
Represents the value of vertical display address V1, (horizontal coordinate.

Vertical coordinates). In Figure 2, 25
The image with a size of 6 x 256 is image 1, and 1
An image with a size of 28 x 128 is image 2,
The display position is the first one when the image data 2 is read out.
Horizontal coordinates 88-215.corresponding to the horizontal display address H1 and the first vertical display address V1. Vertical coordinates 28-155
becomes. In the example shown in the table and FIG. 2, the value of the horizontal address register 21 is 40 and the value of the vertical address register 22 is 40.
Although the value of 1 is set to 100, this value can of course be set to any value. With respect to the display position of image 1, image 2 can be displayed in the horizontal direction by changing the value in the horizontal address register 21, and in the vertical direction by changing the value in the vertical address register 22. can.

As described above, according to this embodiment, by changing the values of the registers 21 and 22 for image 1 having a size of 256 x 256 and image 2 having a size of 128 x 128, images can be displayed in any relative positional relationship. There is an effect.

In the example described above, two images, image 1 and image 2, were displayed, but the number of memories was increased according to the number of images to be displayed. By increasing the number of registers, adder 9 image display area limiting circuit, AND gate, and OR gate.

Alternatively, the present invention can also be applied to an image display device that displays two or more images by using them in a time-sharing manner.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the image display device according to the present invention, and FIG. 2 shows the image display device shown in FIG.
FIG. 3 is a diagram showing the relationship between images displayed on RT. 1: Oscillator circuit 2, 5: Counter 11.12:
Display image memory 21.22: Data address register 24.25:
Addition circuit 52: Image display area limiting circuit

Claims (1)

[Scope of Claims] 1. A display address generating means, a first display image storage means receiving as input the first display address generated from the display address generating means, and a display address receiving the first display address as input. A first image read from the first display image storage means, comprising a conversion means and a second display image storage means inputting a second display address output from the display address conversion means. An image display device characterized in that data and second image data read from the second display storage means are displayed in a superimposed manner in an arbitrary relative positional relationship. 2. The display address conversion means has an address data holding means, a calculation means, and an image data display restriction means, and the calculation means calculates the first display address and the value of the address data holding means. The image data output limiting means generates a second display address, and when the second display address has a value outside the address range specified by the image data display limiting means, the image data output limiting means stops displaying the second image data. The image display device according to claim 1, wherein the image display device is prohibited.