JPS6190400A - Mos type memory module - Google Patents

Abstract

PURPOSE:To have chips detect by themselves whether a bonding connection of commonly connected terminals is good or bad by inserting a MOSFET, to which a diode is connected, between terminals independently used per chip and those commonly connected, at each memory chip. CONSTITUTION:An external terminal for package, which is connected by wire bonding to an independent-use input terminal 121 of a memory module 111, etc., is grounded,and the independent-use input terminal 121 of the other module 11n is brought into a released state. Then a DC voltmeter 44 and DC ammeter 45 are connected to the external terminal for package which is connected by wire bonding to a commonly connected input terminal 122 to be checked. A DC voltage is impressed on the interval between terminals 121 and 122, provided that said voltage is the same as the threshold voltage of an FETQ3, to which a diode is connected, or higher than that, or the same as the threshold voltage of an FETQ1 of an input protection circuit or lower than that. Then the ammeter 44 and voltmeter 45 detect whether the DC current flows or not, and the chips can detect by themselves whether the bonding connection of commonly connected terminals is good or bad.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention is directed to accommodating a plurality of MOS ljl (insulated date type) memory integrated circuit chips in a single cage, and connecting each chip to an address input terminal. The present invention relates to a MOS type memory module in which chips are connected in parallel to operate each chip simultaneously, and particularly relates to an input circuit section of each chip.

[Technical background of the invention]

Recently, for the purpose of improving the packaging density of memory ICs in memory IC application systems, memory modules (for example, 64KX4 pit configuration) has been developed. This memory module (hybrid memory) includes a plurality of memory chips 11 to 1n having the same configuration as shown in FIG.
It is housed in t-1 packages, and some of the input terminals (ponding pads) of each memory chip (address terminals, chip control terminals) are commonly connected between chips to correspond to 74 chips. Connected to external input terminals (address terminals, read/write terminals). In addition, the signal terminals (data input terminals and data output terminals in the case of random access memory) used independently for each memory chip 11 to 1n are individually connected to the corresponding external terminals (data input terminals DIo-DI) of the package sensor.
, , data output terminals Doo-DOj).

FIG. 4 shows conventional MOS type memory chips 401 to 40.
This figure shows a test state described later for memory monoyl using a memory monolayer, in which each chip has a plurality of input terminals 41. ...
and an input terminal 41. An input protection circuit 43 is provided to protect an input dirt circuit 42 such as an inverter that receives signal input from . This input protection circuit 4
3 usually includes protective resistors R, , R, an N-channel enhancement type MOS FIIET (field effect transistor) Ql, and a diode-connected N-channel enhancement type MOSFET Q 2 with the date and source connected to each other as shown in the figure. It consists of

[Problems with background technology]

By the way, in the manufacturing process of memory monoyl as described above, it is necessary to detect and replace defective chips.
As one of the test processes, the memory chip f1. It is necessary to check whether the wire ending connection between each of the terminal groups .about.1n and the package external terminals is well established (ending open state). in this case,
For the signal terminals used independently on each chip, by connecting a DC voltmeter and a DC ammeter to the corresponding /4' cage external terminals, the quality of the bonding connection can be determined based on whether or not current flows through the terminals. It is possible. On the other hand, regarding the input terminals 41 that are commonly connected between chips as shown in FIG. Input terminal 4 of one chip (multiple chips) is defective due to a Dending defect, and input terminal 4 of the remaining chips
When the sounding condition of No. 1 is good, current flows to the input protection circuit 43 through the good input terminal 41, so it is difficult to detect the presence or absence of the defective binding chip and to detect the defective chip. Therefore, in order to analyze the bonding failure mode of the chip input terminal, a lot of effort was required, including a visual check using a microscope, etc., and it was impossible to automate the analysis. Also, it is possible to detect a defective chip by performing a functional test on the chip, but is it a malfunction of the chip itself or the terminals mentioned above? It was difficult to determine whether the terminal connection was defective or not.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and includes an external input terminal of a device in which a plurality of MOS memory chips are housed with predetermined input terminals commonly connected to each other and the commonly connected input terminal. The object of the present invention is to provide an MO3 type memory module that can easily detect for each chip whether or not the electrical connection with the chip is in an open state.

[Summary of the invention]

That is, the MO3 type memory monole of the present invention has a MOS transistor in each memory chip, which is diode-connected between all terminals that are commonly connected between the chips and at least one terminal that is used independently for each chip. type FET
It is characterized in that all the parts are inserted and connected.

As a result, when performing a chip terminal bonding quality test, all terminals of one chip 6 are subject to check, and their independently used terminals are connected to a predetermined potential terminal, while the independently used terminals of each of the remaining chips are left open, and By applying a predetermined DC voltage to the commonly connected terminals, the presence or absence of a current path can be determined depending on the bonding quality of the common connection terminals to be checked in the chip to be checked. This makes it easy to test the binding quality.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

In Figure 1, 111 to 1 are MOS type memory chips used in some parts, for example R.
AM chip), and each chip's signal terminal (9)
12t r 12z *...128. °“・12m
Some of them (address input terminals, tick control terminals) are connected to the corresponding terminals 122 of each chip, . . . terminals 12 . Comrades are commonly connected. This commonly connected terminal group is connected by wire bonding to the corresponding external terminal for Gufuke-2, and the terminals used independently for each chip (data input terminal 121 and data output terminal (not shown) ) are wire bonded to the corresponding external terminals for each of the 9 pieces.

In each of the above chips 111 to 11n, the fourth
As described above with reference to the figure, the input f-) circuit 42 is connected corresponding to the signal input terminal, and the input protection circuit 4
3 is provided.

Furthermore, in the present invention, each of the above chips 111 to 11
n each, each input terminal 122 .n is connected in common between the chips. ...12. A diode-connected N-channel enhancement type M in which the drain and y-t are mutually connected between the input terminal 121 and the independently used data input terminal 121.
OSFETQa 2>E Insertion connected. In this case, the threshold voltage vTH3 of the FETQs is equal to the threshold voltage vTH1 of the FETQt in the input protection circuit 43 (approximately 25V if total)! voltage is also a sufficiently low value (for example, about 15v).
), and the reason for this will be explained in the explanation of the operation in the bonding pass/fail test below.

When manufacturing the above memory monole? In the testing process before testing? /D/G pass/fail test.

As part of this test, the commonly connected input terminals (for example, 122) of each of the chips f111 to f11n are sequentially checked for each chip. In other words, input terminal 1 for independent use in one chip f111 to be checked.
I? wire bonded to 21? The external terminal for tsukeno is grounded, the input terminal 121 for independent use in the remaining chips is set to the open state, and in this state, the external terminal for tsukeno is connected by wire bonding to the commonly connected input terminal 122 that should be checked. DC voltmeter 4
4 and a DC ammeter 45 are connected to this external terminal, and whether the threshold voltage of the FET Q3 (7) is higher than vTH1':) F'
ET Q t (7) Apply a predetermined DC voltage lower than the threshold voltage V□1. As a result, the input terminal 122 to be checked in the chip 11□ to be checked is checked. If the grounding connection is good, the DC ammeter 4
5 -> the input terminal 122 -> FETQs -> independently used input terminal 121 -> A current flows through the path of the ground terminal (note that at this time, the FET Ql of the input protection circuit 43 is in a non-conducting state because the applied voltage is low). the above? If the terminal connection is open, no current will flow through the above path. Such electrical testing allows chip-by-chip testing of each commonly connected input terminal. It is possible to easily detect whether the terminal connection is good or bad, and it is possible to easily and quickly analyze chip failures.Is it a malfunction of the chip itself? Since it is possible to easily determine whether there is a defect in the manufacturing process, it is possible to shorten the manufacturing process.

In the above embodiment, the input terminals 12 and 12 for common connection on the chip and the input terminals 2 for independent use
FE connected with a diode between input terminal 121
TQ3 was inserted respectively, but instead of this, as shown in FIG. 2, input terminals 122 . Even if a diode-connected FETQa is inserted between the data output terminal 12i and the independently used data output terminal 12m, the same effect as in the above embodiment can be obtained.

In FIG. 2, 13 is an output buffer circuit connected to the data output terminal 12m, and 44 and 45 are a DC voltmeter and a DC ammeter, respectively, for testing the quality of the binding as described above.

Furthermore, if the memory chip is a RAM chip, any of the above-mentioned embodiments may be adopted;
In the case of a (read-only memory) chip, the embodiment shown in FIG. 2 may be adopted.

〔Effect of the invention〕

As described above, according to the MOS type memory monole of the present invention, it is possible to easily detect the quality of the RF bonding connection of the terminals that are commonly connected between chips in each memory chip, so that the ability to analyze bonding failures can be improved and the manufacturing process can be improved. The process can be shortened.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a binding quality test state for an embodiment of the MOS type memory monoyl of the present invention;
FIG. 2 is a circuit diagram showing the test state of another embodiment, FIG. 3 is a diagram for explaining the correspondence between the human output signal of the memory monologue and each memory chip, and FIG.
The figure is a circuit diagram showing a bonding quality test state of a conventional MOSO8 type memory module. 111 to 11n...MOS type memory chips are 12. ~
12, rl...terminal, 42...input f-) circuit, 4
3...Input protection circuit, Q3...MoS FET. Applicant's Representative Patent Attorney Takeshi Suzue Syllable 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] A plurality of MOS type memory chips are housed in one package, and the terminal group of each chip includes terminals to which corresponding comrades of each chip are commonly connected and terminals used independently for each chip. In the MOS type memory module, each chip has a diode-connected MOS type FET inserted between all the commonly connected terminals and the at least one independently used terminal. Characteristic MOS type memory module.