JPS6188671A - Video signal decision circuit - Google Patents

Abstract

PURPOSE:To prevent abnormal state of a display picture by counting pulse number of the first video signal while a vertical synchronizing pulse signal through the count. CONSTITUTION:A composite synchronizing signal (a) separated synchronously from the first video signal being a major signal received by a TV receiver is inputted to a count input terminal 1 of a counter 3 and a vertical synchronizing signal (b) of the second video signal being an additional signal from a personal computer or the like is inputted to a reset terminal R of the counter 3 respectively, and the level at an output terminal QB is at an H level and the level of an output terminal QD is at an L level when the count number is within a prescribed range while no second video signal exists and an output terminal 4 goes to an H level. When the count is at the outside of the range, the level of the output terminals QB, QD goes to both L or H, the output terminal 4 outputs an L level so as to decide the presence or absence of the supply of the 1st video signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a video signal determining circuit, and more particularly to a video signal determining circuit that determines whether or not a video signal is supplied.

2. Description of the Related Art Conventionally, there have been video signal synthesis circuits for displaying superimposed images on television images. This video signal synthesis circuit is supplied with, for example, a main video signal received from a television broadcast, and an additional video signal from a personal computer, etc. that is synchronized with this video signal, and generates an additional video signal. is the period during which a character, figure, etc. is expressed.The main video signal is replaced with an additional video signal to obtain a composite video signal, which is then output.

When performing such superimposed display, the personal computer continues to output additional video signals at all times, but the television receiver that receives television broadcasts, for example, when changing channels, it outputs additional video signals from channels that are not being broadcast ( 5 channel, etc.), the main video signal cannot be obtained. Further, when a video tape recorder is used instead of a television receiver, the main video signal cannot be obtained if the video tape recorder is set to stop mode.

Problems to be Solved by the Invention Since in a composite video signal, only the period representing a character, figure, etc. is replaced by an additional video signal, the composite synchronization signal of the composite video signal cannot be obtained from the main video signal. It is something that Therefore, as described above, since there is no composite synchronization signal in the composite video signal when the main video signal is not supplied, there is a problem in that the display screen based on this composite video signal becomes abnormal.

Therefore, the present invention provides a video signal determination circuit that solves the above problems by counting the number of pulses of the main video signal during the existence period of the vertical synchronization pulse and determining whether or not the main video signal is supplied. The purpose is to

Means for Solving the Problems The present invention counts the number of pulses of the main video signal during the existence period of the vertical synchronization pulse, and determines whether the main video signal is within or outside a predetermined range. The presence or absence of supply is being determined.

In the present invention, the number of pulses of the main video signal during the existence period of the vertical synchronization pulse is counted, and this counted value becomes the main video signal which is approximately the same as the number of cuts in the vertical synchronization pulse of the main video signal. When a video signal is being supplied and the count value is different from the number of notches, it is determined that the main video signal is not being supplied.

Example FIG. 1 shows a circuit diagram of an embodiment of the circuit of the present invention.

In the figure, 1 and 2 are input terminals, and input terminal 1 receives the main video signal (first video signal) received by a television receiver or reproduced by a video tape recorder.
A composite synchronizing signal a as shown in FIG. Input terminal 2 also receives a vertical synchronizing signal b as shown in FIG. 2(B) of an additional video signal (second video signal) from the personal computer, or a vertical retrace signal as shown in FIG. 2(C). During this period, a non-interlaced composite synchronization signal C without equalization pulses is received,
The vertical synchronization signal or the composite synchronization signal C is supplied to the reset terminal R of the counter 3. Here, the personal computer is supplied with the same composite synchronization signal as that coming into input terminal 1, and the additional video signal generated by the personal computer is vertically and horizontally synchronized with the main video signal. It was taken.

The counter 3 is in a reset state when the signal supplied to the reset terminal R is at the H level, and counts the pulses that enter the counting input terminal after the reset is released while the signal at the reset terminal R is at the L level. 21 of counter 3 (
-2 represents the lower limit of the predetermined range) output terminal Q8 for output
The anode of the diode Dl is connected to 23 (
=8 represents the upper limit of the predetermined range) output terminal Ql for output
) is connected to the anode of the diode D2.

The cathode of the diode D1 is a protection resistor R connected in series.
+ is connected to the base of the transistor Tr+ via the resistor R2, and the connection point between the protective resistor R1 and the resistor R2 is connected to the capacitor C1, one end of which is grounded, and the other end of the capacitor C1, which is connected to the base of the transistor Tr+ via the resistor R2 and the capacitor C1. In contrast, an integrating circuit with a sufficiently large discharge time constant is constructed. Similarly, the cathode of diode D2 is connected to resistors R3 and Ra connected in series.
A capacitor C with one end grounded is connected to the base of the transistor Trz via
The other end of 2 is connected, and the resistor R4 and capacitor C2 constitute an integrating circuit with a sufficiently large discharge time constant for the vertical scanning period. The emitter of the transistor Tr+ is grounded, the collector is connected to the anode of the diode D3, and is supplied with power via a resistor R5. The base of the transistor Tr2 is connected to the above-mentioned diode 6-ode D3, the mitter is grounded, the collector is connected to the output terminal 4, and the resistor R is connected to the base of the transistor Tr2.
Power is supplied via 6.

Here, a case will be described in which a vertical synchronizing signal of an additional video signal is input to the input terminal 2. The counter 3 is reset from 1 to 1 during the existence period of the vertical synchronization signal 1), and counts the pulses a1 to a6 of the composite synchronization signal a. Therefore, the counter 3 outputs a pulse of 1-level from the output terminal Qe from the time the pulse a2 arrives until before the pulses a and I arrive, and there is no pulse output from the output terminal Qo.

Since the counter 3 is reset during periods other than wi 1-1, there is no level output from the output terminals Q[], QDJ:su]. The capacitor C1 is charged by the H level pulse output from the output ☆v11 child QB within the period Ti, the base of the transistor Tr+ is always at the H level, and the 1-transistor Tr+ is rendered conductive. Furthermore, since there is no pulse output from the output terminal QD, the capacitor C2 is not charged and the transistor Tr2 is non-conductive. Therefore,
An H level signal is output from the output terminal 4.

Next, a case where the main video signal cannot be obtained will be explained. This includes the first case where the synchronization separation input of the main video signal is short-circuited and the signal entering input terminal 1 is at a constant level of H or L, and the first case when the channel of the television receiver is broadcasting. is switched to a channel that does not have
Alternatively, there is a second case in which the video tape recorder is in stop mode and the synchronization separation input becomes white noise, and the signal entering the input terminal 1 is a random pulse with a high repetition frequency.

In the first case, since there is no pulse input to the input terminal 1 of the counter 3, the counter 3 does not perform a counting operation within the period Ti, and the output terminals QB, Ql) are always at the L level.

Therefore, capacitor C+.

C2 is not charged (, transistor Tr+
Since the transistor Tr2 is non-conductive, the transistor Tr2 becomes conductive. As a result, an L level signal is output from the output terminal 4.

In the second case, the counter 3 counts pulses with a random high repetition frequency within the period Tl, and the count value is "
8'', H level pulses are output from the output terminals Qe and Qo, respectively. Therefore, the capacitor C+ is increased by the H level pulses output from the output terminals Qs and Qo, respectively, within the period T1.

Each of C2 is charged together and the transistor Tr +.

Both Tr2 are conductive. When the transistor Tr2 becomes conductive, an L level signal is output from the output terminal 4.

In other words, when the main video signal is obtained, a 1" level signal is output from the output terminal 4, and when the main video signal is not obtained, an L level signal (binary) is output from the output terminal 4. ) is output.

The signal from this output terminal 4 is supplied as a switching signal to a video signal synthesis circuit (not shown), and the video signal synthesis circuit always takes out and outputs an additional video signal when the signal from the output terminal 4 is at the 1-level. do. As a result, when the main video signal cannot be obtained, additional video from the microcomputer is displayed on both sides of the monitor, thereby preventing the display screen from going into an abnormal state.

Next, when a composite synchronization signal C of an additional video signal is input to the input terminal 2, the circuit shown in the first diagram performs exactly the same operation as described above for the vertical synchronization signal period T1 of this composite synchronization signal C. , the explanation thereof will be omitted. In this case, in the second case where the main video signal is not obtained, random high-repetition frequency pulses coming from input terminal 1 are counted during the horizontal synchronization pulse period of composite synchronization signal C, and the output terminal QB and QD are each at a level of 1.

In other words, it is determined that the main video signal is not obtained even in periods other than the period TI, and the determination ability is improved.

Note that a blanking pulse or the like generated from the main video signal may be supplied to the input terminal 1, and the output signals of the output terminals QB and QD may be supplied to the input terminal 1 by using a latch circuit instead of an integrating circuit. It may be latched during the vertical scanning period, and is not limited to the above embodiment.

Note that the circuit of the present invention may be applied to circuits other than video signal synthesis circuits, and is not limited to the above embodiments.

Effects of the Invention As described above, the video signal determination circuit according to the present invention counts the number of pulses of the first video signal during the existence period of the vertical synchronization pulse, and determines whether or not the first video signal is supplied based on the count value. In order to determine whether or not the first video signal is supplied, it is possible to accurately determine whether the first video signal is supplied, and the circuit configuration thereof is simple and inexpensive. The second video signal, which is always stably present, is taken out by the above-mentioned combining circuit, so that an abnormal state of the displayed image can be prevented.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of one embodiment of the circuit of the present invention, and Fig. 2 is a circuit diagram of an embodiment of the circuit of the present invention.
FIG. 3 is a waveform diagram of signals supplied to the illustrated circuit. 1.2...Input terminal, 3...Counter, 4...Output terminal, C+, C2...Capacitor, D1-D3・
...Diode, R1-R6...Resistance, Tr+, Tr
2...Transistor.

Claims (2)

[Claims] (1) A second video signal that is synchronized with the first video signal and always exists stably.
counting the number of pulses of the first video signal during the existence period of at least the vertical synchronization pulse of the video signal, and when the counted value is within a predetermined range that includes the number of notches of the vertical synchronization pulse of the first video signal; A video signal determination circuit characterized in that it determines that the first video signal is supplied, and determines that the first video signal is not supplied when the count value is outside the predetermined range. (2) A circuit that determines whether or not the first video signal is supplied based on whether the counted value is within or outside the predetermined range indicates that the counted value has exceeded the lower limit of the predetermined range. The signal and the signal indicating that the counted value exceeds the upper limit of the predetermined range are each held in an integrating circuit with a discharge time constant exceeding one vertical scanning period, and the first 2. The video signal determination circuit according to claim 1, wherein the video signal determination circuit generates a binary signal representing whether or not the video signal is supplied.