JPS6188355A - Data processor - Google Patents

Abstract

PURPOSE:To prevent securely hang up by receiving directly an insertion request signal of the bus timing, which is generated from memory and I/O control circuit, and providing a weight control circuit for the insertion and control of the bus timing. CONSTITUTION:Receiving the 1st ready signal 8 from the I/O control circuit 8, a weight control circuit 15 immediately returns the 2nd ready signal 17 to a CPU1 and simultaneously starts counting the number of insertions of a timing bus Tw of the CPU1 through a timing line 16 of a bus cycle from the CPU1. When abnormality arises in the signal 8 and a low level continues, the insertion counted contents of the bus Tw are compared with the signal 8. If the low level of the signal 8 continues over a period when the number of insertions of the bus Tw permitted by the system is counted, a signal 17 is forcibly retuned to a high level to terminate the bus cycle, and the execution of the CPU1 is advanced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data processing device icB having a bus structure, which prevents bus hang-up caused by hardware failure. be.

[Conventional technology]

Conventionally, the path structure of this data processing apparatus was shown in FIG. In Figure 2, (1) is the central processing unit (hereinafter referred to as CPU), (2) is memory, (J is input/output music) 0@l production (hereinafter referred to as IOC), (hereinafter referred to as IO
The input/output equipment w connected to C(a), (hereinafter referred to as work 10), (5), (6), (7) and system t are connected to (8).
+r'+ l is a long-lasting element, and (δ) is memory (2
) and IOC (3) 17. + Address bus with redundant fingers,
(6) consists of CPU (1), memory (2) and engineering OC (8).
Data in 1 hour? Data bus for sending and receiving, (7) is cP
A strobe signal that U (1) gives to the memory (2) and the OC (31) to specify the data transmission/reception timing, (8)
, memory (2) and IOC (8) are c P U (1
) is the first ready signal for extending and receiving the first strobe signal. FIG. 5 shows that the data processing device shown in FIG.
2 is a timing chart showing the basic timing of data transmission and reception. Specifically, for example, Intel's CPU
Data processing device 1'I using 8086ffi? This path timing corresponds to VC. In the 6th evil (
9) U CPU (1) and 7'-E-li (2) and X
T between OCta1: This is the timing that defines the pass cycle' for transferring 1 byte or 2 bytes of data, and consists of 4 clocks from minimum T□ to T4. (1
0a), the inverse ratio period of the address, (11b)
A strobe signal (
% (12a) indicates the 1t1 period including the data to be sent and received in the exit period 1' of 7th.

As shown in Figure 6, there is a bus cycle in the memory (2) and the memory (OC<:3) where data cannot be transmitted or received in the minimum pass cycle consisting of M from T to T4. This shows the bus cycle when the bus cycle is extended. 03) is the bus timing inserted between Ic T3 and T4 to extend the pass cycle. (14a) ns CPU (1) is I
(Stimming Tw t- inserting t approving m
This is the first ready signal generated by the memory (2) or the CPU OC (81).
(1) increases the number of path timings Tw to be inserted.

Figure 7 shows that the Eribus timing Tw continues to be inserted due to a failure in the ready signal sending circuit of 1 memory (2) and the FC OC (81), and the bus cycle is not completed, resulting in a so-called bus pull-up. It shows the bus timing,
(10th, (11th, (120th address) respectively.

Strobe, indicating data continues, (14C)
7'c indicates that the low level signal from the memory (2) or IOC (31) continues abnormally.

Next, the operation of the above configuration will be explained. In this embodiment, the case where data is sent from the CPU (1) to the IOC (81) will be explained as an example.
) sends a strobe signal (7) that specifies the timing at which data on the data bus (6) is taken in.
8) cannot take in data in the minimum pass cycle (consisting of 4 clocks T□ to T), the first ready signal (8) immediately after receiving the strobe signal (7).
) Lowers k to low level and requests CPU (1) to insert bus timing Tw (13). 0 response series, the bus timing shown in Figure 6 Tw 0
3J is inserted from the CPU (1) Vc, and the address bus (
5) As the address (10a) above is the address (10b), the strobe signal (11a) is the strobe number 1 (
11b), the data (12) on the data bus (6)
a) are each extended rLl like data (12b)
In order for the engineering OC<3) to receive data safely,
A bus cycle is formed. In FIG. 6, %, (7, 1) is shown as an example where two bus timings Tw are added, but such TwO0U each memory (2), IOC (3
) is normally specified for each.

[Problem that the invention seeks to solve]

Conventional data processing devices are configured and controlled as described above, so that memory (2) or memory (A (8)
If a failure occurs in the first ready signal generation circuit on the side, the bus timing Tw changes to CPU(1)K as shown in
There is a problem in that the bus cycle is not terminated because F is continuously inserted, and it is not possible to recover from a system down due to a so-called path hang-up.

This invention was made in order to solve all the problems of the conventional ones as mentioned above, and it is possible to prevent the so-called hang amplifier of the path caused by the failure of the memory or the data processing. Vcli7 to prevent device system down
The object of the present invention is to obtain a data processing device that stops the data processing.

[Problem til! means to decide]

The data processing device according to the present invention includes a memory and an IOC.
A wait control circuit is provided to directly receive a bus timing insertion request and control bus timing insertion by directly receiving a bus timing insertion request.

[Effect]

The above-mentioned wait control circuit monitors the first ready signal from the memory and IOC, and if an abnormality occurs in the LDII and the low level continues to be 7'C, it forces the second signal to the CPU. The bus cycle is terminated and the bus hang amplifier is prevented from becoming VC.

〔Example〕

Same as in FIG. 4 showing the configuration of a conventional data processing device, corresponding parts are given the numerals 7'c and 1-, μs.
2 is the pass timing at which memory (2) and engineering QC (3) occur. That's what it means.

As shown in FIG. 2, the weight control circuit of 0) includes lead time signal receiving means (15a), means (15b,) for transmitting the bus cycle status of cPU (1), and timing path insertion. It has means (15c) for counting the number of timing buses inserted, and means (15d) for sending out a second ready signal for terminating the bus cycle when the number of timing bus insertions counted by this means is too large. . (16) is a timing line for transmitting the state of the CPU cycle of CPU (1) to the WTC (b));
αγ) receives the first lady number (8) from the memory (2) or IOC (13) and processes and monitors the fcWTC (15-2), and controls the bus so that it does not hang up.
This is the second ready signal sent to P U (1).

Figure 3 shows the pass timing when the above-mentioned WTCφ) operation terminates the bus cycle in a systematic manner and completely prevents the bus's 71-ng amplifier.
J indicates the second ready signal sent to WTC0J5JEngR)cPU(1) Next, the operation of the bus knocking amplifier prevention control according to the above configuration of the invention of 0 will be explained. Na. In addition, the case where data is sent from CPU (1) to IOC (a) at 2 in FIG. 1 will be explained as an example. So CPU (1)
At the same time as transmitting data to the data bus (6),
The IOC (a) sends out a strobe signal (7) that defines the timing at which all data on the data bus (6) is received.

If the entire data cannot be captured in the minimum bus cycle (consisting of 4 clocks from T□ to T4), the first ready signal (8) is immediately low after receiving the strobe signal (7 clocks). level and requests w'rc (to) to insert the path timing Tw (IIJ shown in Figure 5).Receive 1st lady old number (8) t'''fc
WTCCL5) converts this into a t-,42 ready signal (1η) and transmits it to CPU (1). Through this series of operations, the bus timing TwtJ mark shown in FIG.
1), and the address signal on the address bus (6) is like the address (10t1), and the strobe signal (
7) is (11d, l), data 4 on data bus (6) is extended as shown in (12d), and l0C
Extension of the pass cycle is started so that (3) can safely receive data 1g.

However, due to the failure of IOC (a), the low level of the second ready signal αq continues abnormally, and as shown in FIG. Next, the operation of the WTC (b) for preventing hang amplifiers on the Vcc bus will be explained. Figures 1 to 6 ice
0C (3) F. Luti No. 1g (8)
fcW T CC15), the second ready signal (1
'l) f CP T7 (CPU T7 at the same time as returning IHC
From (1), counting of the number of gods on the timing bus Tw09> of cPU (1) is started via the bus cycle timing line (16).

If an abnormality occurs in the first ready signal (8) and the low level continues at 7'C, it is constantly compared with the insertion number count of the upper timing path Twα3), and the timing path 7wQ3) that is acceptable in the system is Even if the first ready signal continues to be at a low level for a time exceeding the number of insertions, the second ready signal is forced to a no-y level to terminate the bus cycle and proceed with the operation of the CPU (1). Figure 6 shows the effect of the WTC residence 1c Ex 2nd ready signal 1.1 even if the old number 8 continues as in (14a).
7) is forcibly reverted to a high level like μs), indicating the end of the pass cycle.

2. In the above example, from CPU (1) to CPU Q Cj8
), but the case where data is sent to l0C(
8) to CPU (1), and from CPU (1) to memory (
2) and when transmitting data from the memory (2) to the cPU (1), the same effect as in the 8-pin embodiment can be achieved.

Further, although the number of insertions of path timing Tw is not specified, it is possible to set all the counter values in w'rc to any value according to system requirements.

〔Effect of the invention〕

As described above, if this invention is implemented, the hang amplifier of the bus caused by the delay of the μ memory can be eliminated by waiting.
This can be reliably prevented by monitoring and controlling the flow rate in the wholesale circuit, and prevents and prevents system failures in the data processing equipment.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a data processing device showing an embodiment of the present invention, Figure 2 is a block diagram showing the basics of the unit control path in the above device, and Figure 3 is a block diagram of a data processing device showing an embodiment of the present invention. FIG. 4 is a timing chart showing the completion state of a bus cycle by the device, and FIG. 5 is a block diagram of a conventional data processing device.
The figure is a basic timing chart of the minimum bus cycle for data transmission and reception, and Figure 6 is a t-pass cycle timing chart that is extended to push the bus timing Tw.
This is a timing chart in case the F-bus cycle cannot be completed due to insertion of abnormal bus timing rw. In Figure 2, (1) is the central processing unit, (2) is the memory,
(8) is an input/output control device, (4) is an input/output device, ψ is a weight control circuit, (15a) is a second ready signal receiving means, (151:+) is a bus cycle of l'X central processing unit. Status transmitting means, (15c) a timing bus insertion count hand ah (15ti) a second ready No. 15 sending means for terminating a bus cycle, α6) a timing line, and 07 a second ready signal.

Claims (1)

[Claims] It has a central processing unit connected to a bus, a memory that stores programs, data, etc., an input/output control device that inputs and outputs data, and an input/output device that is connected to this input/output control device. The data processing device controls the length of a strobe signal sent by the central processing unit when transmitting and receiving information between the devices, and transmits and receives information in accordance with the operation of the memory and input/output control device. The first bus timing insertion request generated by the control device
means for receiving a ready signal; means for transmitting the bus cycle status of the central processing unit; means for counting the number of insertions of the timing bus Tw of the central processing unit transmitted by the means; If the first ready signal continues to be at a low level for a period of time exceeding a predetermined number of inserted timing buses Tw, a second ready signal that is forcibly returned to a high level is sent to the central processing unit to restart the bus cycle. 1. A data processing device comprising: a weight control circuit having means for terminating.