JPS6184764A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device that determines the type of a connected microprocessor and performs an operation according to the type.

(Prior Art) Conventionally, a semiconductor integrated circuit that provides an interface between a central processing unit (hereinafter simply referred to as a CPU) and peripheral devices such as a keypad or display device is called a peripheral LS.
I devices (e.g. asynchronous communication adapter LSI, synchronous data communication LSI, asynchronous receiver/transmitter L
S11 Peri7 Eral Inter7 Ace Adapter, CRT
Controllers, etc.), and several types were commercialized depending on the type of CPU to be connected. This is because the types and contents of control signals differ depending on the type of CPU, and therefore the interface circuits built into the peripheral LSI devices differ. In order to manufacture peripherals I and SI according to the type of CPU, a method has been used in which interface circuits are switched υ by a master slice method.

However, in this conventional type, it is necessary to produce many types of peripheral LSIs for each type of CPU, which complicates the main arm process and reduces the production volume per glaze, reducing mass production effectiveness. However, there was an inconvenience that the unit price of each LSI device increased.

(Problems to be Solved by the Invention) In view of the problems in the conventional type described above, the present invention solves the problems of the CPU.
It is an object of the present invention to provide a peripheral LSI device that can be used regardless of the type of peripheral LSI device, simplify the design and production process of the peripheral LSI device, and improve quality and reduce the price.

(Means for Solving the Problems) In order to solve the above-mentioned problems, according to the present invention, the type of microprocessor connected to the microprocessor is determined based on the difference in the timing relationship of a plurality of control signals inputted from the connected microprocessor. It is equipped with a microprocessor search circuit for discriminating, and a plurality of interface circuits for exchanging control signals with each different type of microprocessor, and based on the output of the microprocessor search circuit, an interface circuit corresponding to the connected microprocessor is selected. A semiconductor integrated circuit device is provided which is characterized in that the selection is made.

(Operation) According to the present invention, by using the above-described means, the type of CPU such as a microprocessor connected to the LSI device in the peripheral LSI device is automatically determined and a corresponding interface circuit is selected. Ru. therefore,
If! It is possible to perform ink7ace between multiple types of CPUs and peripheral devices simply by using type i peripheral LSI devices.

(Example) Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 schematically shows a peripheral LSI device as a semiconductor integrated circuit device according to an embodiment of the present invention. The device shown in the figure includes a CPU search circuit 1 that determines the type of cpυ of a connected microprocessor, etc., an A type interface 2 and a B type interface 3 provided for each type of CPU to be read directly, and control register 4
Equipped with.

In the peripheral LSI device shown in FIG.
Control signals input from , for example, enable signal E or read signal RD, read/write signal R/W or write signal type, etc., are input to CPU search circuit l, which analyzes these control signals. Determine the type of connected CPU. and interface 2 or 3 corresponding to the determined type.
The interface is activated by inputting an enable signal to the interface. The activated interface creates a control signal based on each core number 0-Ai input from the CPU and applies it to the control register 4. The control register 4 receives, for example, 8-bit data Do from the data bus connected to the CPU in response to this resistor control signal.
,..., import D7 or transfer the data in register 4 to the CPU. Through such a procedure, the control register 4 is initialized, and based on the contents of the control register 4, a well-known interface operation between the CPU and a peripheral device (not shown) is performed.

By the way, the types of CPUs currently on the market are broadly divided into two types: those manufactured by Motorola, Inc. in the United States, and those manufactured by Intel, Inc. in the United States. These two systems of CPU differ in the format and timing of control signals related to peripheral LSI devices. The peripheral LSI device according to the present invention detects the difference in timing of these control signals and performs switching between A/7 and Ace.

! Figure 2 shows the waveforms of control signals in a Motorola-based CPU (for example, referred to as a human-type CPU) and an Intel-based CPU (for example, referred to as a B-type CPU). There are 38 types of control signals for the A type CPU K, such as the enable signal E1 chip select signal cs, and the !J-dried signal R/W. As shown in (b), the chip select signal C8, !/- code signal RD
There are three types: , and write signal type.

Extracting the characteristics of each of these control signals for each type of t-CPH, first of all, in the A type CPU, (1) the read/write signal R/W is in the write mode, that is, during the "L" level period, the enable signal E is Includes a period of H# level, that is, the read/write signal R
Both the enable signal E and the read/write signal R/W are at the L'' level while the fall of /W is at least about 20 nM- from the edge.

(2) Data is read on the falling edge of enable signal E.

Furthermore, in the B type CPU, (1) the read signal RD and the write signal ■ do not become active 1L' at the same time.

(2) Data is read when the write signal WT rises to the 9th edge.

Analyzing the characteristics of such control signals reveals that CP
In order to determine the type of CPU at the beginning of the so-called write cycle in which U writes control data to the control renostar in the peripheral LSI device, it is necessary to determine the nature of (1) for the A-type CPU and (1) for the B-type CPU. It turns out that we can take advantage of the differences in their properties.

FIG. 3 shows an example of a CPU search circuit that determines the type of CPU using such a difference in properties.

The circuit in the figure consists of a slip-flop 7 with NOR gates 5 and 6, a NOR dart 8 and an inverter 9 connected to the inputs of the flip-flop 7, and a 1M goo whose output is connected to the A-type interface 10. -1.
10-2.10-4. Gate 11-1.11-2.11-4 after the output is connected to ink 7 ace for B type
, Furi, f71:i y7'70 output each AND coo
) Inverters 12-1.12-2.12 connected between the inputs of 10-1, 10-2 and 10-4, respectively.
-4t- equipped.

One input of each gate 11-1.11-2.11-4 is directly connected to the output of the flip-flop l=i, 7''7. Also, Andoo) 10-1 and 11-1
．． The other inputs of 10-2 and 11-2, 10-4 and 11-4 are control signal terminals TI, T2. Connected to T4. Also, T
Reference numeral 5 denotes a terminal to which a reset signal RE8 is applied, which is connected to the input of the inverter 90, and may be created by an internal circuit depending on the purpose of the peripheral LsI.

When a peripheral LSI device including the circuit shown in FIG. 3 is connected to, for example, an A-type CPU, each control signal terminal TI, T2 . A read/write signal R/W, an enable signal E, a preselect signal C8, and a preselect signal C8 are applied to T4, respectively. Also, if a B type CPU is connected, each terminal TI.

T2 and T4 respectively receive write signals WT, ! A J-mode signal RD and a chip select signal C8 are applied.

When initializing the peripheral LSI device, the reset signal RES at the terminal T5 is temporarily set to the L" level, and a signal at the "H" level is applied to one input terminal of the NOR gate 6 of the flop 7. .), clip 70 tube 7
That is, the output of the NOR gate 5 becomes H" level. Therefore, the output of the ANDr gate 11-1.
H” level IJ is applied to one input of 1-4,
Each control signal terminal T1. T2. T4 is B
Connected to the type interface. That is, the third
The circuit shown in the figure is initially in a state corresponding to a B-type CPU. Then, the peripheral L including the circuit shown in FIG.
When the SI device is connected to A-type CPU K, there is a period during which the read/2 write signal R/W and enable signal E applied to control signal terminals 1 and T2, respectively, are at the 'L' level at the same time. Therefore, the output of NOR gate 8 becomes H” level, and gate 7
The output of 0tsug7 is set to t-"L" level. Therefore,
A high level signal is applied to one input of the AND DIRT 10-1.10-2.10-4, and the control signal terminals Tl, T2. T4 is connected to the A type interface. That is, in the write cycle during initial setting, it is detected that the signals at the control signal terminals T1 and T2 reach the 'Lm level at the same time, and the peripheral peripheral device is set to a state compatible with the A-type CPU.

FIG. 4 shows another example of the CPU@%2 circuit. The circuit shown in the figure uses inverters 13, 14, a NAND gate 15, and an inverter 16 in place of the NOR gate 8 in the circuit shown in FIG. The inverter 14 is a high-resistance inverter (an inverter that falls slowly at 9 and rises quickly at 9) and has a larger output impedance than other inverters, so that the signal delay time becomes longer. It was made by With this configuration, the rise of the enable signal E applied to the control signal terminal T2 delays the timing of the read/write signal R.
The longer the time that /W and the enable signal E are both at a low level, the more securely the flip roller f7 is set. Other operations are the same as those of the circuit shown in FIG. 3, so explanations will be omitted.

(Effects of the Invention) As described above, according to the present invention, it is possible to handle multiple types of CPUs with one type of peripheral LSI device. It is possible to improve quality and reduce unit price.

[Brief explanation of the drawing]

FIG. 1 is a partial block circuit diagram showing the internal configuration of a peripheral device according to an embodiment of the present invention, and FIGS. 2(a) and (b) are waveforms showing control signals of different types of CPUs, respectively. 3 and 4 respectively show the CP used in the peripheral LSI device according to the present invention.
FIG. 2 is a block circuit diagram showing an example of a U search circuit. 1...CPU search circuit, 2...I/Taf Ace for human type, 3...Interface for B type, 4...
Control resistor, 5, 6.8...NOR gate, 7...
・7 Ripflo, Pu, 9.12-1.12-2.12-
4.13, 14°16... Inverter, 10-1.
10-2.10-4゜11-1.11-2.11-4・
...AND gate, 15...NAND dart.

Claims (1)

[Claims] A microprocessor search circuit that determines the type of a microprocessor based on a difference in the timing relationship of a plurality of control signals inputted from the connected microprocessors; 1. A semiconductor integrated circuit device comprising an interface circuit and selecting an interface circuit corresponding to a connected microprocessor based on an output of the microprocessor search circuit.