JPS6184074A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS6184074A JPS6184074A JP59206084A JP20608484A JPS6184074A JP S6184074 A JPS6184074 A JP S6184074A JP 59206084 A JP59206084 A JP 59206084A JP 20608484 A JP20608484 A JP 20608484A JP S6184074 A JPS6184074 A JP S6184074A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- electrode
- light
- substrate
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F10/00—Individual photovoltaic cells, e.g. solar cells
- H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
- H10F10/17—Photovoltaic cells having only PIN junction potential barriers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/10—Semiconductor bodies
- H10F77/16—Material structures, e.g. crystalline structures, film structures or crystal plane orientations
- H10F77/162—Non-monocrystalline materials, e.g. semiconductor particles embedded in insulating materials
- H10F77/164—Polycrystalline semiconductors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/548—Amorphous silicon PV cells
Landscapes
- Photovoltaic Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
「発明の利用分野」
この発明は、水素またはハロゲン元素が添加されたPI
N接合を有するアモルファス半導体を含む非単結晶半導
体を絶縁表面を有する基板に設けた光電変換素子(単に
素子という)を複数個電気的に直列接続をして、高い電
圧を発生せしめる光電変換装置に関する。Detailed Description of the Invention "Field of Application of the Invention"
Relating to a photoelectric conversion device that generates a high voltage by electrically connecting in series a plurality of photoelectric conversion elements (simply referred to as elements) in which a non-single crystal semiconductor including an amorphous semiconductor having an N junction is provided on a substrate having an insulating surface. .
「従来の技術」
従来、水素またはハロゲン元素が添加された非単結晶半
導体としてアモルファス半導体が知られている。しかし
、かかる半導体はアモルファス構造を有し、結晶性を積
極的に用いていないため、PIN接合における■型半導
体層のキャリアの空乏層の厚さは0.3μ以下と狭く、
また、A11 (100mW/cm”)での光照射に対
し劣化が生じてしまった。"Prior Art" Conventionally, amorphous semiconductors are known as non-single crystal semiconductors to which hydrogen or halogen elements are added. However, since such a semiconductor has an amorphous structure and does not actively use crystallinity, the thickness of the carrier depletion layer of the ■-type semiconductor layer in the PIN junction is as narrow as 0.3μ or less.
In addition, deterioration occurred due to light irradiation at A11 (100 mW/cm").
「本発明が解決しようとする問題点」
本発明は、かかるアモルファス半導体を含む水素または
ハロゲン元素を含有する非単結晶半導体に対し、レーザ
アニールを行い、異方性を有する柱状粒を結晶化を助長
せしめて形成し、光照射に対する劣化を防ぎ、かつPI
N接合を有する光電変換装置の電流が流れる方向に対し
てはI型半導体の活性領域の空乏層を1J以上と大きく
巾広にすることを特徴としている。``Problems to be Solved by the Present Invention'' The present invention involves performing laser annealing on non-single crystal semiconductors containing hydrogen or halogen elements, including such amorphous semiconductors, to crystallize columnar grains having anisotropy. promotes formation, prevents deterioration due to light irradiation, and
It is characterized in that the depletion layer in the active region of the I-type semiconductor is widened to 1 J or more in the direction in which current flows in a photoelectric conversion device having an N junction.
さらに連結部を構成する非活性半導体領域は、結晶粒の
粒界を多数回横切る方向にして高抵抗とし、この非活性
領域での電極間リークを防ぐものである。Furthermore, the inactive semiconductor region constituting the connecting portion has a high resistance in a direction that crosses the grain boundaries of crystal grains many times, thereby preventing leakage between electrodes in this inactive region.
「問題を解決しようとする手段」
本発明は、透光性電極側よりこの電極を透過して、内部
の非単結晶半導体に対し、500nm以上省波長のパル
ス状の強光(パルス巾10〜1000秒)を照射して、
■型半導体層またはそれに近接したPまたはN型半導体
層を水素またはハロゲン元素を柱状粒の粒界に多量に偏
析させて内部に保存しつつ結晶性を促進せしめるもので
ある。"Means for Solving the Problem" The present invention transmits a light-transmitting electrode from the side of the transparent electrode to the internal non-single-crystal semiconductor with pulsed strong light (with a pulse width of 10 to 1000 seconds),
(2) The crystallinity of the type semiconductor layer or the P or N type semiconductor layer adjacent thereto is promoted by segregating a large amount of hydrogen or a halogen element at the grain boundaries of the columnar grains and storing the hydrogen or halogen element inside the layer.
特に本発明は、その光吸収が小さい500 nm以上一
般には0.5〜2μ例えば0.53μまたは1.06μ
のYAG レーザまたは波長0.69μのルビーレーザ
のパルス状の強光を照射し、全体または内部の十分深い
領域までのI型半導体の結晶性を柱状粒として異方性を
有せしめて促進させる、いわゆる光アニールを行った。In particular, the present invention has a light absorption of 500 nm or more, generally 0.5 to 2μ, for example 0.53μ or 1.06μ.
Irradiating strong pulsed light from a YAG laser or a ruby laser with a wavelength of 0.69μ to promote the crystallinity of the I-type semiconductor as a whole or to a sufficiently deep region in the form of columnar grains with anisotropy. So-called optical annealing was performed.
このため、光は照射光側の透光性導電膜(Eg #3.
0eV)に対し損傷を与えない波長でかつ半導体の光吸
収係数の比較的少ない、即ち深い領域まで光アニールを
行い得る500nm以上の波長を用いた。Therefore, the light is transmitted through the transparent conductive film (Eg #3.
A wavelength of 500 nm or more was used, which is a wavelength that does not cause damage to 0 eV) and has a relatively small optical absorption coefficient of the semiconductor, that is, a wavelength of 500 nm or more that can perform optical annealing to a deep region.
本発明は、この先アニールにより同時に伴う電気伝導度
の増加が、集積化構造にあってアイソレイションの妨げ
になってはならない。このため本発明方法においては、
この先アニールを活性半導体領域のみにおいては、粒界
が電流の流れに平行に、かつ、この非活性領域において
は粒界が電界と交叉するように異方性を有せしめた。即
ち、基板に対し垂直方向に成長せしめた。In the present invention, the increase in electrical conductivity that accompanies the subsequent annealing must not interfere with isolation in the integrated structure. Therefore, in the method of the present invention,
The annealing was performed to have anisotropy such that the grain boundaries were parallel to the current flow only in the active semiconductor region, and the grain boundaries crossed the electric field in the non-active region. That is, the growth was made perpendicular to the substrate.
本発明はこの先アニールと同時またはその前または後の
工程において、非活性領域で集積化のためのに連結部を
構成するため、非単結晶半導体をレーザ光 (Qスイッ
チ)がかけられたYAG レーザ光によりスクライブし
、除去したものである。In the present invention, a YAG laser is applied to a non-single crystal semiconductor with laser light (Q-switch) in order to form a connection part for integration in an inactive region in a process that is performed simultaneously with, before, or after annealing. It was scribed and removed using light.
「作用」
本発明は、柱状粒の異方性を用いるため、各セル間のア
イソレイション領域は、もし電流が流れ得ても、柱状粒
を横切る方向であるため抵抗が大きく、十分なアイソレ
イションができる。他方、PINの電流は柱状粒にそっ
た方向であり、電流は粒界を横切らない。加えて光はラ
ンダムに1層内で光路を有せしめ、光吸収係数が大きい
水素を多量に有する粒界を多数回横切るように光閉じ込
め型のセルとする。即ち第1および裏面側の第2の電極
を凹凸にせしめ、また裏面電極は反射性を有せしめるこ
とが有効である。本発明はこれらの効果を存し、かつ集
積化光電変換装置の製造に光照射面側からの光を加えて
光アニール工程のみで他の余分の工程を伴わずに完了さ
せることができるという特長を有する。"Operation" Since the present invention uses the anisotropy of columnar grains, even if current can flow in the isolation region between each cell, the resistance is large because it is in the direction across the columnar grains, and sufficient isolation is required. I can do it. On the other hand, the current in PIN is in the direction along the columnar grains and does not cross grain boundaries. In addition, an optical confinement type cell is formed in which light is randomly given optical paths within one layer and crosses grain boundaries containing a large amount of hydrogen, which has a large optical absorption coefficient, many times. That is, it is effective to make the first and second electrodes on the back side uneven and to make the back electrode reflective. The present invention has these effects, and has the advantage that the manufacturing of an integrated photoelectric conversion device can be completed by adding light from the light irradiation surface side and completing the photo annealing process without any other extra steps. has.
本発明の装置における素子の配置、大きさ、形状は設計
仕様によって決められる。しかし本発明の内容を簡単に
するため、以下の詳細な説明においては、第1の素子の
下側(基板側)の第1の電極と、その右隣りに配置した
第2の素子の第2の電極(半導体上即ち基板から離れた
側)とを電気的に直列接続させた場合のパターンを基と
して記す。The arrangement, size, and shape of elements in the device of the present invention are determined by design specifications. However, in order to simplify the content of the present invention, in the following detailed description, the first electrode on the lower side (substrate side) of the first element and the second electrode of the second element disposed on the right side thereof will be described. The pattern is based on the case where the electrodes (on the semiconductor, that is, on the side away from the substrate) are electrically connected in series.
そしてこの規定された位置にLS用のレーザ光、例えば
波長1.06μ(光径約50μ)または0.53μ(光
径約25μ)のYAGレーザ(焦点路111i140
m m )を照射させる。Then, a laser beam for LS is applied to this specified position, for example, a YAG laser (focal path 111i140
m m ) is irradiated.
さらにそれを0.05〜5m/分例えば30cm 7分
の操作速度で移動せしめ、前工程と従属関係の開講を作
製せしめる。Further, it is moved at an operating speed of 0.05 to 5 m/min, for example, 30 cm/7 min, to create a subordinate relationship with the previous process.
本発明は、基板が透光性のガラスである場合、また、非
透光性基板上に半導体を形成し、その上面の光照射に対
し500nm以上のレーザ光アニール(エネルギ密度は
lXl0’〜I Xl0Jす/cm2でありレーザスク
ライブの際のエネルギ密度の5X106〜5 X 10
7W/cm2より1/10〜1/103である)を行っ
たもので、製造工程を従来公知の光電変換WiZの作製
工程を単にレーザアニール工程を加えるのみで、歩留り
を従来の約60%より84%にまで高めることができる
という画期的な光電変換装置の作製方法を提供すること
にある。In the present invention, when the substrate is a light-transmitting glass, or when a semiconductor is formed on a non-light-transmitting substrate, the upper surface is annealed with a laser beam of 500 nm or more (the energy density is lXl0' to I Xl0J/cm2, and the energy density during laser scribing is 5X106~5X10
7W/cm2), and by simply adding a laser annealing process to the conventional photoelectric conversion WiZ manufacturing process, the yield has been reduced to about 60% of the conventional method. It is an object of the present invention to provide an innovative method for manufacturing a photoelectric conversion device that can increase the conversion rate to 84%.
以下に図面に従って本発明の詳細を示す。The details of the invention are shown below in accordance with the drawings.
「実施例1」 第1図は本発明の光電変換素子の縦断面図である。"Example 1" FIG. 1 is a longitudinal sectional view of the photoelectric conversion element of the present invention.
図面において、絶縁表面を有する基板例えばガラス基1
反(1)であって、1.5cm 、巾2cmを用いた。In the drawings, a substrate with an insulating surface, for example a glass substrate 1
A piece (1) of 1.5 cm and a width of 2 cm was used.
さらにこの上面に、全面にわたって第1の導電膜(2)
である透光性導電膜を0.1〜0.5μの厚さに形成さ
せた。この導電膜は高低差〜0.1 μの凹凸を有せし
めた。Further, on this upper surface, a first conductive film (2) is formed over the entire surface.
A transparent conductive film having a thickness of 0.1 to 0.5 μm was formed. This conductive film had unevenness with a height difference of 0.1 μm.
この透光性導電膜(2)として弗素等のハロゲン元素が
添加された酸化スズを主成分とする透光性導電膜または
ITO(酸化スズ・インジューム) (500〜500
0人代表的には500〜1500人)をスパッタ法また
はスプレー法により形成させて、第1の導電膜とした。This transparent conductive film (2) is a transparent conductive film whose main component is tin oxide to which a halogen element such as fluorine is added, or ITO (tin oxide indium) (500 to 500
(typically 500 to 1,500 people) was formed by a sputtering method or a spray method to form a first conductive film.
この後、この上面にプラズマCVD法、フォトCvD法
またはLPCV D法により、光照射により光起電力を
発生する非単結晶半導体即ちPIN接合を存する水素ま
たはハロゲン元素が添加された非単結晶半導体層(3)
をI型半導体中の最低酸素濃度を5×10111cm−
3以下とし、かつその厚さを0.3〜5.Op代表的に
は2.0μの厚さに形成させた。Thereafter, a non-single-crystal semiconductor layer to which hydrogen or a halogen element is added on the upper surface by a plasma CVD method, a photo-CvD method, or an LPCV-D method to form a non-single-crystal semiconductor that generates photovoltaic force upon light irradiation, that is, a PIN junction. (3)
The minimum oxygen concentration in type I semiconductor is 5 x 10111 cm-
3 or less, and the thickness is 0.3 to 5. Op is typically formed to have a thickness of 2.0 μm.
その代表例は光照射が基板側からの場合であるため、P
型(SixC1−xO< x < 1 )半導体(約2
00A)−I型アモルファスまたはセミアモルファスの
シリコン半導体(約2.0μ)−N型の微結晶(約50
0人)を有する半導体よりなる1つのPIN接合を有す
る非単結晶半導体(3)を均一の膜厚で形成させた。A typical example is when light is irradiated from the substrate side, so P
type (SixC1-xO<x<1) semiconductor (approximately 2
00A) - I-type amorphous or semi-amorphous silicon semiconductor (approximately 2.0 μ) - N-type microcrystal (approximately 50
A non-single-crystal semiconductor (3) having one PIN junction made of a semiconductor having a uniform thickness (0) was formed to have a uniform thickness.
第1図において、さらにこの上面に第2の導電膜(5)
およびコネクタ(30)を形成した。In FIG. 1, a second conductive film (5) is further formed on this upper surface.
and a connector (30) was formed.
さらに本発明方法における500 nm以上の波長(一
般には530nmまたは1.06μ)を発光するYAG
またはルビーパルス光レーザアニール装置の概要および
その方法を示す。Further, in the method of the present invention, YAG that emits light at a wavelength of 500 nm or more (generally 530 nm or 1.06μ)
Also, an outline of a ruby pulsed light laser annealing apparatus and its method will be presented.
被照射構造物は第1図または裏面電極を形成する前の半
導体(3)が積層された基板を対象とする。The structure to be irradiated is the one shown in FIG. 1 or the substrate on which the semiconductor (3) is laminated before forming the back electrode.
光源の照射光面積は光学系を用いてlmmX9mmの照
射面積としたルビーパルスレーザ光を用いた。The irradiation area of the light source was set to 1 mm x 9 mm using an optical system using a ruby pulse laser beam.
また、スキャンスピードとの関係でその厚さを1mmと
して、照射エネルギ密度を制御するため、100 μ〜
3mmまで可変させてもよい。In addition, in relation to the scan speed, the thickness was set to 1 mm, and in order to control the irradiation energy density, the thickness was set at 100 μ~
It may be varied up to 3 mm.
ここではCTCコムチックトレーニング株式会社製レー
ザ発振器を用いた。Here, a laser oscillator manufactured by CTC Comtic Training Co., Ltd. was used.
さらにこのレーザ光はレンズで長方形に集光し、パルス
光(周波数300Hz 〜30KHz)を有し5KW
/c艷(巾11の場合)となった。Furthermore, this laser beam is focused into a rectangular shape by a lens, has pulsed light (frequency 300Hz to 30KHz), and has a power output of 5KW.
/c (for width 11).
この照射光(25)を被照射面に一定速度の移動基体に
照射させた。This irradiation light (25) was irradiated onto the irradiated surface of a moving base at a constant speed.
か(すると、非単結晶半導体中で1層の全厚さく波長0
.7μの場合)または0.53μの波長を用いる場合に
その半分程度の3000〜5000人の深さの領域に柱
状粒の結晶化を助長させる領域を作ることができた。こ
の結晶化の事実は、この工程の後レーザラマン分光測定
を行うことにより判明した。(Then, the total thickness of one layer in a non-single crystal semiconductor is
.. When using a wavelength of 7μ) or 0.53μ, it was possible to create a region that promotes crystallization of columnar grains in a region with a depth of 3,000 to 5,000 people, which is about half of that. The fact of this crystallization was found by performing laser Raman spectroscopy after this step.
加えて、この本発明方法のアニールは光パルスアニール
のため、結晶化の際、既に含有している水素またはハロ
ゲン元素を外部に脱気することが少なく、また結晶粒界
に偏析せしめ、この粒界でのの不対結合手を中和させ得
る。加えて結晶性または秩序性を光アニールにより促進
するため、光劣化特性が小さくなり、加えてPN間のア
モルファス半導体における1層中の空乏層の巾をアモル
ファス構造のPIN接合における0、3μより結晶性を
有せしめるため、1〜3μと伸ばすことができるという
二重の特長を有していた。このため1層の最適厚さをア
モルファス半導体の0.5 μより1.5〜2.0μに
まで厚くさせることができ、光電変換装置としての電流
を増加させ得る。In addition, since the annealing method of the present invention is a light pulse annealing, hydrogen or halogen elements that are already contained are less likely to be degassed to the outside during crystallization, and they are segregated at grain boundaries and are It can neutralize the unpaired bond in the field. In addition, since crystallinity or orderliness is promoted by photoannealing, photodegradation characteristics are reduced, and in addition, the width of the depletion layer in one layer in an amorphous semiconductor between PN can be reduced from 0.3μ in a PIN junction with an amorphous structure. It had the double feature of being able to be stretched to 1 to 3 μm in order to give it elasticity. Therefore, the optimum thickness of one layer can be increased from 0.5 μ of an amorphous semiconductor to 1.5 to 2.0 μ, and the current as a photoelectric conversion device can be increased.
かくの如(第1図に示した半導体上の第2の導電膜(5
)は金属と透光性導電酸化膜(CTF) とを用いた。Thus (the second conductive film (5) on the semiconductor shown in Figure 1)
) used metal and a transparent conductive oxide film (CTF).
その厚さはそれぞれ300〜1500人に形成させ、光
閉じ込め型の構造とした。The thickness of each layer was formed by 300 to 1,500 people, and the structure was an optical confinement type.
このCTFとしてクロム−珪素化合物等の非酸化物導電
膜よりなる透光性導電膜を用いてもよい。As this CTF, a light-transmitting conductive film made of a non-oxide conductive film such as a chromium-silicon compound may be used.
これらは電子ビーム蒸着法またはスパッタ法、フォトC
vD法、フォト・プラズマCVD法を含むCVD法を用
い、半導体層を劣化させないため、250°C以下の温
度で形成させた。These are electron beam evaporation method, sputtering method, photo C
A CVD method including a vD method and a photo-plasma CVD method was used to form the semiconductor layer at a temperature of 250° C. or lower in order to prevent deterioration of the semiconductor layer.
斯くして照射光(10)に対し、この実施例の如き基板
(3,5mm X 3cm)において、11.8%(1
,05cm2)の変換効率を存せしめることができた。Thus, for the irradiation light (10), on the substrate (3.5 mm x 3 cm) as in this example, 11.8% (1
, 05 cm2).
第2図は本発明の思想の概要を説明する構成図である。FIG. 2 is a configuration diagram illustrating the outline of the idea of the present invention.
第2図(A)は柱状粒(40) (ここでは3ケ所のみ
を示す)をその柱径(41)が0.1〜2μ、一般には
1μ以下を5E)1 (走査電子顕微鏡写真)で調べた
ところ、平均粒径、0.1〜0.15μを有し、垂直方
向に成長している。Figure 2 (A) shows columnar grains (40) (only three locations are shown here) with a columnar diameter (41) of 0.1 to 2μ, generally less than 1μ as 5E)1 (scanning electron micrograph). Upon examination, it was found that the average grain size was 0.1-0.15μ, and they grew vertically.
このエネルギハンド巾を第2図(B) 、 (C) 、
(D) 、 (E)に示す。即ち第2図(B)は第2
図(A)におけるB−Boの柱状粒の中央部の縦方向に
電界が加わらない場合である。(C)は電界によりホー
ル(42)、電子(43)がドリフトしている。(D)
は柱状粒のA−へ”での断面におけるエネルギハンドを
横方向に示す。This energy hand width is shown in Figure 2 (B), (C),
Shown in (D) and (E). In other words, Fig. 2 (B) is the second
This is a case in which no electric field is applied in the vertical direction at the center of the B-Bo columnar grain in FIG. In (C), holes (42) and electrons (43) are drifting due to the electric field. (D)
shows the energy hand in the cross section of the columnar grain at "A-to" in the lateral direction.
すると光照射によって発生した電子(42′)、ホール
(43’)は粒界での水素が多量にある領域で光−電気
変換をしてキャリア(42) 、 (42“)を発生ず
る。Then, electrons (42') and holes (43') generated by light irradiation undergo photo-electrical conversion in the region where a large amount of hydrogen exists at the grain boundary, and generate carriers (42) and (42'').
そのキャリアはより安定なレベルである柱状粒の内部に
ドリフトする。このため再結合中心の多くが存在する粒
界により離れた柱状粒の中央部でキャリアをドリフトす
ることができる。The carriers drift to a more stable level inside the columnar grains. Therefore, carriers can be drifted in the center of the columnar grains, which are separated by the grain boundaries where most of the recombination centers are present.
他方、第2図(E)に示すごとく、集積化構造における
連結部のアイソレイション領域ではこの粒界を横切るご
とくにして電界が印加される。この時は粒界(45)が
バリアになり、リーク電流を流しにくい。即ち光電変換
装置の集積化を行わんとするとき、連結部を構成する非
活性領域ではリーク電流をより流さないようにするには
、基板に対し垂直方向に柱状粒を成長させればよい。On the other hand, as shown in FIG. 2(E), an electric field is applied across the grain boundaries in the isolation region of the connection portion in the integrated structure. At this time, the grain boundaries (45) act as a barrier, making it difficult for leakage current to flow. That is, when attempting to integrate a photoelectric conversion device, columnar grains may be grown in a direction perpendicular to the substrate in order to prevent leakage current from flowing in the inactive region forming the connection portion.
第2図(F)は柱状粒(40)の粒界(45)に水素が
偏析し高濃度になる。このためこの粒界が光学的Egを
大きくし、かつアモルファス半導体と同様に光吸収係数
が大きい。In FIG. 2(F), hydrogen segregates at grain boundaries (45) of columnar grains (40) and becomes highly concentrated. Therefore, this grain boundary increases the optical Eg and has a large light absorption coefficient like an amorphous semiconductor.
このことより、光はこの粒界を多数回横切るようにする
ことが薄い厚さで光−電気変換を効率よく行うに重要で
あることがわかる。This shows that it is important for light to cross this grain boundary many times in order to efficiently perform light-to-electrical conversion with a small thickness.
またこれらの理由により、半導体の柱径は真性または実
質的に真性の半導体の厚さの0.1〜5μに比べそれ以
下で、一般的には0.05〜0.2μにする、二とが有
効である。Also, for these reasons, the diameter of the pillars of the semiconductor is smaller than the thickness of the intrinsic or substantially intrinsic semiconductor, which is 0.1 to 5 μ, and is generally 0.05 to 0.2 μ. is valid.
これ以上にすると、粒界で発生したキャリアは柱状粒内
部へのドリフトよりも先にPまたはN層Gこドリフトし
てしまい、十分に行われず、即ち粒界で水素によりバリ
アを高くした意味が減少してしまう。If it is more than this, the carriers generated at the grain boundaries will drift into the P or N layer G before drifting into the interior of the columnar grains, and this will not be carried out sufficiently, which means that the purpose of raising the barrier with hydrogen at the grain boundaries will be lost. It will decrease.
第3図における(15) 、 (16)はそれぞれ縦方
向の電気伝導度及び横方向の電気伝導度を示す。In FIG. 3, (15) and (16) indicate the electrical conductivity in the vertical direction and the electrical conductivity in the lateral direction, respectively.
各グラフにおける初期値は水素が添加されたアモルファ
ス半導体の構造において濶べた光転導度(15) 、
(17)および暗転導度(16) 、 (18)である
。次のプロットはルビーレーザアニールをアモルファス
半4体に行ない多結晶化した後の特性、第3のプロット
の光照射(AMI)を2時間照射した後の電気伝導度を
示す。さらに第4の測定点は150℃、2時間熱アニー
ルした後の特性を示す。The initial value in each graph is the optical conductivity (15) in the structure of an amorphous semiconductor doped with hydrogen.
(17) and dark conductivity (16), (18). The next plot shows the characteristics after polycrystallization by performing ruby laser annealing on the amorphous semi-quartet, and the third plot shows the electrical conductivity after irradiation with light irradiation (AMI) for 2 hours. Furthermore, the fourth measurement point shows the characteristics after thermal annealing at 150° C. for 2 hours.
これらの結果より明らかなことは、垂直方向の電気伝導
度は光アニールにより約3倍に光転導度゛が向上するが
、粒界を横切る水平方向の(17)に示す電気伝導度は
約1710に減少する。It is clear from these results that the electrical conductivity in the vertical direction improves by approximately three times due to photoannealing, but the electrical conductivity in the horizontal direction across grain boundaries, shown in (17), increases by approximately 3 times. It decreases to 1710.
加えて、粒界に存在する水素、酸素等により横方向の電
気伝導度特性には光劣化(ステブラ・ロンスキ効果)が
見られるが、垂直方向の電気伝導度には実質的には変化
がなく、きわめて安定である。In addition, photodeterioration (Stebler-Lonski effect) is observed in the electrical conductivity characteristics in the lateral direction due to hydrogen, oxygen, etc. present at the grain boundaries, but there is virtually no change in the electrical conductivity in the vertical direction. , is extremely stable.
実施例2 第4図は本発明の製造工程を示す縦断面図である。Example 2 FIG. 4 is a longitudinal sectional view showing the manufacturing process of the present invention.
被膜の製造プロセスは実施例1と同様に行った。The manufacturing process of the film was carried out in the same manner as in Example 1.
即ち、図面において、絶縁表面を有する基板例えばガラ
ス基板(1)であって、長さく図面では左右方向) 1
0cm、巾10cmを用いた。さらに、この上面に、全
面にわたって第1の導電膜(2)である透光。That is, in the drawing, a substrate having an insulating surface, for example, a glass substrate (1), whose length is in the left-right direction in the drawing) 1
0 cm and a width of 10 cm. Further, on this upper surface, a first conductive film (2) is formed to transmit light over the entire surface.
性導電膜(2)を0,1〜0.5 μの厚さに凹凸を有
して形成させた。A conductive film (2) was formed with a thickness of 0.1 to 0.5 μm and an uneven pattern.
この後、この基板の上側より、YAGレーザ(波長0.
53μ(パルス中30n秒)加工機(日本電気型)によ
り平均出力0.3〜IW (焦点距離40 m m )
を加え、直径5mm φのレーザ光を集光し、スポット
径20〜70μφ代表的には50μφをマイクロコンピ
ュータにより制御して、上方よりレーザ光を照射し、そ
の走査により、スクライブライン用の第1の開溝(13
)を形成させ、各活性素子領域(31) 、 (11,
)に第1の電極(15)をレーザスクライブ(LSとい
う)により作製した。After this, a YAG laser (wavelength 0.
53 μ (30 ns during pulse) Average output 0.3 to IW (focal length 40 mm) by processing machine (Nippon Denki type)
is added, a laser beam with a diameter of 5 mm φ is focused, a spot diameter of 20 to 70 μφ is typically controlled by a microcomputer, and the laser beam is irradiated from above. Open groove (13
), and each active element region (31), (11,
), a first electrode (15) was produced by laser scribing (referred to as LS).
LSにより形成された開講(13)は、巾約50μ長さ
10cmであり、深さはそれぞれ第1の電極を構成させ
るために完全に切断分離した。The openings (13) formed by LS had a width of about 50 μm and a length of 10 cm, and the depths were completely cut and separated to form the first electrodes.
か(して第1の素子(31)および第2の素子(11)
を構成する領域の巾は5〜40mm例えば10mmとし
て一形成させた。(The first element (31) and the second element (11)
The width of the area constituting the area is 5 to 40 mm, for example, 10 mm.
この時、第1の開講(13)に充填させた半導体は高抵
抗型であり、アイソレイションが行われなければならな
い。At this time, the semiconductor filled in the first semiconductor (13) is of a high resistance type, and isolation must be performed.
この後、この上面にプラズマCVD法、フォl−CVD
法またはLPCV D法により、実施例と同様に非単結
晶半導体層(3)を0.5〜5.0μ代表的には2.0
μの厚さに形成させた。After this, plasma CVD method, Fol-CVD method is applied to this upper surface.
method or LPCV D method to form a non-single crystal semiconductor layer (3) with a thickness of 0.5 to 5.0 μm, typically 2.0 μm, as in the example.
It was formed to a thickness of μ.
さらに第4図(B)に示されるごとく、第1の開講(1
3)の左方向側(第1の素子側)にわたって第2の開講
(14)を第2のLSI程により形成させた。Furthermore, as shown in Figure 4 (B), the first lecture (1
A second opening (14) was formed over the left side (first element side) of 3) by the second LSI process.
この図面では第1および第2の開講(13) 、 (M
)の中心間を100μずらしている。In this drawing, the first and second openings (13), (M
) are shifted by 100μ.
かくして第2の開溝(18)は第1の電極の側面または
上面(8) 、 (9)を露出させた。The second open groove (18) thus exposed the side or top surface (8), (9) of the first electrode.
さらに本発明は、第1の電極(2)の透光性導電膜(1
5)の表面のみを露呈させてもよいが、製造、・歩留り
の向上のためには、レーザ光が0.1〜ト例えば0.8
Wでは多少強すぎ、この第1の電極(15)の深さ方向
のすべてを除去した。しかし、その側面(8)(側面の
みまたは側面と上面の端部)に第1図(C)で第2の電
極(38)とのコネクタ(30)が密接しても、その接
触抵抗が一般に酸化物−酸化物コンタクト(酸化スズ−
ITOコンタクト)となり、その界面にkl物バリアが
形成されないため、実用上何等問題はなかった。Furthermore, the present invention provides a transparent conductive film (1) of the first electrode (2).
Although only the surface of 5) may be exposed, in order to improve production and yield, it is recommended that the laser beam be 0.1 to 0.8
W was a little too strong, so the entire depth of this first electrode (15) was removed. However, even if the connector (30) with the second electrode (38) in FIG. Oxide-oxide contact (tin oxide)
ITO contact), and no Kl barrier was formed at the interface, so there was no practical problem.
第4図において、さらにこの上面に第4図(C)に示さ
れるごとく、第2の導電膜(5)およびコネクタ(30
)を形成した。In FIG. 4, as shown in FIG. 4(C), a second conductive film (5) and a connector (30
) was formed.
・この第2の導電膜(5)は金属と透光性導電酸化膜(
CTF) とを用いた。その厚さはそれぞれ300〜1
500人に形成させた。・This second conductive film (5) is made of metal and a transparent conductive oxide film (
CTF) was used. Its thickness is 300~1
500 people formed it.
さらに本発明方法における500 nm以上の波長を発
光するルビーパルス光レーザアニールは実施例1と同様
に行った。Furthermore, the ruby pulse light laser annealing which emits light with a wavelength of 500 nm or more in the method of the present invention was performed in the same manner as in Example 1.
即ち、被照射用基板は第4図(B)または(C)に示す
。That is, the substrate to be irradiated is shown in FIG. 4(B) or (C).
第2の透光性電極(5)を形成する前または後の構造物
を光アニール工程における対象基体として実施例1と同
様に行った。The same procedure as in Example 1 was carried out using the structure before or after forming the second light-transmitting electrode (5) as the target substrate in the photo-annealing process.
かくして、図面では示していないが、光アニール(25
)を光照射面側から行い、栽仮に垂直方向の柱状粒を有
する半導体にI型半導体を形成させた。Thus, although not shown in the drawings, optical annealing (25
) was performed from the light irradiation side to form an I-type semiconductor on the semiconductor having columnar grains in the vertical direction.
この時、領域(13)の非活性領域(34) (33’
) の半導体は素子(31) 、 (11)の第1
の電極間のアイソレイションを行うため、柱状粒は多数
回横切るように基板に垂直に成長させた。At this time, the inactive area (34) (33'
) are the first elements of elements (31) and (11).
In order to achieve isolation between the electrodes, the columnar grains were grown perpendicularly to the substrate, crossing them many times.
このレーザアニールの後、第3のLSにより切断分離を
して複数の第2の電極(39) 、 (38)を第3の
開講(20)を形成してアイソレイションした。After this laser annealing, a third LS was used to cut and separate the plurality of second electrodes (39) and (38) to form a third electrode (20) and isolate them.
このCTFとしてクロム−珪素化合物等の非酸化物導電
膜よりなる透光性導電膜を用いてもよい。As this CTF, a light-transmitting conductive film made of a non-oxide conductive film such as a chromium-silicon compound may be used.
かくして第4図(C)に示されるごとく、複数の素子(
31) 、 (11)を連結部(4)で直列接続する光
電変換装置を作ることができた。Thus, as shown in FIG. 4(C), a plurality of elements (
31) and (11) were connected in series at the connection part (4) to create a photoelectric conversion device.
第4図(D)はさらに本発明を光電変換装置として完成
させんとしたものである。即ちパッシベイション膜とし
てプラズマ気相法またはフォト・プラズマ気相法により
窒化珪素膜(21)を500〜2000人の厚さに均一
に形成させ、各素子間のリーク電流の湿気等の吸着によ
る発生をさらに防いだ。FIG. 4(D) shows the present invention further completed as a photoelectric conversion device. That is, as a passivation film, a silicon nitride film (21) is uniformly formed to a thickness of 500 to 2,000 layers by a plasma vapor phase method or a photo plasma vapor phase method, and the leakage current between each element is caused by adsorption of moisture, etc. This further prevented the outbreak.
さらに外部引出し端子(22) 、 (22’ )を周
辺部に設けた。Furthermore, external lead-out terminals (22) and (22') were provided at the periphery.
斯くして照射光(10)に対し、この実施例のごとき基
板(10cm X LOcm)において、各素子を巾1
0mm X 92mrrlの短冊状に設け、さらに連結
部の中200μm外部引出し電極部の巾3mm、周辺部
4mmによリ・実質的に88mm x 92mm内に1
0段を有せしめた。Thus, for the irradiation light (10), on a substrate (10 cm x LO cm) as in this example, each element has a width of 1
It is provided in a strip shape of 0 mm x 92 mrrl, and furthermore, the width of the 200 μm external extraction electrode part in the connecting part is 3 mm, and the peripheral part is 4 mm.
It has a 0 stage.
その結果、パネルにて8.3%(理論的に゛は9.6%
になるが、11段直列連結抵抗により実効変換効率が低
下した(^旧(100mW /cm2]))にて、6.
7Wの出力電力を存せしめることができた。The result was 8.3% on the panel (theoretically 9.6%
However, the effective conversion efficiency decreased due to the 11-stage series-connected resistor (^old (100mW/cm2)), 6.
It was possible to maintain an output power of 7W.
またさらにこのパネルを大きくし、例えば40cmX
60cmを2ヶ直列にアルミサツシの固い枠内またカー
ボン・ブラックによる可曲性枠内に組み合わせることに
よりパッケージさせ、120cm X 40cmのNE
DO規格の大電力用のパネルを設けることが可能である
。Furthermore, make this panel larger, for example, 40cmX.
A 120cm x 40cm NE is packaged by combining two 60cm pieces in series within a hard frame made of aluminum sash or a flexible frame made of carbon black.
It is possible to provide DO standard high power panels.
またこのNEDO規格のパネル用にはシーフレックスに
よりガラス基板の裏面(照射面の反対側)に本発明の光
電変換装置の上面をはりあわせて、風圧、雨等に対し機
械強度の増加を図ることも有効である。In addition, for this NEDO standard panel, the top surface of the photoelectric conversion device of the present invention is attached to the back surface of the glass substrate (opposite side to the irradiation surface) using Seaflex to increase mechanical strength against wind pressure, rain, etc. is also valid.
パネルの実効効率としてAMI (100mW/cm
”)にて8.7%、化カフ、8Wを得ることができた。The effective efficiency of the panel is AMI (100mW/cm
”), we were able to obtain 8.7%, cuff, and 8W.
有効面積は82.8cm”であり、パネル全体の82.
8%を有効に利用することができた。The effective area is 82.8 cm”, and the total panel area is 82.8 cm”.
8% could be used effectively.
本発明におけるレーザアニールは、0.53μパルス巾
30n秒のYAG レーザまたは0,69μ(パルス巾
70n秒)の波長のルビーレーザを用いた。For laser annealing in the present invention, a YAG laser with a 0.53 μ pulse width of 30 ns or a ruby laser with a wavelength of 0.69 μ (pulse width 70 ns) was used.
しかしこの500nm(0,5μ) 〜5000nm(
5μm)の波長光を他のレーザ光、またはフラッシュ状
のキセノンランプ等を用いて行うことは有効である。However, this 500nm (0.5μ) ~ 5000nm (
It is effective to use another laser beam or a flash-shaped xenon lamp to emit light with a wavelength of 5 μm).
本発明の実施例は半導体装置における特にガラス基板側
から光照射を行う光電変換装置に関して記した。しかし
これを金属基板上に絶縁膜コートをし、この上面に下側
電極、半導体、上側電極を積層し、基板の上方からの照
射の光電変換装置にも適応し得る。加えて、PTNまた
はNIP構造を有する水素またはハロゲン元素が添加さ
れたフォトセンサ、イメージセンサに対して本発明を適
用してもよいことはいうまでもない。The embodiments of the present invention have been described regarding semiconductor devices, particularly photoelectric conversion devices that irradiate light from the glass substrate side. However, this method can also be applied to a photoelectric conversion device in which irradiation is applied from above the substrate by coating a metal substrate with an insulating film and laminating a lower electrode, a semiconductor, and an upper electrode on the upper surface. In addition, it goes without saying that the present invention may be applied to photosensors and image sensors to which hydrogen or halogen elements are added and have a PTN or NIP structure.
「効果」
本発明は第5図に示す如く、光照射(AMI (100
mw/cm2))効果に対してきわめて有効である。そ
してその1例として一般的なアモルファスPIN型半導
体の劣化特性(50)に比べて、I型半導体の場合は1
.0〜5μと厚いにもかかわらず、きわめてその劣化が
少ない結果(51)を本発明では得ることができた。(
51)は実施例1、(52)は実施例2の特性である。"Effect" As shown in FIG.
mw/cm2)) effect. As an example, compared to the deterioration characteristics of a general amorphous PIN type semiconductor (50), in the case of an I type semiconductor, 1
.. In spite of the thickness of 0 to 5 μm, the present invention was able to obtain results (51) in which the deterioration was extremely small. (
51) is the characteristic of Example 1, and (52) is the characteristic of Example 2.
第1図は本発明の光電変換装置の縦断面図を示す。
第2図は本発明で得られる柱状粒および対応するエネル
ギハンド閣を示す。
第3図は本発明で得られる特性を示す。
第4図は本発明の光電変換装置の製造工程を示す縦断面
図である。
第5図は本発明の光パルスアニールを行なわない光電変
換装置と、本発明の光パルスアニールを行った光電変換
装置の光照射信頬性特性である。FIG. 1 shows a longitudinal cross-sectional view of a photoelectric conversion device of the present invention. FIG. 2 shows the columnar grains and the corresponding energy hand obtained according to the invention. FIG. 3 shows the characteristics obtained with the present invention. FIG. 4 is a longitudinal sectional view showing the manufacturing process of the photoelectric conversion device of the present invention. FIG. 5 shows the light irradiation cheek characteristics of a photoelectric conversion device without optical pulse annealing according to the present invention and a photoelectric conversion device subjected to optical pulse annealing according to the present invention.
Claims (3)
上に密接してPIN接合を有する水素またはハロゲン元
素が添加された非単結晶半導体と、該半導体上に第2の
電極とを有する光電変換素子を複数個直列に連結部にて
連結して設けた半導体装置において、真性または実質的
に真性のI型半導体は基板に垂直方向に柱状粒を一部ま
たは全部に有せしめることを特徴とする半導体装置。1. A substrate having an insulating surface has a first electrode, a non-single crystal semiconductor doped with hydrogen or a halogen element having a PIN junction in close contact with the electrode, and a second electrode on the semiconductor. A semiconductor device including a plurality of photoelectric conversion elements connected in series at a connecting portion, characterized in that the intrinsic or substantially intrinsic type I semiconductor has columnar grains in part or all in a direction perpendicular to the substrate. semiconductor device.
電極は凹凸表面を有し、裏面電極は反射性電極が設けら
れたことを特徴とする半導体装置。2. 2. A semiconductor device according to claim 1, wherein the first and second electrodes have uneven surfaces, and the back electrode is provided with a reflective electrode.
非活性領域は結晶粒の粒界を多数回横切る方向にして高
抵抗領域を設けることを特徴とする半導体装置。3. 2. A semiconductor device according to claim 1, wherein the inactive region constituting the connecting portion is provided with a high resistance region in a direction that crosses grain boundaries of crystal grains many times.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59206084A JPS6184074A (en) | 1984-10-01 | 1984-10-01 | semiconductor equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59206084A JPS6184074A (en) | 1984-10-01 | 1984-10-01 | semiconductor equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6184074A true JPS6184074A (en) | 1986-04-28 |
Family
ID=16517552
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59206084A Pending JPS6184074A (en) | 1984-10-01 | 1984-10-01 | semiconductor equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6184074A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61231771A (en) * | 1985-04-05 | 1986-10-16 | Semiconductor Energy Lab Co Ltd | Method for manufacturing semiconductor devices |
US5481121A (en) * | 1993-05-26 | 1996-01-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having improved crystal orientation |
US5534716A (en) * | 1993-08-27 | 1996-07-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having transistors with different orientations of crystal channel growth with respect to current carrier direction |
US5962871A (en) * | 1993-05-26 | 1999-10-05 | Semiconductor Energy Laboratory Co., Ltd. | Method for producing semiconductor device |
US6090646A (en) * | 1993-05-26 | 2000-07-18 | Semiconductor Energy Laboratory Co., Ltd. | Method for producing semiconductor device |
JP2001358350A (en) * | 2000-06-12 | 2001-12-26 | Canon Inc | Photovoltaic element |
US6475840B1 (en) * | 1993-06-12 | 2002-11-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
JP2013149951A (en) * | 2011-12-21 | 2013-08-01 | Panasonic Corp | Thin-film solar cell and manufacturing method thereof |
-
1984
- 1984-10-01 JP JP59206084A patent/JPS6184074A/en active Pending
Cited By (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61231771A (en) * | 1985-04-05 | 1986-10-16 | Semiconductor Energy Lab Co Ltd | Method for manufacturing semiconductor devices |
US5481121A (en) * | 1993-05-26 | 1996-01-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having improved crystal orientation |
US6337231B1 (en) | 1993-05-26 | 2002-01-08 | Semiconductor Energy Laboratory Co., Ltd. | Method for producing semiconductor device |
US5824573A (en) * | 1993-05-26 | 1998-10-20 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
US5962871A (en) * | 1993-05-26 | 1999-10-05 | Semiconductor Energy Laboratory Co., Ltd. | Method for producing semiconductor device |
US6090646A (en) * | 1993-05-26 | 2000-07-18 | Semiconductor Energy Laboratory Co., Ltd. | Method for producing semiconductor device |
US6121076A (en) * | 1993-05-26 | 2000-09-19 | Semiconductor Energy Laboratory Co., Ltd. | Method for producing semiconductor device |
US6475840B1 (en) * | 1993-06-12 | 2002-11-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US6194254B1 (en) | 1993-08-27 | 2001-02-27 | Semiconductor Energy Laboratories Co., Ltd. | Semiconductor device and method for manufacturing the same |
US5616506A (en) * | 1993-08-27 | 1997-04-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a crystallized silicon thin film in which the crystallization direction is oriented either vertically or horizontally to the current flow direction |
US5534716A (en) * | 1993-08-27 | 1996-07-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having transistors with different orientations of crystal channel growth with respect to current carrier direction |
US6482686B1 (en) | 1993-08-27 | 2002-11-19 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing a semiconductor device |
US7045819B2 (en) | 1993-08-27 | 2006-05-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US7410849B2 (en) | 1993-08-27 | 2008-08-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US7875508B2 (en) | 1993-08-27 | 2011-01-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US8133770B2 (en) | 1993-08-27 | 2012-03-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
JP2001358350A (en) * | 2000-06-12 | 2001-12-26 | Canon Inc | Photovoltaic element |
JP2013149951A (en) * | 2011-12-21 | 2013-08-01 | Panasonic Corp | Thin-film solar cell and manufacturing method thereof |
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