JPS6182260A - I/O interrupt control method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an interrupt control method in a data processing system, and particularly in a system where a CPU and an input/output adapter operate independently and asynchronously.
The present invention relates to an input/output interrupt control method that enables faster input/output processing by shortening the time during which a CPU is occupied when an interrupt request is made to a U.

[Conventional technology]

FIGS. 2 and 3 show two examples of conventional typical input/output interrupt control methods. In both figures, 1 is a CPU, 2 is a main storage device, 3 is a lotus, 4.5 is an input/output adapter, 6 is an input/output device #1, 7 is an input/output device #2, and 8 is interrupt information.

In the example shown in Figure 2, when the input/output adapter 4 sends an interrupt request signal to the CPU 1 based on a request from the input/output device #1 (■), the CPU checks the interrupt mask, and if it is not masked, This is accepted, the interrupt information is directly read from the interrupt information area 8 of the input/output adapter 4, and the cause of the first interrupt is analyzed (■). That is, the content of the cause of the interrupt and the machine number (#1) of the input/output unit of the interrupt requesting device are identified, the corresponding control command information is determined, and the control command information is written to the input/output adapter 4 for control.

In the example shown in FIG. 3, in response to an interrupt request (■') from the input/output adapter 4, the CPUI notifies interrupt permission (■'), and the input/output adapter 4 responds to the above-mentioned 4. <
1 Store the interrupt information 8 and the machine number (#1) of the input/output crab unit at a predetermined fixed address of the device 2 (■')
. Based on this information, the CPU 1 analyzes the cause of the interrupt, sets control command information, and sends the input/output adapter 4
I'm trying to control it.

[Problem that the invention seeks to solve]

As seen in the examples of FIGS. 2 and 3, conventionally, it is necessary to transfer interrupt information from the two output adapters to the CPU every time two interrupt requests are received.

Since the CPU is occupied during this time, there is a problem in that other processing is delayed.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention provides the above-mentioned 1. a
The input/output adapter is notified of the interrupt information storage address in the device, and when an end interrupt is raised from an active input/output device, it does not immediately raise an interrupt request to the CPU, but instead The interrupt information is stored in the main memory address notified by the CPU, and then an interrupt request is sent to the CPU.

According to the configuration of the present invention, in a data processing system in which a CPU and an input/output adapter operate asynchronously, the CPU receives interrupt information of the main storage device that is predetermined for each input/output device number for the input/output adapter. Notify me of the storage area address.

When making an interrupt request to the CPU, the input/output adapter first stores the interrupt information in the interrupt information storage area notified in advance, then makes an interrupt request to the CPU, and in response, the CPU issues an interrupt. When a permission notification is received, the CPU is notified of the input/output device number, and the CPU accesses the corresponding interrupt information storage area based on the input/output device number notified from the input/output adapter and retrieves one interrupt information. It is characterized by interrupt processing.

[Action of the invention]

According to the present invention, the CPU does not need to perform processing to capture interrupt information when receiving an interrupt request from an input/output adapter, and can directly refer to a predetermined address in the main storage device using only the machine number of the input/output device. The burden of this will be reduced.

〔Example〕

FIG. 1 is a block diagram of a system according to an embodiment of the present invention.

In the figure, 1 is the CP, U, 2 is the main storage, 3 is the bus, 4 and 5 are input/output adapters, 6 is human output device #1,
7 is input/output device #2. 8° and 8' are input/output devices #1, respectively. Interrupt information #2, 9.9' is also input/output device #1. Unit control word UC for #2
W (#1), UCW (#2), 10. 10'
Similarly, 11 is an interrupt information storage area for input/output devices #1 and #2, and 11 is a management table that provides correspondence between input/output device machine numbers and interrupt information storage area addresses. Also,
Each unit control word UCW is provided with one interrupt information storage address area 9a, 9a'.

The unit control word UCW is used as control information for the input/output adapter to multiplex control multiple input/output devices under it. stored separately. Each has three control states: ready state, operating state 9 interrupt pending state. The ready state is a state waiting for activation from the CPU'U, and is activated when the CPU issues an input/output command, and transitions to the operational state.

In the operating state of unit control word UCW, UC
The content of the command specified by W, for example, executes data transfer, activates the corresponding input/output device, and performs data transfer processing. Then, when a termination interrupt is raised from the input/output device due to the completion of data transfer, a transition is made to a 2-interrupt pending state. This state is maintained until the interrupt processing by the CPU is completed, and upon completion of the interrupt processing, the device returns to the operable state and returns to the state where it waits for the next activation.

Furthermore, each input/output control word (UCW 9, 9') has interrupt information storage address areas 9a, 98' as shown in Figure 2. The address of the information storage area 10.10' is set.

The human output adapter 4 is connected to the unit control word LJ mentioned above.
Using CW 4m function, each input/output dehyce is 6,7°...
・Data transfer between the CPU and the main storage device 2 is executed asynchronously and independently from the CPU.

The input/output adapter 4 responds to the end interrupt from the input/output device and makes an interrupt request to the CPUI. , uni-nod control word t''UCW (9,9
4 above pointed to by the interrupt information storage address in ',...)
．． into the interrupt information storage area of device 2 (10°10',...
・Transfer to ).

The interrupt information G includes the command address at the end of data transfer, control flag, remaining byte count, input/output device status, input/output adapter status, etc.

The input/output adapter 4 inputs 1 interrupt information into the above 1. After storing it in the designated area of the a device 2, an interrupt request signal is sent to the CPUI. When there is a response from the CPUI indicating that it has been accepted, the I/O device number 3m of the interrupt request source is known.

On the other hand, when the CPUI detects the interrupt request signal from the input/output adapter 4, it checks the mask.

If the reception is possible, the input/output adapter 4 is notified of the reception. Next, when the machine number of the input/output device is sent, the management table 11 of the main storage device 2 is referred to, the address of the machine number is obtained, and the input information storage area (10, 10', ・
...) Read one interrupt information from the area of the corresponding address.

Subsequently, the CPU 1 notifies the input/output adapter 4 that the interrupt information has been received. The input/output adapter thereby terminates the operation of the input/output device. That is, the UCW is made operational.

Next, a series of operations of the embodiment system shown in FIG. 1 will be schematically explained using the time chart shown in FIG.

(2) is the IPL time, and the interrupt information storage address is set in the unit control word UCW. UCW becomes operational.

In (2), the CPU activates the input/output adapter, the UCW (#1) becomes operational, and as a result, the input/output adapter activates the manual saw device (#1).

In (2), data transfer between the main storage device and the input/output device (#1) is executed.

In ■, the input/output adapter that receives the end interrupt from the input/output de-hysteret (#1) puts the UCW (#1) in the interrupt pending state and transfers the interrupt information to the area of the main storage device specified by the UCW (#1). Store it in

In (2), an interrupt request is sent from the input/output adapter to the CPU.

In (2), the CPU sends a notification to the input/output adapter. In response, the input/output adapter returns the input/output device number.

In (2), the CPU performs a process of reading interrupt information from the main memory.

In (2), the CPU notifies the input/output adapter of reception of interrupt information. And the input/output adapter.

Return UCW (#1) to operational status.

〔Effect of the invention〕

As described above, according to the present invention, from the input/output adapter to the C
This is because when making an interrupt request to PtJ, the interrupt request signal is raised to the CPU after one interrupt information is transferred.

Until then, the CPU can perform other processing,
The processing efficiency of the CPU can be improved.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a system according to an embodiment of the present invention. Figures 2 and 3 are explanatory diagrams of the conventional method, and Figure 4 is the illustration of the 1st method.
3 is a time chart of an operation example of the embodiment system shown in the figure. In the figure, 1 is a CPU, 2 is a main storage device, and 3 is a bus. 4 and 5 are input/output adapters, 6 and 7 are input/output devices #1 and #2, 8 and 8' are interrupt information, 9
and 9' are unit control words UCW (#I) and UCW (#2), 9a and 9a' are interrupt information storage address areas, 10 and 10' are interrupt information storage areas, and 11 is a management table.

Claims (1)

[Claims] In a data processing system in which a CPU and an input/output adapter operate asynchronously, the CPU notifies the input/output adapter in advance of the interrupt information storage area address of the main storage device determined for each input/output device model number, When making an interrupt request to the CPU, the input/output adapter first stores the interrupt information in the interrupt information storage area notified in advance, then makes an interrupt request to the CPU, and in response, the CPU issues an interrupt. When a permission notification is received, the CPU is notified of the input/output device number, and the CPU accesses the corresponding interrupt information storage area based on the input/output device number notified from the input/output adapter, and retrieves the interrupt information. An input/output interrupt control method characterized by interrupt processing.