JPS6176142A - Ultrasonic receiving phasing circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to the configuration of a wave receiving phaser for an electronic scanning ultrasonic tomography apparatus.

[Background of the invention]

A typical example of a conventional receiving phaser is the 1980-15
As described in No. 8706, a receiving phasing system includes a first delay means for phasing a received signal with a minute delay time and a second delay means for phasing a received signal with a relatively long delay time. There is a vessel. This method is simpler than phasing with one stage of delay means for each array element, but since all analog LC delay lines are used as delay means, performance can be improved by increasing the number of array elements. In this case, the circuit size increases and the equipment becomes expensive.

[Purpose of the invention]

An object of the present invention is to provide a simplified receiving phaser for an ultrasonic tomographic apparatus.

[Summary of the invention]

In order to achieve such an object, the present invention phases the minute delay time by controlling the phase of the control signal of the sample-and-hold circuit, and then uses a switch to switch between a tap input type LC delay line or a fixed (or variable) delay line. A relatively large delay time is phased by a delay means in which a means and an adder are coupled in series.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing a circuit configuration for phasing a received signal from the deflection angle θ direction according to the present invention.

1.2. . . . , N is an array element, X-1 to X-M are minute delay means using the sample and hold circuit shown in FIG. 2(a), M MPXil'i input terminals, and a switch array at the output terminal. , 5L-1 to SL- have fixed delay means or variable delay means with a delay time τm, and AL-1 to AL- have 2
10-1 is an output terminal of an adder with one human output.

In Fig. 1(b), HH' is the same phase plane of the received waves with the deflection angle θ, and in order to add the received signals of the array elements in the same phase, after delaying the signal of the first element by τ, It is necessary to add the signals of all elements. However, τ1=i×τ0+ΔTI
(1) Here, θ is the deflection angle, d is the element interval, ■ is the speed of sound, and ΔTI is the convergence delay time.

Therefore, the delay time τl for the i-th element is τ, ==kX
rL+Δτ turbidity (2) However, when k=1~, a relatively large delay time (kXτL) common to each element corresponding to the m-th minute delay means, and figure(
It can be divided into the remaining minute delay Δτl shown in the shaded area in b).

FIG. 2(a) shows a sample and hold circuit for performing a minute delay. 1 to 4 are array elements, S-1 to S-4,
S-0 is a sample hold means, Fig. 2(b)
Samples and holds are performed according to control signals C1 to C4 and Co shown in FIG.

A-1 is an adder, B-1 is an output terminal of the minute delay block X-1, and is also an input terminal of the switch MPX shown in FIG. 1(a).

If the minute delay times of the received signals of the first to fourth elements with respect to the deflection angle θ and the convergence distance t are Δτ1 to Δτ4, Fig. 2 (
According to b), the received signals of each of the elements 1 to 4 are sampled and held at times 01 to C4, which are earlier by Δτl to Δτ4, respectively, with respect to the sample and hold time Co of the sample and hold means S-0, and the signals are sampled and held by the adder A-1. After each hold value is added, the addition result is sampled and held at time C6, and the hold value of the addition result is output to the output terminal B-1.

By repeating this process every sampling period T, a phased output with a minute delay with respect to the deflection angle θ is discretely outputted every period T to the output terminal B-1. In FIG. 1, the output is connected to the output terminal 'l of MPX for performing a relatively large delay (kXτL) for block X-1 by a switch array MPX that can be switched at each time CO.
'-k is selected and input to adder AL-k. Similar processing is possible for each of the minute delay blocks X-2 to X-M, and the output terminals T-L to T-K of MPX are
The phasing results of minute delays shown in the shaded areas in FIG. 1(b) are output. The adder AL- adds the output signal from the output terminal 'l'- of MPX and the output signal from the delay means SL-, and then inputs the signal to the delay means 5L-(k+1). The signal that has passed through the delay means SL twice is delayed by (k×τL). Therefore, the output terminal 10-1 outputs the phasing results of the received signals of each element with respect to the deflection angle θ and the convergence distance t shown in FIG. 1(b).

FIG. 2(C) shows the configuration of the minute delay block when the minute delay times Δτ1 to Δτ3 are long with respect to the sampling period T. FIG. 2(d) shows the sample hold time of the sample hold means S-IN5-3, 5-00 in FIG. 2(C). The received signal of element 1 is sampled and held at time C1, held for Δτl−Δτ2, and then added to the received signal of multiple element 2 by adder A-1, and sampled and held at time C2. Similarly below,
The signal of element 1 is Δτ11 The signal of element 2 is Δτ2, element 3
After the signal is held for Δτ3, it is added to the signal of the cable 4 by an adder A-3, and the addition result is sampled and held at time Co. Therefore, the slightly delayed phased outputs of the received signals of the elements 1 to 4 are outputted every period T to the output terminal B-1. Hereinafter, by performing the relatively large delay as described above, phasing of the received signal of each element with respect to the deflection angle θ and the convergence distance t can be realized in this case as well.

In the small delay block using sample and hold shown in Fig. 2, the control signal C is
Since it is possible to phase an arbitrary minute delay time Δr by changing +−Ca, dynamic focusing can be realized by changing Δτl for each sampling for different convergence distances t.

Fixed or variable delay means 5L-1 to SL- in FIG. 1(a)
For example, an analog LC delay line, a sample and hold circuit, a COD, a switched capacitor memory, etc. can be used. If variable delay means are used, the number of output terminals of the switch ivl P X can be reduced. In the explanation of FIG. 1(b), for the sake of simplicity, a relatively large delay is divided into equal intervals, and the delay means 5L-
It was delayed from 1 to SL-, but it was divided at uneven intervals and 5L-
It is clear that the present invention is applicable even when 1 to 5L-K are set to different delay times.

FIG. 3 is a diagram showing a second embodiment of the present invention. G-
1 to G- are current mirror amplifiers, and DL is one analog LC delay line having K tap input terminals T'-1 to T'-K. Other symbols are the same as in FIG. 1(a). The signal processing from output terminals T-1 to T-K of MPX is the same as that shown in FIGS. 1 and 2. Minute delay block X output to output terminals T-1 to T-K
The phased output voltage values of -1 to X-M are converted into current values by current mirror amplifiers G-1 to G-K, and then input to taps T'-1 to T'-K of the LC delay line DL. Ru. T'
The delay intervals from -1 to T'- are equal intervals (or unequal intervals) for each rL, and the signals input to each tap have a relatively large delay other than the shaded area in Fig. 1(b). Thereafter, it is added as a current value and output to the output terminal 10-1.

Therefore, in this case as well, the deflection angle θ
It is possible to realize a received signal for the convergence distance t.

FIG. 4 is a diagram showing a third embodiment of the present invention. Fourth
In figure (a), F-1 to F- are integrators, M P
X-1 is a switch array with one input terminal and one output terminal. Other symbols are the same as in FIG. 1(a). Fourth
Figure (b) shows the integrator F-1 and the switch MP connected to it.
1 is a diagram showing an example of the configuration of X, MPX-1. W, 1-1~
Wl-M is a switch array on the input side corresponding to integrator F-1, 0F-1 is an operational amplifier, CA-1 is a capacitor, 5W-1 is a switch for discharging capacitor 0-1,
R-1 is an output side switch of integrator F-1. Figure 4 (
C) is a diagram showing the ON-OFF timing of each switch shown in FIG. High level is ON, low level power is O
It is FF. The signal processing from the output terminals B-1 to B-M of the small delay blocks X to X-M is shown in FIGS.
This is the same as shown in the figure.

, the operation of integrator F-1 will be explained using FIGS. 4(b) and 4(c). At time to, switch W1-1 is ONL,
All other switches related to F-1 are turned OFF.

The phased output of the small delay block X-1 is integrated into the capacitor CA-1 for a minute time Δ. Small delay block X-
The phased output of No. 2 is delayed by a relatively large delay time rL shown in equation (2) corresponding to the deflection angle θ, and is integrated into the ONL of the switch W1-2 and the capacitor A-1. Similarly, the phased output of each small delay block is connected to the capacitor CA-
1, and the time (to + (M 1) τ + Δ)
Then, the phased outputs of all the array elements are integrated into the capacitor/server A-1.

After that, the switch ratio -1 is turned ON, and the output terminal 10-1 is connected to C.
Output the integral value of A-1. After the switch R-1 is turned off, the switch 8W-1 is turned on a short time later, the charge in the capacitor CA-1 is discharged, and the integrator F-1 is cleared. With the sampling period being T, the same processing as that for the integrator F-1 is repeatedly performed for the integrator F-2 from time to+T. The same process is repeated for the integrators F-3 to F-K, so that the output terminal 1
0-1 outputs the phasing result for the deflection angle θ every sampling period T.

〔Effect of the invention〕

As described above, according to the present invention, a receiving phaser can be realized with a simple configuration by phasing a small delay using a sample and hold circuit and then selecting the input of a relatively large delay means using a switch. . Therefore, by increasing the number of array elements, a high-performance receiving phaser can be realized in a small size and at a low cost.

[Brief explanation of the drawing]

FIG. 1(a) is a diagram showing the configuration of an embodiment of the present invention.
FIG. 2(b) is a diagram showing the delay time of each element with respect to the deflection angle θ, FIG. 2(a) is a diagram showing the configuration of the minute delay means, FIG. C) is the second minute delay means, FIG. 2(d) is an explanatory diagram of its operation, FIG. 3 is a diagram showing the second embodiment of the present invention, and FIGS. 4(a) and (b). (C) is a diagram showing a third embodiment of the present invention. 1 to N...Array element, X1 to X-M...Minute delay means, MPX, MPX-1...Switcher array, S-1
~S-4, S-0...Sample hold circuit, A-1
~A-3, AL-1 ~AL-K...Adder, 5L-1
~5L-K...Fixed (or variable) 4 extending means, G-1~
G-K...Current mirror amplifier, DL...Tapped analog LC delay line, F-1 to F-K...Integrator,
Wl-1 to Wl-M, 5W-1, R-1...switcher,
0P-1...Operation amplifier, CA-1...Capacitor. No. / Country<'>) No. 22 m) (b) <C) (d,) No. 412] (Shin
(C)1+T-1

Claims (1)

[Claims] 1. The amplitude of the transmitted or received signal of each element of the array vibrator;
In an ultrasonic tomography device that deflects or focuses an ultrasonic beam by controlling the phase and obtains a tomographic image, a sample is used to perform phasing with a minute delay for each of the received signals of N arrayed transducers. M first delay means (where N=n×M) each consisting of a hold means, a switching means that can arbitrarily select 2 output terminals for M input terminals, and a fixed delay means (or 1. An ultrasonic reception phasing circuit characterized in that a second delay means in which variable delay means (variable delay means) and adders are arranged alternately in series performs a relatively large delay to phase a reception signal. 2. The ultrasonic receiving phasing circuit according to claim 1, wherein a tapped analog LC delay line by current addition is used as the second delay means. 3. The ultrasonic receiving phasing circuit according to claim 1, wherein sample-hold means and adders are arranged alternately in series as the second delay means. 4. As the second delay means, K integrators are provided corresponding to the K output terminals of the switching means, and each output of the integrators is selected by the switch. An ultrasonic receiving phasing circuit according to claim 1.