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JPS6170715A - Growing method of compound semiconductor - Google Patents

Growing method of compound semiconductor

Info

Publication number
JPS6170715A
JPS6170715A JP59191672A JP19167284A JPS6170715A JP S6170715 A JPS6170715 A JP S6170715A JP 59191672 A JP59191672 A JP 59191672A JP 19167284 A JP19167284 A JP 19167284A JP S6170715 A JPS6170715 A JP S6170715A
Authority
JP
Japan
Prior art keywords
layer
gaas
substrate
temperature
grown
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59191672A
Other languages
Japanese (ja)
Other versions
JPH0236060B2 (en
Inventor
Masahiro Akiyama
秋山 正博
Yoshihiro Kawarada
河原田 美裕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP59191672A priority Critical patent/JPS6170715A/en
Publication of JPS6170715A publication Critical patent/JPS6170715A/en
Publication of JPH0236060B2 publication Critical patent/JPH0236060B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10P14/2905
    • H10P14/24
    • H10P14/3221
    • H10P14/3421

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To obtain a GaAs layer of high quality by cleaning the surface of a substrate of Si or Ge by high temperature treatment, then growing a thin GaAs buffer layer on the (100) substrate at a low temperature, and growing the GaAs layer to be obtained on the buffer layer. CONSTITUTION:To epitaxially grown a GaAs layer on the 100 surface of Si or Ge substrate, the substrate is heat treated under arsenic pressure by removing the surface oxide film of the substrate at temperature for obtaining clean substrate surface. A GaAs buffer layer of 200Angstrom or lower in thickness is grown at 450 deg.C or lower, and the GaAs layer is grown at the growing temperature of the normal GaAs layer. Thus, after high temperature treatment is performed and cleaned, a thin GaAs buffer layer is grown at low temperature, and a GaAs layer to be obtained is grown on the buffer layer at the growing temperature of the normal GaAs layer. Thus, the GaAs layer which has no oval defect and good crystallinity of sole domain can be obtained.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明はシリコン(Si )基板又はゲルマニウム(
Ge)基板上に砒化ガリウム(GaAs)層をエピタキ
シャル成長させる方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) This invention applies to silicon (Si) substrates or germanium (germanium) substrates.
The present invention relates to a method for epitaxially growing a gallium arsenide (GaAs) layer on a Ge) substrate.

(従来の技術) 半導・体集積回路技術の急速な進展に伴い、大面積の基
板上に大規模集積回路を形成しようとしたり又は三次元
回路を形成しようとする試みが成されている。或いは又
ソーラセルの研究も盛んとなヲlいる。そのためには、
例えば、81基板上に高部質のGaAs単結晶層を形成
することが望まれ<%する。しかしながら、従来は81
基板上にGaAs層を直接成長させることが困難であっ
たため、81基板上に何等かのバッファ層を一旦成長さ
せ、このバッファ層上にGaAs層を成長させる試みが
なされていた。そして文献(Applied Phys
icsLetters 38 (10) 、 15 M
ay 1981 、 p 779〜781)にも開示さ
れているように、このパツファ門としてGeの薄膜を使
用する例が多い。
(Prior Art) With the rapid progress of semiconductor and integrated circuit technology, attempts have been made to form large-scale integrated circuits on large-area substrates or to form three-dimensional circuits. Furthermore, research into solar cells is also active. for that purpose,
For example, it is desirable to form a high quality GaAs single crystal layer on an 81 substrate. However, conventionally 81
Since it has been difficult to grow a GaAs layer directly on a substrate, attempts have been made to first grow some kind of buffer layer on the 81 substrate and then grow the GaAs layer on this buffer layer. and literature (Applied Phys.
icsLetters 38 (10), 15 M
AY 1981, p. 779-781), there are many examples in which a thin film of Ge is used as the gate.

(発明が解決しようとする問題点) しかしながら、81基板の(loo)面上にGaAs層
を成長させると、Geバッファ層を介したとしてもGa
As層がアンテイフ千イズドメイン(antiphas
e domain )構造となってしまい、その結果充
分な良質な結晶性をもったGaAs層が得られなくなる
という欠点があった。
(Problems to be Solved by the Invention) However, when a GaAs layer is grown on the (loo) plane of the 81 substrate, even though the GaAs layer is grown through the Ge buffer layer,
The As layer is an antiphas domain.
As a result, a GaAs layer with sufficient quality crystallinity cannot be obtained.

また、GeとGaAsとを同一の成長装置内で連続的に
結晶成長させると、GaAs層中にGeのドーピングが
あるという欠点があった。
Furthermore, when Ge and GaAs are successively grown in the same growth apparatus, there is a drawback that Ge is doped in the GaAs layer.

この発明の目的は、従来用いていたGeバッファ層を形
成せずに、81又はGe基板上に単一のドメインから成
る高品質のGaAs層を成長させる方法を提供すること
にある。
It is an object of the present invention to provide a method for growing a high quality single domain GaAs layer on an 81 or Ge substrate without forming the conventionally used Ge buffer layer.

(問題点を解決するだめの手段) 1    この目的の達成を図るため、この発明の方法
によれば、シリコン(Si )又はゲルマニウム(Ge
)基板の(100)面上に砒化ガリウム(GaAs)層
をエピタキシャル成長させるに当り、 該シリコン又はゲルマニウム基板を、砒素圧の下で及び
前記基板の表面酸化膜を除去して清浄な基板面を得る温
度で、熱処理する工程と、清浄された該基板上に、45
0℃以下の温度で、)’x%oo又程度以下の厚さの砒
化ガリウムのバッファ掘を成長させる工程と、 該バッファ層上に、通常の砒化ガリウム層の成長温度で
、該砒化ガリウム層を成長させる工程とを含むことを特
徴とする。
(Another Means to Solve the Problems) 1 In order to achieve this object, according to the method of the present invention, silicon (Si) or germanium (Ge)
) When epitaxially growing a gallium arsenide (GaAs) layer on the (100) plane of the substrate, the silicon or germanium substrate is placed under arsenic pressure and the surface oxide film of the substrate is removed to obtain a clean substrate surface. A step of heat treatment at a temperature of 45% is applied to the cleaned substrate.
growing a gallium arsenide buffer layer with a thickness of less than or equal to )'x%oo at a temperature of 0° C. or less; and growing a gallium arsenide layer on the buffer layer at a normal gallium arsenide layer growth temperature. and a step of growing.

(作用) このように、この発明によれば、基板を高温熱処理して
清浄にした後、低温で薄いGaA3 /<ツファ層を成
長させ、続いて通常のGaAs層の成長温度でバッファ
層上に目的とするGaAs層を成長させるので、いわゆ
るオーバルディフェクトのないシ単一ドメインの結晶性
の良いGaAs層が得られる。
(Operation) According to the present invention, after the substrate is cleaned by high-temperature heat treatment, a thin GaA layer is grown at a low temperature, and then a thin GaA layer is grown on the buffer layer at a normal GaAs layer growth temperature. Since the desired GaAs layer is grown, a single domain GaAs layer with good crystallinity without so-called oval defects can be obtained.

また、この発明の方法によれば、Geのノ々ツファ層を
用いる代わりにGaAsの薄いバッファ層を用い、その
上に本来のGaAs層を形成するので、同一の成長装置
内でGaAsバッファ層とGaAs層とを連続成長させ
て高品質のGaAs層を得ることが出来る。
Furthermore, according to the method of the present invention, a thin GaAs buffer layer is used instead of a Ge thin buffer layer, and the original GaAs layer is formed on top of the thin GaAs buffer layer, so that the GaAs buffer layer and the GaAs buffer layer can be formed in the same growth apparatus. A high quality GaAs layer can be obtained by continuously growing the GaAs layer.

(実施例) 以下、図面を参照してこの発明の方法の一実施例につき
説明する。尚、この実施例では、基板として81基板を
用い及び原料としてトリメチルガリウA (Ga(an
、)a )及びアルシン(As Ha )を用い、η相
成長法特にMOCvD法で81基板上にGaAs層を1
a1長させる例につき説明する。
(Example) An example of the method of the present invention will be described below with reference to the drawings. In this example, an 81 substrate was used as the substrate, and trimethylgalium A (Ga(an) was used as the raw material.
, ) a ) and arsine (As Ha ), one GaAs layer is grown on an 81 substrate by the η phase growth method, especially the MOCvD method.
An example of increasing a1 length will be explained.

−一1図は、この発明の化合物半導体の成長方法て実施
する際の、基板を載置するサセプタの温度変化を示す線
図で、以下の説明では温度についてけこのサセプタの温
度で説明するが、ガス流量、ガスの流し方、反応管の形
状、サセプタの形状、サセプタを何度まで加熱している
か等によって基板の温度がサセプタの温度よりも100
”C程度位 。
Figure 11 is a diagram showing the temperature change of the susceptor on which the substrate is placed when carrying out the compound semiconductor growth method of the present invention.In the following explanation, the temperature will be explained using the temperature of the susceptor. , the temperature of the substrate may be 100° higher than the temperature of the susceptor depending on the gas flow rate, the way the gas flows, the shape of the reaction tube, the shape of the susceptor, the temperature to which the susceptor is heated, etc.
”Around C.

まで低くなることもある。It can sometimes go as low as.

先ず、気相成長装置の反応管中のサセプタに81基板を
載置した後、キャリアガスとして例えばH2を流しなが
らサセプタの温度を室温から昇温させる(第1図に示す
時間区間工)。この昇温の途中で、サセプタの温度が5
00〜600°cになった時、砒素圧下による高温熱処
理を行うため、この場合にはAsH3を流し始める。こ
の時のAs Haの分圧は少なくとも0.5 Torr
位となっていれば充分である。尚、このAs Haは、
後述する目的とするGaAs層を成長させた後サセプタ
温度が500℃以下になるまで、流し続ける。
First, after placing the 81 substrate on a susceptor in a reaction tube of a vapor phase growth apparatus, the temperature of the susceptor is raised from room temperature while flowing, for example, H2 as a carrier gas (time period shown in FIG. 1). During this temperature rise, the temperature of the susceptor reaches 5
When the temperature reaches 00 to 600°C, in order to perform high-temperature heat treatment by reducing arsenic pressure, in this case AsH3 starts to flow. At this time, the partial pressure of As Ha is at least 0.5 Torr.
It is sufficient if it is in the same position. Furthermore, this As Ha is
After growing a target GaAs layer to be described later, the flow is continued until the susceptor temperature becomes 500° C. or lower.

サセプタ温度が砒素圧の下で81基板の表面酸化膜を除
去して清浄な基板面を得ることが出来る温度、例えば9
00℃以上の温度好ましくは900%950 ’Cに達
したら、昇温をやめて、この温度にml持して高温熱処
理を行う(第1図に示す時間区−1u)。この場合、熱
処理をH2とAs Haの雰囲気中で行いその処理時間
は5分程度で充分である。
The susceptor temperature is 81 under arsenic pressure, the temperature at which the surface oxide film of the substrate can be removed and a clean substrate surface can be obtained, e.g. 9
When the temperature reaches 00°C or higher, preferably 900% 950'C, the temperature increase is stopped and the high temperature heat treatment is carried out while maintaining this temperature (time interval -1u shown in Fig. 1). In this case, the heat treatment is performed in an atmosphere of H2 and As Ha, and the treatment time is about 5 minutes.

この高温熱処理後、温度を下げて(第1図に示す時間区
間TIE ) 450℃以下の温度好ましくは400−
450℃の温度に保持し、As HaにGa(OH3)
、3を加えた原料ガスを流し、清浄させた81基板の(
lOO)基板面上にGaAsの薄膜をバッファ層として
成長させる(第1図に示した時間区間■)。このGaA
sバッファ層の厚みを200Å程度以下とする。
After this high-temperature heat treatment, the temperature is lowered (time interval TIE shown in FIG. 1) to a temperature of 450° C. or lower, preferably 400° C.
Maintain the temperature at 450℃ and add Ga(OH3) to As Ha.
, 3 was added to the 81 substrate (
lOO) A thin film of GaAs is grown as a buffer layer on the substrate surface (time interval ■ shown in FIG. 1). This GaA
The thickness of the s-buffer layer is about 200 Å or less.

このGaAsバッファ層を成長完了後、再びサセプタ温
度を昇温させて、本来の目的とするGaAs層の通常の
成長温度である650〜soo’c程度にする(第1図
に示す時間区間V)。この実施例ではこの温度を700
’Cとする。この温度の昇温過程において、GaAsバ
ッファ層はアニールされることとなり、その結果、この
GaAsバッファ層は、その上に形成されるGaAs層
がオーバルディフェクトのない結晶性の良い層となるよ
うな、良質なバッファ層となる。
After the growth of this GaAs buffer layer is completed, the susceptor temperature is raised again to about 650 to soo'c, which is the normal growth temperature of the originally intended GaAs layer (time interval V shown in Figure 1). . In this example, this temperature is set to 700
'C. In this temperature raising process, the GaAs buffer layer is annealed, and as a result, the GaAs buffer layer is formed so that the GaAs layer formed thereon becomes a layer with good crystallinity without oval defects. It becomes a high quality buffer layer.

次に、このサセプタを700”Cに保持して、GaAs
バッファ層上にGaAs層を成長させる(第11の時間
区間■)。そのため、再びGa (CHa ) 3を副
長するのに適当な量のAs Haに加えて目的とす゛ 
愕GaAs層を成長させる。
Next, this susceptor was held at 700"C and the GaAs
A GaAs layer is grown on the buffer layer (eleventh time interval ■). Therefore, in addition to an appropriate amount of As Ha to make Ga (CHa) 3 the subcomponent again,
Grow a thin GaAs layer.

このGaAs層の成長が終ったら、サセプタ温度を室温
まで下げる(第1図に示す時間区間■)。
After the growth of this GaAs layer is completed, the susceptor temperature is lowered to room temperature (time interval (■) shown in FIG. 1).

このようにして、同一の気相成長装置内で連続的1に上
述した各処理を行って単一ドメインの高品網のGaAs
層を81基板の(100)面上に成長させ不ことが出来
、この一連の処理過程中にウエノ・(この場合、基板は
もとより、基板に層が形成されたものを総称してウエノ
〜という)を成長装置から化したりすることがない。
In this way, each of the above-described processes in step 1 is performed continuously in the same vapor phase growth apparatus to produce a single domain high-quality GaAs network.
The 81 layer can be grown on the (100) plane of the substrate, and during this series of processing steps, the 81 layer is grown on the (100) plane of the substrate. ) from the growth device.

上述したSi基板の清浄のための高温熱処理はH中でも
効果があるが、H3のみの雰囲気で行つま た場合には、ペデスタル上に以前の成長時に析出した多
結晶のGaAsが再蒸発してクエ・〜上、特にウニへの
周辺部に細かい粒子として付着し、ウェハの周辺部には
GaAs層が得られなくなる恐れがあったり、或いは、
ウェハの中央部では再付着のGaAsがオーバルディフ
ェクトの核となる恐れがある。従って、この発明では、
熱処理に際し、AsHをHと共に流しAs Haが分解
して得られたz 砒素の圧力により、ペデスタル上に析出した残存GaA
sの再蒸発を抑えることによってウェハ上にGaAsの
細かい粒子が付着するのを防止している。
The above-mentioned high-temperature heat treatment for cleaning the Si substrate is effective even in H3 atmosphere, but if it is performed in an atmosphere of only H3, the polycrystalline GaAs precipitated on the pedestal during the previous growth will re-evaporate and the query - On top of that, there is a risk that it will adhere as fine particles, especially around the periphery of the wafer, and there is a risk that a GaAs layer will not be obtained at the periphery of the wafer, or
At the center of the wafer, redeposited GaAs may become the core of an oval defect. Therefore, in this invention,
During heat treatment, residual GaA precipitated on the pedestal due to the pressure of arsenic, which was obtained by flowing AsH with H and decomposing AsHa.
By suppressing re-evaporation of s, fine GaAs particles are prevented from adhering to the wafer.

このため、ウェハ全面にわたってオーバルディフェクト
のない単一のドメインの高品質のGaAs 成長層を得
ることが出来る。
Therefore, a single domain high quality GaAs growth layer without oval defects can be obtained over the entire wafer surface.

又、低温で成長させるバッファ層であるが、そ7沖合の
成長温度は+00−450℃が適当である。
Furthermore, although the buffer layer is grown at a low temperature, the appropriate growth temperature for the offshore part 7 is +00-450°C.

0(たよりも高い温度にすると高温になるに従ってPl
ソファ層上に成長した目的とするGaAs層の表面が荒
れて結晶性の悪い層となってしまう。また、逆にさらに
低い温度にすると、成長速度が著しく遅くなってしまう
0 (If the temperature is higher than that, Pl will increase as the temperature increases.
The surface of the target GaAs layer grown on the sofa layer becomes rough, resulting in a layer with poor crystallinity. On the other hand, if the temperature is lowered even further, the growth rate will be significantly slowed down.

さらに、バッファ層の厚みを10A以下という薄さにし
たが、これより厚くすると、その上に成長させるGaA
s層にオーバルディフェクトが生じたり単一のドメイン
になりにくくなったりして結晶性が悪くなる。しかし、
薄い方は数原子層程度の薄さとなってもよい。
Furthermore, although the thickness of the buffer layer was made as thin as 10A or less, if it was made thicker than this, the GaA layer would be grown on top of it.
Oval defects occur in the s-layer and it becomes difficult to form a single domain, resulting in poor crystallinity. but,
The thinner layer may be as thin as several atomic layers.

この発明は上述した実施例にのみ限定されるものではな
い。例えば、上述した実施例は81基板上にGaAs層
を成長させる例につき説明したがGe基板上にもSi基
板の場合と同様な処理によって高品質のGaAs層を成
長させることが出来る。その場合には、基板の高温熱処
理時のサセプタ温度を600℃以上好ましくは700’
C前後の温度とすれば充分である。
The invention is not limited to the embodiments described above. For example, although the above embodiment describes an example in which a GaAs layer is grown on an 81 substrate, a high quality GaAs layer can also be grown on a Ge substrate by the same process as that for a Si substrate. In that case, the susceptor temperature during high-temperature heat treatment of the substrate should be set at 600°C or higher, preferably 700°C.
A temperature around C is sufficient.

又、上述した実施例ではMOOVD法を用いてGaAs
層の成長を行ったが他の普通の気相成長法で成長させる
ことも出来る。その場合、原料とし力、例えば、三塩化
砒素(AsCA! a )及びガリウム、(!P、)と
か、Ga、アルシン及び塩酸とかを用いる内とが出来る
In addition, in the above-mentioned embodiment, GaAs was
Although layer growth was performed, other conventional vapor phase growth methods can also be used. In that case, raw materials such as arsenic trichloride (AsCA!a) and gallium (!P), Ga, arsine, and hydrochloric acid can be used.

さらに、キャリアガスとしてH3以外の任意適切なガス
を用いることが出来る。
Additionally, any suitable gas other than H3 can be used as the carrier gas.

(発明の効果) 上述した説明からも明らかなように、この発明によれば
、高温熱処理でSi又はGeの基板の表面を清浄にした
後、低温で(100)基板面上に200A以下という薄
膜のGaAsバッファ層を成長させ、このバッファ層上
に目的とするGaAs層を成長させているので、高品質
のGaAs層を成長させることが出来る。
(Effects of the Invention) As is clear from the above description, according to the present invention, after cleaning the surface of a Si or Ge substrate by high-temperature heat treatment, a thin film of 200A or less is formed on the (100) substrate surface at a low temperature. Since the GaAs buffer layer is grown and the target GaAs layer is grown on this buffer layer, a high quality GaAs layer can be grown.

又、この発明により得られたGaAs層のエッチビット
密度は10  cIL  と少なく、移動度についても
lX1Oc*  の電子密度に対して5200cm V
−s  というようにGaAs上に成長させたGaAs
層に近い値が得られているので、充分各種のGaAsデ
バイスの製作に使用可能である。
In addition, the etch bit density of the GaAs layer obtained by this invention is as low as 10 cIL, and the mobility is 5200 cm V for an electron density of lX1Oc*.
-s GaAs grown on GaAs
Since a value close to that of the layer is obtained, it can be used to fabricate a wide variety of GaAs devices.

さらに、Si又は一基板はGaAs基板では得られない
大面積の基板が得られるので、この基板上にこの発明に
よりGaAsを成長させて大面積でしかも高品質のGa
As層を得ることが出来、このGaAs層に大規模集積
回路や或いは三次元回路を作トド込んだり、又、このG
aAs層を用いてソーラぞトを作り上げることが出来る
Furthermore, since a Si or single substrate can provide a substrate with a large area that cannot be obtained with a GaAs substrate, by growing GaAs on this substrate according to the present invention, a large area and high quality GaAs substrate can be obtained.
It is possible to obtain an As layer, and it is possible to fabricate large-scale integrated circuits or three-dimensional circuits in this GaAs layer.
Solar grids can be built using aAs layers.

組違したように、基板上にGaAs層を成長させるため
の全処理工程を同一の気相成長装置内で、ウェー・の出
し入れを行うことなく、実施出来るので、ウェハが汚染
されたり損傷したりすることなく、よってこの点からも
高品質のGaAs層が得られる。
As mentioned above, all the processing steps for growing a GaAs layer on a substrate can be performed in the same vapor phase growth apparatus without the need for loading and unloading wafers, which prevents contamination or damage to the wafers. Therefore, from this point as well, a high quality GaAs layer can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の化合物半導体の製造方法の説明に供
するサセプタの温度変化を示す線図である。
FIG. 1 is a diagram showing temperature changes in a susceptor for explaining the compound semiconductor manufacturing method of the present invention.

Claims (1)

【特許請求の範囲】 1、シリコン(Si)又はゲルマニウム(Ge)基板の
(100)面上に砒化ガリウム(GaAs)層をエピタ
キシャル成長させるに当り、 該シリコン又はゲルマニウム基板を、砒素圧の下で及び
前記基板の表面酸化膜を除去して清浄な基板面を得る温
度で、熱処理する工程と、 清浄された該基板上に、450℃以下の温度で、200
Å程度以下の厚さの砒化ガリウムのバッファ層を成長さ
せる工程と、 該バッファ層上に、通常の砒化ガリウム層の成長温度で
、該砒化ガリウム層を成長させる工程と を含むことを特徴とする化合物半導体の成長方法。 2、各前記工程を同一の成長装置内で連続して行うこと
を特徴とする特許請求の範囲第1項記載の化合物半導体
の成長方法。
[Claims] 1. In epitaxially growing a gallium arsenide (GaAs) layer on the (100) plane of a silicon (Si) or germanium (Ge) substrate, the silicon or germanium substrate is grown under arsenic pressure and a step of heat-treating the substrate at a temperature that removes the surface oxide film of the substrate to obtain a clean substrate surface;
The method is characterized by comprising the steps of: growing a gallium arsenide buffer layer with a thickness of about Å or less; and growing the gallium arsenide layer on the buffer layer at a normal gallium arsenide layer growth temperature. How to grow compound semiconductors. 2. The method for growing a compound semiconductor according to claim 1, wherein each of the steps is performed successively in the same growth apparatus.
JP59191672A 1984-09-14 1984-09-14 Growing method of compound semiconductor Granted JPS6170715A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59191672A JPS6170715A (en) 1984-09-14 1984-09-14 Growing method of compound semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59191672A JPS6170715A (en) 1984-09-14 1984-09-14 Growing method of compound semiconductor

Publications (2)

Publication Number Publication Date
JPS6170715A true JPS6170715A (en) 1986-04-11
JPH0236060B2 JPH0236060B2 (en) 1990-08-15

Family

ID=16278536

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59191672A Granted JPS6170715A (en) 1984-09-14 1984-09-14 Growing method of compound semiconductor

Country Status (1)

Country Link
JP (1) JPS6170715A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6430210A (en) * 1987-07-27 1989-02-01 Nippon Telegraph & Telephone Method for growing iii-v compound semiconductor
US5438951A (en) * 1992-12-21 1995-08-08 Nippon Steel Corporation Method of growing compound semiconductor on silicon wafer
EP0723039A2 (en) 1995-01-19 1996-07-24 Nippon Steel Corporation Compound semiconductor substrate and process of producing same
JP2010225981A (en) * 2009-03-25 2010-10-07 Fujitsu Ltd Optical semiconductor device, integrated device, and method for manufacturing optical semiconductor device
JP2019517732A (en) * 2016-04-07 2019-06-24 アイクストロン、エスイー Formation of layers on semiconductor substrates

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0579586U (en) * 1991-05-28 1993-10-29 エムケー精工株式会社 Light emitting diode display
JPH058961U (en) * 1991-07-15 1993-02-05 スタンレー電気株式会社 Surface mount LED

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6430210A (en) * 1987-07-27 1989-02-01 Nippon Telegraph & Telephone Method for growing iii-v compound semiconductor
US5438951A (en) * 1992-12-21 1995-08-08 Nippon Steel Corporation Method of growing compound semiconductor on silicon wafer
EP0723039A2 (en) 1995-01-19 1996-07-24 Nippon Steel Corporation Compound semiconductor substrate and process of producing same
US5833749A (en) * 1995-01-19 1998-11-10 Nippon Steel Corporation Compound semiconductor substrate and process of producing same
JP2010225981A (en) * 2009-03-25 2010-10-07 Fujitsu Ltd Optical semiconductor device, integrated device, and method for manufacturing optical semiconductor device
JP2019517732A (en) * 2016-04-07 2019-06-24 アイクストロン、エスイー Formation of layers on semiconductor substrates

Also Published As

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JPH0236060B2 (en) 1990-08-15

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