JPS6168620A - Resetting controller - Google Patents

Abstract

PURPOSE:To reset a system securely by providing a device which detects the signal logic on a data transfer strobe signal line and inhibiting the transmission of a reset pulse for a specific time. CONSTITUTION:The resetting controller 16, a system resetting switch 1, and a common bus 3 are provided so as to initialize controllers 7a-7c. This controller 6 consists of a resetting detector 8, the 1st clocking device 11, a flip-flop 14, the 2nd clocking device 15, and gate devices 10, 12, and 13. Then, a data transfer strobe signal is sent out at the operation point of time of said switch 1 and a system resetting signal for carrying on the transmission for the 2nd specific time D2 after the 1st specific time D1 is elapsed is sent out 4 unless the 1st specific time D1 is elapsed, so the transfer time of data is secured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reset control device for initializing a control device 1 connected by a common bus.

[Conventional technology]

A conventional device of this type is shown in FIG. In the figure (1) is the system reset switch% (
2) Harisett pulse generation circuit, (3) common bus,
(4) is the reset signal M in the common bus (3), (5)
is the data transfer strobe signal line in the common bus (3),
(6) is the data signal line in the common bus (3), (7a)
l (7b) and (7c) are control devices connected to the common bus (3), respectively.

In the device shown in Fig. 3, when the operator fully operates the system reset switch (1), a square wave pulse is generated by the reset pulse generation circuit (2), and the control signal is transmitted via the reset signal line (4). Apparatus (7a).

A reset signal is sent to (7b) and (7c) to initialize these control devices (7a), (7b) and (7c).

At this time, if a data transfer strobe signal is being sent to the data transfer strobe signal line (5), the control device that is sending the data transfer strobe signal is initialized, so the data transfer strobe signal is not sent. The transmission of data sent from the control device to the data signal line (6) is also stopped.

[Problem that the invention seeks to solve]

As described above, the conventional reset control device uses a common bus (3
) in the data transfer strobe signal line 5) is generated and sent to the common bus (3) regardless of whether the signal on the data transfer strobe signal line 5) is significant or not. While the signal on the data transfer strobe signal line (5) is significant, the associated control device is reset;
There was a problem that data transfer was not guaranteed.

This invention was made in order to solve the above-mentioned problems, and provides a reset control device that can guarantee the transfer of data that was being transferred at the time when the operator operated the system reset switch. is intended to provide.

[Means for solving problems]

In this invention, a device is provided for detecting the signal logic on the data transfer strobe signal line, and by completely blocking transmission of the reset pulse for a predetermined time from the time when the signal logic becomes significant, the data is transferred only during the predetermined time. Guaranteed transfer.

[Effect]

If the data transfer strobe signal is not significant at the time the operator operates the system reset switch, or even if it is significant, a predetermined time has already elapsed since it became significant, the reset pulse is immediately sent. , and if the predetermined time has not elapsed, a reset pulse is sent out at the time when the predetermined time has elapsed. [Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.
The same symbols as in the figure indicate the same or equivalent parts, (8) is a reset detector, (9) and (13) are respective OR circuits, (
10), (12) are AND circuits, (11) is a first timer, (14) is a flip-flop, (15) is a second timer, and (10), (12).

(13) are collectively referred to as a gate device, and (8) to (15)
) is called the reset control device.

FIG. 2 is an operation time diagram showing an example of the signal waveform of each part of the circuit in FIG. 1.
The same figure (bl is the output of the clock (11), the same figure (cl is the output of the reset detector (8), the same figure (d) is the OR circuit (13)
), and in the same figure (el indicates the output of the flip-flop (14).D and D2if are the clocks (11), respectively.

(15) are the delay times of the first . This is called a second predetermined time. When the reset detector (8) detects that the system reset switch (1) has been operated, the reset detector (8) sends out a rectangular wave signal shown in FIG. 2 (cl). , that is, if the output of the AO circuit (9) is logic "0" at time t2, that is, if there is no signal on the data transfer strobe signal line (5), the output of the reset detector (8) is the AND circuit. (
10) and is input to the OR circuit (13). Also, at time t2', the output of the OR circuit (9) (Fig. 2 (a))
Both the output of the clock (11) (Fig. 2 (b)) are logical
1'', the output of the reset detector (8) passes through the AND circuit (12) and is input to the OR circuit (13).

t as shown in FIG. When the relationship of
The output of 13) is as shown in FIG. 2 fdl. Second
At the falling point of the waveform shown in the figure (di), the flip-flop (1
4) is set and reset after D2 time.

The signal shown in FIG. 2 tel is applied to the reset signal line (4), and while the signal is at logic "1"
), (7b), and (7c) are reset, and the output of the OR circuit (9) becomes logic "0".

As described above, if any of the data transfer strobe signals is logic "1" at the time when the operation of the system reset switch (1) is detected, the data transfer strobe signal is Interval logic “1”
This 00 hour reservation ensures that the system
Any data transfers that need to be completed before resetting can be completed.

Also, during the period when the output of the flip-flop (14) is "1", one of the control devices sends out a data transfer strobe signal on the data transfer strobe signal line (5), and the output logic of the OR circuit (9) changes. Even if it becomes "1", the output of the 7 lip-flop (14) is not affected in any way.

The above is a reset control device (with one flip 70 knob for one system reset switch (1)).
16) has been explained, but the present invention is not limited to this.
It may have multiple system reset switches or it may have multiple flip-flops.

〔Effect of the invention〕

As described above, according to the present invention, the system reset
If the data transfer strobe signal is being sent out at the time the switch is operated, and the first predetermined time D has not yet elapsed from the start point of sending the data transfer strobe signal, the second predetermined time D is elapsed. The entire system reset signal is sent out for a period of time L)2, so
It is possible to secure the transfer time for data that needs to be completed before the system reset, and it is also possible to reliably execute the system reset.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an operation time diagram showing signals of each part of the circuit in FIG. 1, and FIG.
The figure is a block diagram showing a conventional device. (1) is the system reset switch, (4) is the reset signal line, (5) is the data transfer strobe signal, (8
) is the reset detector, (9) is the OR circuit, (10),
(12), (13) are Fi agate devices, and (14) are flip-flops. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] A reset control device for controlling system reset of a computer, which detects operation of a system reset switch and sends out a logic "1" signal for a predetermined time period from the time of detection. a detector; an OR circuit that outputs a logic "1" signal when any of the data transfer strobe signals on the plurality of data transfer strobe signal lines is significant; and when the output of this OR circuit is logic "0" and the above When the output is logic "1" and the period in which the output is logic "1" has exceeded the first predetermined time D_1, a gate device that allows the output of the reset detector to pass; A reset control device, characterized in that it comprises means for generating a system reset signal that lasts for a second predetermined time D_2 from the starting point of passing through the gate device.